KR20150040493A - Method for forming pattern in semiconductor device - Google Patents

Method for forming pattern in semiconductor device Download PDF

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Publication number
KR20150040493A
KR20150040493A KR20130119067A KR20130119067A KR20150040493A KR 20150040493 A KR20150040493 A KR 20150040493A KR 20130119067 A KR20130119067 A KR 20130119067A KR 20130119067 A KR20130119067 A KR 20130119067A KR 20150040493 A KR20150040493 A KR 20150040493A
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South Korea
Prior art keywords
exposure
region
layer
forming
mask
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KR20130119067A
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Korean (ko)
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조병욱
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에스케이하이닉스 주식회사
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Publication of KR20150040493A publication Critical patent/KR20150040493A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

The present technique relates to a method for forming pattern in semiconductor device to be able to make the constant pattern while improving pitch. The method to form the pattern of the semiconductor device according to the technique includes: a step to form photoresist on an etching object layer; a step to carry out the first exposure light on the phtoresist layer; a step to perform the second exposure light to form the overlapped exposure light area overlapped with the above first exposure light on the photoresist layer; a step to form the photoresist pattern while proceeding the developing process to remove the overlapped exposure light area; and a step to etch the above etching object layer by the above photoresist pattern.

Description

METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly, to a pattern forming method of a semiconductor device.

Photolithography technology is widely used for transferring pattern shapes onto wafers in the manufacture of semiconductor devices. However, as the degree of integration of a semiconductor device rapidly increases and the design rule is rapidly reduced, various problems have arisen due to the resolution limit of photolithography. As the design rule becomes smaller, the CD (Critical Dimension) of the pattern to be resolved becomes smaller, but the patterning itself is inevitable due to the limit of the resolving power that can be obtained by a single exposure process.

The present embodiments provide a method of forming a pattern of a semiconductor device capable of forming a uniform pattern while increasing the pitch.

A method of patterning a semiconductor device according to an embodiment of the present invention includes: forming a photoresist layer on a layer to be etched; Performing a primary exposure on the photoresist layer; performing a secondary exposure on the photoresist layer to form a double exposure region overlapping the primary exposure; Forming a photoresist pattern by performing a developing process to remove the double exposure region; And etching the etching target layer with the photoresist pattern. The primary exposure and the secondary exposure can be performed by forming a line-shaped exposure area extending in the zigzag direction.

A method of forming a pattern of a semiconductor device according to an embodiment of the present invention includes: forming a mold layer on a substrate; Forming a photoresist layer on the mold layer; Forming a first exposure region extending in the zigzag direction by first exposing the photoresist layer; Forming a second exposure area extending in a zigzag direction by performing a second exposure so as to form a double exposure area overlapping the first exposure area; Forming a photoresist pattern by performing a developing process to remove the double exposure region; Etching the mold layer by the photoresist pattern to form a plurality of holes; And forming a storage node in each of the plurality of holes.

A mask according to an embodiment of the present invention is a mask for patterning a plurality of holes, comprising: a first mask including a first line-shaped light-transmitting region including a plurality of first bending parts and extending in a zigzag direction; And a second mask including a second line-shaped light-transmitting region extending in a zigzag direction including a plurality of second bending portions overlapping with the first bending portion, wherein the first bending portion and the second bending portion A double exposure can be performed on the overlapping area.

The above-described technique has the effect of improving the process margin while reducing the cost by uniformly forming the pattern in the zigzag direction by the double exposure method.

Therefore, it is possible to improve the characteristics and reliability of the semiconductor device and enable the high integration of the semiconductor device.

1A to 1C are views showing a pattern forming method according to the first embodiment.
2A to 2C are views for explaining a double exposure method according to the first embodiment.
3 is a view showing a plurality of pattern arrays according to the first embodiment.
4A is a view for explaining a double exposure method according to the second embodiment.
4B is a view showing a pattern array formed using the photoresist layer on which the double exposure shown in FIG. 4A is performed.
5A to 5D are views for explaining a double exposure method according to the third embodiment.
6A to 6G are views showing an example of a method of forming a plurality of capacitors by applying the third embodiment.
7 is a schematic view showing a memory card;
8 is a block diagram showing an electronic system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

1A to 1C are views showing a pattern forming method according to the first embodiment.

As shown in FIG. 1A, an etch target layer 102 is formed on a substrate 101. The substrate 101 may include a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate. Although not shown, a conductive structure including a conductive layer or a conductive layer may further be formed on the substrate 101. In addition, an impurity region may be formed in the substrate 101. Further, an insulating layer may be further formed on the substrate 101.

The etch target layer 102 is a material that is etched by a subsequent etch process. The etch target layer 102 may comprise a silicon layer, a metal layer, silicon oxide, or silicon nitride. For example, the etch target layer 102 may be formed of phosphor silicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetra ethyl ortho silicate (TEOS) Or high density plasma-chemical vapor deposition (HDP-CVD) oxide. Hereinafter, in the first embodiment, the etching target layer 102 may include silicon oxide.

A photoresist layer 130 is formed on the etch target layer 102. A double exposure (140) is performed on the photoresist layer (130). Thus, a double exposure region 133 is formed in the photoresist layer 130. [ Although not shown, a hard mask layer may be further formed between the etching target layer 102 and the photoresist layer 130.

As shown in Fig. 1B, the developing step 150 is performed. The double exposure area 133 is selectively removed by the developing process 150. [ Thus, a photoresist pattern 160 including a plurality of open portions 161 is formed. The plurality of open portions 161 is a space from which the double exposure region 133 is removed.

The etching target layer 102 is etched by the photoresist pattern 160, as shown in FIG. Accordingly, a plurality of patterns 170 are formed on the etching target layer 102. The plurality of patterns 170 may be the same as the shapes of the double exposure region 133 and the open portion 161. [

2A to 2C are views for explaining a double exposure method according to the first embodiment.

Referring to FIGS. 2A to 2C, the exposure mask includes a first exposure mask 110 and a second exposure mask 120. A double exposure 140 is performed on the photoresist layer 130 '(FIG. 2A) by the first exposure mask 110 and the second exposure mask 120.

As shown in FIG. 2A, the first exposure mask 110 includes a light shielding region 111 and a plurality of first light-transmissive regions 112. The first light-transmissive region 112 is a line-shaped light-transmissive region extending in the first direction (X). The first light-transmitting region 112 has a first width W1. A plurality of first light-transmissive regions 112 are formed with a first interval S1.

2B, the second exposure mask 120 includes a light shielding region 121 and a plurality of second light-transmissive regions 122. As shown in FIG. The second light-transmissive region 122 is a line-shaped light-transmissive region extending in the second direction Y. And the second light-transmissive region 122 has a second width W2. A plurality of second light-transmissive regions 122 are formed with a second interval S2.

The first width W1 and the second width W2 are the same (W1 = W2). Also, the first interval S1 and the second interval S2 are the same (S1 = S2). The first direction X and the second direction Y may intersect. The first direction X and the second direction Y may intersect in the vertical direction, or may intersect in the diagonal direction.

A first exposure is performed using the first exposure mask 110 and a second exposure is performed using the second exposure mask 120. [ When the first exposure and the second exposure are performed, the first light-transmissive region 112 and the second light-transmissive region 122 are overlapped and exposed.

2C is a view showing a photoresist layer 130 in which a dual exposure 140 is performed by a first exposure mask 110 and a second exposure mask 120. FIG.

Referring to FIG. 2C, the photoresist layer 130 having the double exposure 140 applied thereto includes an exposure region 134 and a non-exposure region 135. The exposure region 134 includes a first exposure region 131, a second exposure region 132, and a dual exposure region 133. The first exposure with the first exposure mask 110 is performed, and thus the first exposure area 131 is formed. The second exposure with the second exposure mask 120 is performed, and thus the second exposure area 132 is formed. A double exposure area 133 is formed in a region where the first exposure area 131 and the second exposure area 132 overlap. The double exposure area 133 is an area removed by the subsequent development process ('150' in FIG. 2B). The double exposure region 133 may have various shapes. For example, the double exposure area 133 may have the form of a square, a rectangle, an oval or a circle. The double exposure region 133 can be variously implemented according to the shape, width, and interval of the first and second transparent regions 112 and 122. The area of the double exposure area 133 can be adjusted by adjusting the first width W1 and the second width W2. The high density double exposure area 133 can be formed by adjusting the first interval S1 and the second interval S2.

3 is a view showing a plurality of pattern arrays according to the first embodiment.

As shown in FIG. 3, a plurality of patterns 170 are uniformly formed in the etching target layer 102 with a uniform size and spacing by an etching process using a photoresist pattern 160 on which double exposure is performed.

4A is a view for explaining a double exposure method according to the second embodiment.

As shown in FIG. 4A, the double exposure according to the second embodiment is performed using the first exposure mask and the second exposure mask similarly to the first embodiment. A plurality of first exposure regions 231 and a plurality of second exposure regions 232 are formed in the photoresist layer 230 by double exposure. The first exposure area 231 is an independent form extending in the first direction, and the plurality of first exposure areas 231 form an irregular array. The second exposure area 232 is an independent form extending in the second direction, and the plurality of second exposure areas 232 form an irregular array.

A double exposure area 233 is formed by the first exposure area 231 and the second exposure area 232. [ The plurality of double exposure areas 233 form an irregular array.

As such, the first exposure area 231, the second exposure area 232, and the double exposure area 233 are mixed in the form of uniform spacing and the form of uneven spacing.

4B is a view showing a pattern array formed using the photoresist layer 230 in which the double exposure shown in FIG. 4A is performed.

Referring to FIG. 4B, a developing process is performed on the photoresist layer 230 in the same manner as in the first embodiment. The etching target layer 202 is etched by the photoresist pattern. Accordingly, a plurality of patterns 270 are formed on the etching target layer 202. The plurality of patterns 270 include a plurality of patterns 270 having uniform intervals and a plurality of patterns 270 having nonuniform intervals.

5A to 5D are views for explaining a double exposure method according to the third embodiment.

Referring to FIGS. 5A to 5C, the exposure mask includes a first exposure mask 310 and a second exposure mask 320.

5A, the first exposure mask 310 includes a non-light-transmitting region 321 and a first light-transmitting region 312 in the form of a line. The first light-transmitting region 312 is a line-shaped light-transmitting region extending in the zigzag direction. For example, the first light-transmitting region 312 is a zigzag shape having a plurality of first bending parts 313. The plurality of first bending parts 313 may have the form of a vertex. In addition, the plurality of first bending parts 313 may have a rounding type.

As shown in FIG. 5B, the second exposure mask 320 includes a non-light-transmitting region 321 and a second light-transmitting region 322 in the form of a line. The second light-transmissive region 322 is a line-shaped light-transmissive region extending in the zigzag direction. For example, the second light transmitting region 322 is a zigzag shape having a plurality of second bending parts 323. The plurality of second bending parts 323 may have the form of a vertex. In addition, the plurality of second bending parts 323 may have a rounded shape.

The widths of the first light-transmitting region 322 and the second light-transmitting region 322 are the same.

The first exposure is performed using the first exposure mask 310 and the second exposure is performed using the second exposure mask 320. [ The exposure positions of the first exposure mask 310 and the second exposure mask 320 are adjusted such that the first light-transmitting region 312 and the second light-transmitting region 322 overlap each other when the first exposure and the second exposure are performed, do.

5C is a view showing the photoresist layer 330 in which the double exposure is performed by the first exposure mask 310 and the second exposure mask 320. FIG.

Referring to FIG. 5C, the photoresist layer 330 having the double exposure 334 applied thereto includes an exposure region 334 and a non-exposure region 335. The exposure region 334 includes a first exposure region 331, a second exposure region 332, and a dual exposure region 333. The first exposure with the first exposure mask 310 is performed, and thus the first exposure area 331 is formed. A second exposure by the second exposure mask 320 is performed, and thus a second exposure area 332 is formed. A double exposure area 333 is formed in a region where the first exposure area 331 and the second exposure area 332 overlap. The double exposure area 333 is an area which is removed by a subsequent developing process. The double exposure area 333 may have various shapes. For example, the double exposure area 333 may have the form of a square, a rectangle, an ellipse or a circle. The dual exposure region 333 can be variously implemented according to the shape, width, and interval of the first and second transparent regions 312 and 322.

5C, the exposure positions of the first exposure mask 310 and the second exposure mask 320 are adjusted so that the first bending part 313 and the second bending part 323 are overlapped with each other for the double exposure area 333, . The plurality of double exposure areas 333 overlapping the first bending part 313 and the second bending part 323 have a certain area. The plurality of double exposure regions 333 are regions where open portions are formed by a subsequent patterning process. The dual exposure region 333 may be implemented variously according to the shapes of the first bending part 313 and the second bending part 323.

5D is a diagram showing a plurality of pattern arrays according to the third embodiment.

As shown in FIG. 5D, a plurality of patterns 370 are uniformly formed in the etching target layer 302 with a uniform size and spacing by an etching process using the photoresist pattern 330 on which the double exposure is performed.

As described above, when the double exposure is performed using the first exposure mask 310 and the second exposure mask 320 having a zigzag shape light-transmitting region, the resolution P can be increased by about 1.43 times . Thus, it is possible to realize the high-density pattern 370 and secure the process margin.

6A to 6G are views showing an example of a method of forming a plurality of capacitors by applying the third embodiment.

As shown in Fig. 6A, an interlayer insulating layer 12 is formed on a substrate 11. Fig. Although not shown, before forming the interlayer insulating layer 12, transistors and bit lines can be formed. A plurality of contact holes (not shown) are formed in the interlayer insulating layer 12. A contact plug 13 is formed in the contact hole. The contact plug 13 may comprise a silicon-containing layer, a metal-containing layer, or a laminated structure of a silicon-containing layer and a metal-containing layer. For example, the contact plug 13 may be formed of a stacked structure of a polysilicon layer, a metal silicide layer, and a metal layer. The metal silicide layer may comprise a cobalt silicide layer. The metal layer may comprise a tungsten layer.

A mold layer (14) is formed on the contact plug (13) and the interlayer insulating layer (12). The mold layer 14 may comprise a layer of silicon oxide, silicon nitride or silicon oxide and silicon nitride. For example, the mold layer 14 may be formed of phosphor silicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetra ethyl ortho silicate (TEOS), plasma enhanced- Or high density plasma-chemical vapor deposition (HDP-CVD) oxide.

A hard mask layer (15A) is formed on the mold layer (14). The hard mask layer 15A becomes an etch barrier used when the mold layer 14 is etched. Thus, the hard mask layer 15A may be formed of a material having an etch selectivity relative to the mold layer 14. [ The hard mask layer 15A may comprise a single layer or a multilayer structure of two or more layers. For example, the hard mask layer 15A may be formed in a multilayer structure by stacking an amorphous carbon layer and a silicon oxynitride.

A photoresist layer 16A is formed on the hard mask layer 15A.

As shown in FIG. 6B, a first exposure (17) is performed. The first exposure region 18 is formed in the photoresist layer 16A by the primary exposure 17. [ The first exposure area 18 has a zigzag shape. The first exposure mask 310 shown in FIG. 5A may be applied for the primary exposure 17. [

As shown in Fig. 6C, the secondary exposure 19 is performed. A second exposure area (not shown) is formed in the photoresist layer 16A by the secondary exposure 19. The second exposure area has a zigzag shape. The second exposure mask 320 shown in Fig. 5B may be applied for the secondary exposure 19. [

As described above, the dual exposure region 21 is formed by the primary exposure 17 and the secondary exposure 19. The photoresist layer 16A includes a dual exposure area 21 and a single exposure area /

As shown in Fig. 6D, the developing step 22 is performed. The double exposure area 21 is selectively developed by the development step (22). The single exposure area / non-exposure area 20 remains unremoved by the development step 22. [

As described above, the photoresist pattern 16 is formed by the developing step 22. The photoresist pattern 16 has a plurality of open portions 23. The plurality of open portions 23 are portions where the double exposure region 21 is removed.

The developing process 22 uses a developer capable of selectively developing the double exposure region 21.

As shown in FIG. 6E, the hard mask layer 15A is etched by the photoresist pattern 16. Subsequently, the mold layer 14 is etched. Thus, the hard mask pattern 15 is formed. A plurality of hole patterns 24 are formed by the etching of the mold layer 14.

As shown in FIG. 6F, the photoresist pattern 16 and the hard mask pattern 15 are removed. The photoresist pattern 16 may be removed by a stripping process. The hard mask pattern 15 can be removed by a cleaning process.

As described above, the plurality of hole patterns 24 are formed with uniform size and uniform spacing.

As shown in FIG. 6G, a storage node 25 is formed in the hole 24. The storage node 25 may have a pillar shape. In another embodiment, the storage node 25 may have a cylinder shape.

As a comparative example of these embodiments, there is a technology such as EUV, DPT (Double Patterning Technology) or SPT (Spacer Patterning Technology). DPT is a method of dividing the patterning into two portions in order to obtain a pattern below the limit resolution. SPT is a method of forming a spacer around a pattern after pattern formation, and etching a lower layer using a spacer as an etching barrier.

However, in the case of a hole array such as a storage node (SN) of a DRAM, it is impossible to implement a pattern by the EUV, DPT, or SPT technology as the pattern size becomes smaller.

As a result, when the staggered LLE method is applied as in the present embodiments, the SN patterning of the DRAM is possible by increasing the patterning pitch.

The semiconductor device according to the above-described embodiments may be applied to a dynamic random access memory (DRAM), and the present invention is not limited thereto. For example, a static random access memory (SRAM), a flash memory, a ferroelectric random access memory (FeRAM) (Magnetic Random Access Memory), and a PRAM (Phase Change Random Access Memory).

7 is a schematic view showing a memory card;

Referring to FIG. 7, the memory card 400 may include a controller 410 and a memory 420. Controller 410 and memory 420 may exchange electrical signals. For example, the memory 420 and the controller 410 can send and receive data in response to a command from the controller 410. [ Accordingly, the memory card 400 can store data in the memory 420 or output the data from the memory 420 to the outside. The memory 420 may include a semiconductor device having a pattern as described above. The memory card 400 may be used as a data storage medium of various portable devices. For example, the memory card 400 may be a memory stick card, a smart media card (SM), a secure digital (SD) card, a mini secure digital card, mini SD), or a multi media card (MMC).

8 is a block diagram showing an electronic system.

8, an electronic system 500 may include a processor 510, an input / output device 530, and a chip 520, which may be in data communication with each other using bus 540 . The processor 510 may be responsible for executing the program and controlling the electronic system 500. The input / output device 530 may be used to input or output data of the electronic system 500. The electronic system 500 may be connected to an external device, e.g., a personal computer or network, using the input / output device 530 to exchange data with the external device. The chip 520 may store code and data for operation of the processor 510 and may process some of the operations provided in the process 510. [ For example, the chip 520 may include a semiconductor device having the above-described pattern. The electronic system 500 may comprise various electronic control devices that require the chip 520 and may be a mobile phone, an MP3 player, navigation, a solid state disk (SSD) ), Household appliances, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

310: first exposure mask
320: second exposure mask
330: photoresist layer
333: Double exposure area

Claims (11)

Forming a photoresist layer on the etch target layer;
Performing a primary exposure on the photoresist layer
Subjecting the photoresist layer to a secondary exposure so as to form a double exposure area overlapping with the primary exposure;
Forming a photoresist pattern by performing a developing process to remove the double exposure region; And
Etching the etching target layer with the photoresist pattern
And patterning the semiconductor substrate.
The method according to claim 1,
Wherein a line-shaped exposure region extending in a zigzag direction is formed in the primary exposure and the secondary exposure.
The method according to claim 1,
Wherein the primary exposure and the secondary exposure proceed while moving the exposure position using one exposure mask. The method according to claim 1,
Wherein the first exposure and the second exposure proceed by using different first exposure masks and second exposure masks, respectively.
Forming a mold layer on the substrate;
Forming a photoresist layer on the mold layer;
Forming a first exposure region extending in the zigzag direction by first exposing the photoresist layer;
Forming a second exposure area extending in a zigzag direction by performing a second exposure so as to form a double exposure area overlapping the first exposure area;
Forming a photoresist pattern by performing a developing process to remove the double exposure region;
Etching the mold layer by the photoresist pattern to form a plurality of holes; And
Forming a storage node in each of the plurality of holes;
≪ / RTI >
6. The method of claim 5,
Wherein the first exposure region and the second exposure region each include a line-shaped exposure region extending in a zigzag direction.
6. The method of claim 5,
Wherein the first exposure region and the second exposure region each include a line-shaped exposure region extending in a zigzag direction including a plurality of bending portions.
8. The method of claim 7,
Wherein the overlapping exposure region is formed by overlapping the bending portions of the first exposure region and the second exposure region.
6. The method of claim 5,
Wherein the primary exposure and the secondary exposure are performed while moving the exposure position using one exposure mask.
6. The method of claim 5,
Wherein the first exposure and the second exposure proceed using different first exposure masks and second exposure masks, respectively.
In a mask for patterning a plurality of holes,
A first mask including a first line-shaped light-transmitting region including a plurality of first bending parts and extending in a zigzag direction; And
And a second mask including a second line-shaped light-transmitting region extending in a zigzag direction including a plurality of second bending parts overlapping with the first bending part,
Wherein a double exposure is performed on an overlapping area of the first bending part and the second bending part.
KR20130119067A 2013-10-07 2013-10-07 Method for forming pattern in semiconductor device KR20150040493A (en)

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