KR20150040493A - Method for forming pattern in semiconductor device - Google Patents
Method for forming pattern in semiconductor device Download PDFInfo
- Publication number
- KR20150040493A KR20150040493A KR20130119067A KR20130119067A KR20150040493A KR 20150040493 A KR20150040493 A KR 20150040493A KR 20130119067 A KR20130119067 A KR 20130119067A KR 20130119067 A KR20130119067 A KR 20130119067A KR 20150040493 A KR20150040493 A KR 20150040493A
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- South Korea
- Prior art keywords
- exposure
- region
- layer
- forming
- mask
- Prior art date
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly, to a pattern forming method of a semiconductor device.
Photolithography technology is widely used for transferring pattern shapes onto wafers in the manufacture of semiconductor devices. However, as the degree of integration of a semiconductor device rapidly increases and the design rule is rapidly reduced, various problems have arisen due to the resolution limit of photolithography. As the design rule becomes smaller, the CD (Critical Dimension) of the pattern to be resolved becomes smaller, but the patterning itself is inevitable due to the limit of the resolving power that can be obtained by a single exposure process.
The present embodiments provide a method of forming a pattern of a semiconductor device capable of forming a uniform pattern while increasing the pitch.
A method of patterning a semiconductor device according to an embodiment of the present invention includes: forming a photoresist layer on a layer to be etched; Performing a primary exposure on the photoresist layer; performing a secondary exposure on the photoresist layer to form a double exposure region overlapping the primary exposure; Forming a photoresist pattern by performing a developing process to remove the double exposure region; And etching the etching target layer with the photoresist pattern. The primary exposure and the secondary exposure can be performed by forming a line-shaped exposure area extending in the zigzag direction.
A method of forming a pattern of a semiconductor device according to an embodiment of the present invention includes: forming a mold layer on a substrate; Forming a photoresist layer on the mold layer; Forming a first exposure region extending in the zigzag direction by first exposing the photoresist layer; Forming a second exposure area extending in a zigzag direction by performing a second exposure so as to form a double exposure area overlapping the first exposure area; Forming a photoresist pattern by performing a developing process to remove the double exposure region; Etching the mold layer by the photoresist pattern to form a plurality of holes; And forming a storage node in each of the plurality of holes.
A mask according to an embodiment of the present invention is a mask for patterning a plurality of holes, comprising: a first mask including a first line-shaped light-transmitting region including a plurality of first bending parts and extending in a zigzag direction; And a second mask including a second line-shaped light-transmitting region extending in a zigzag direction including a plurality of second bending portions overlapping with the first bending portion, wherein the first bending portion and the second bending portion A double exposure can be performed on the overlapping area.
The above-described technique has the effect of improving the process margin while reducing the cost by uniformly forming the pattern in the zigzag direction by the double exposure method.
Therefore, it is possible to improve the characteristics and reliability of the semiconductor device and enable the high integration of the semiconductor device.
1A to 1C are views showing a pattern forming method according to the first embodiment.
2A to 2C are views for explaining a double exposure method according to the first embodiment.
3 is a view showing a plurality of pattern arrays according to the first embodiment.
4A is a view for explaining a double exposure method according to the second embodiment.
4B is a view showing a pattern array formed using the photoresist layer on which the double exposure shown in FIG. 4A is performed.
5A to 5D are views for explaining a double exposure method according to the third embodiment.
6A to 6G are views showing an example of a method of forming a plurality of capacitors by applying the third embodiment.
7 is a schematic view showing a memory card;
8 is a block diagram showing an electronic system.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .
1A to 1C are views showing a pattern forming method according to the first embodiment.
As shown in FIG. 1A, an
The
A
As shown in Fig. 1B, the developing
The
2A to 2C are views for explaining a double exposure method according to the first embodiment.
Referring to FIGS. 2A to 2C, the exposure mask includes a
As shown in FIG. 2A, the
2B, the
The first width W1 and the second width W2 are the same (W1 = W2). Also, the first interval S1 and the second interval S2 are the same (S1 = S2). The first direction X and the second direction Y may intersect. The first direction X and the second direction Y may intersect in the vertical direction, or may intersect in the diagonal direction.
A first exposure is performed using the
2C is a view showing a
Referring to FIG. 2C, the
3 is a view showing a plurality of pattern arrays according to the first embodiment.
As shown in FIG. 3, a plurality of
4A is a view for explaining a double exposure method according to the second embodiment.
As shown in FIG. 4A, the double exposure according to the second embodiment is performed using the first exposure mask and the second exposure mask similarly to the first embodiment. A plurality of
A
As such, the
4B is a view showing a pattern array formed using the
Referring to FIG. 4B, a developing process is performed on the
5A to 5D are views for explaining a double exposure method according to the third embodiment.
Referring to FIGS. 5A to 5C, the exposure mask includes a
5A, the
As shown in FIG. 5B, the
The widths of the first light-transmitting
The first exposure is performed using the
5C is a view showing the
Referring to FIG. 5C, the
5C, the exposure positions of the
5D is a diagram showing a plurality of pattern arrays according to the third embodiment.
As shown in FIG. 5D, a plurality of
As described above, when the double exposure is performed using the
6A to 6G are views showing an example of a method of forming a plurality of capacitors by applying the third embodiment.
As shown in Fig. 6A, an
A mold layer (14) is formed on the contact plug (13) and the interlayer insulating layer (12). The
A hard mask layer (15A) is formed on the mold layer (14). The
A
As shown in FIG. 6B, a first exposure (17) is performed. The
As shown in Fig. 6C, the
As described above, the
As shown in Fig. 6D, the developing
As described above, the
The developing
As shown in FIG. 6E, the
As shown in FIG. 6F, the
As described above, the plurality of
As shown in FIG. 6G, a
As a comparative example of these embodiments, there is a technology such as EUV, DPT (Double Patterning Technology) or SPT (Spacer Patterning Technology). DPT is a method of dividing the patterning into two portions in order to obtain a pattern below the limit resolution. SPT is a method of forming a spacer around a pattern after pattern formation, and etching a lower layer using a spacer as an etching barrier.
However, in the case of a hole array such as a storage node (SN) of a DRAM, it is impossible to implement a pattern by the EUV, DPT, or SPT technology as the pattern size becomes smaller.
As a result, when the staggered LLE method is applied as in the present embodiments, the SN patterning of the DRAM is possible by increasing the patterning pitch.
The semiconductor device according to the above-described embodiments may be applied to a dynamic random access memory (DRAM), and the present invention is not limited thereto. For example, a static random access memory (SRAM), a flash memory, a ferroelectric random access memory (FeRAM) (Magnetic Random Access Memory), and a PRAM (Phase Change Random Access Memory).
7 is a schematic view showing a memory card;
Referring to FIG. 7, the
8 is a block diagram showing an electronic system.
8, an
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.
310: first exposure mask
320: second exposure mask
330: photoresist layer
333: Double exposure area
Claims (11)
Performing a primary exposure on the photoresist layer
Subjecting the photoresist layer to a secondary exposure so as to form a double exposure area overlapping with the primary exposure;
Forming a photoresist pattern by performing a developing process to remove the double exposure region; And
Etching the etching target layer with the photoresist pattern
And patterning the semiconductor substrate.
Wherein a line-shaped exposure region extending in a zigzag direction is formed in the primary exposure and the secondary exposure.
Wherein the primary exposure and the secondary exposure proceed while moving the exposure position using one exposure mask.
Wherein the first exposure and the second exposure proceed by using different first exposure masks and second exposure masks, respectively.
Forming a photoresist layer on the mold layer;
Forming a first exposure region extending in the zigzag direction by first exposing the photoresist layer;
Forming a second exposure area extending in a zigzag direction by performing a second exposure so as to form a double exposure area overlapping the first exposure area;
Forming a photoresist pattern by performing a developing process to remove the double exposure region;
Etching the mold layer by the photoresist pattern to form a plurality of holes; And
Forming a storage node in each of the plurality of holes;
≪ / RTI >
Wherein the first exposure region and the second exposure region each include a line-shaped exposure region extending in a zigzag direction.
Wherein the first exposure region and the second exposure region each include a line-shaped exposure region extending in a zigzag direction including a plurality of bending portions.
Wherein the overlapping exposure region is formed by overlapping the bending portions of the first exposure region and the second exposure region.
Wherein the primary exposure and the secondary exposure are performed while moving the exposure position using one exposure mask.
Wherein the first exposure and the second exposure proceed using different first exposure masks and second exposure masks, respectively.
A first mask including a first line-shaped light-transmitting region including a plurality of first bending parts and extending in a zigzag direction; And
And a second mask including a second line-shaped light-transmitting region extending in a zigzag direction including a plurality of second bending parts overlapping with the first bending part,
Wherein a double exposure is performed on an overlapping area of the first bending part and the second bending part.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR20130119067A KR20150040493A (en) | 2013-10-07 | 2013-10-07 | Method for forming pattern in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR20130119067A KR20150040493A (en) | 2013-10-07 | 2013-10-07 | Method for forming pattern in semiconductor device |
Publications (1)
Publication Number | Publication Date |
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KR20150040493A true KR20150040493A (en) | 2015-04-15 |
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KR20130119067A KR20150040493A (en) | 2013-10-07 | 2013-10-07 | Method for forming pattern in semiconductor device |
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KR (1) | KR20150040493A (en) |
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2013
- 2013-10-07 KR KR20130119067A patent/KR20150040493A/en not_active Application Discontinuation
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