KR20150038328A - 1들을 최하위 비트들이 되도록 풀링하면서 비트들을 좌측으로 시프팅하기 위한 명령어 - Google Patents

1들을 최하위 비트들이 되도록 풀링하면서 비트들을 좌측으로 시프팅하기 위한 명령어 Download PDF

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Publication number
KR20150038328A
KR20150038328A KR1020157004840A KR20157004840A KR20150038328A KR 20150038328 A KR20150038328 A KR 20150038328A KR 1020157004840 A KR1020157004840 A KR 1020157004840A KR 20157004840 A KR20157004840 A KR 20157004840A KR 20150038328 A KR20150038328 A KR 20150038328A
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South Korea
Prior art keywords
operand
vector
register
processor
registers
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Abandoned
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KR1020157004840A
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English (en)
Korean (ko)
Inventor
미하일 플로트니코브
이고르 에르몰라에브
안드레이 나라이킨
로버트 발렌타인
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인텔 코포레이션
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Publication of KR20150038328A publication Critical patent/KR20150038328A/ko
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
KR1020157004840A 2012-09-28 2013-06-25 1들을 최하위 비트들이 되도록 풀링하면서 비트들을 좌측으로 시프팅하기 위한 명령어 Abandoned KR20150038328A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/630,131 US9122475B2 (en) 2012-09-28 2012-09-28 Instruction for shifting bits left with pulling ones into less significant bits
US13/630,131 2012-09-28
PCT/US2013/047669 WO2014051782A1 (en) 2012-09-28 2013-06-25 Instruction for shifting bits left with pulling ones into less significant bits

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020167030379A Division KR101817459B1 (ko) 2012-09-28 2013-06-25 1들을 최하위 비트들이 되도록 풀링하면서 비트들을 좌측으로 시프팅하기 위한 명령어

Publications (1)

Publication Number Publication Date
KR20150038328A true KR20150038328A (ko) 2015-04-08

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ID=50386382

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020157004840A Abandoned KR20150038328A (ko) 2012-09-28 2013-06-25 1들을 최하위 비트들이 되도록 풀링하면서 비트들을 좌측으로 시프팅하기 위한 명령어
KR1020167030379A Active KR101817459B1 (ko) 2012-09-28 2013-06-25 1들을 최하위 비트들이 되도록 풀링하면서 비트들을 좌측으로 시프팅하기 위한 명령어

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020167030379A Active KR101817459B1 (ko) 2012-09-28 2013-06-25 1들을 최하위 비트들이 되도록 풀링하면서 비트들을 좌측으로 시프팅하기 위한 명령어

Country Status (7)

Country Link
US (1) US9122475B2 (enExample)
JP (2) JP6092400B2 (enExample)
KR (2) KR20150038328A (enExample)
CN (1) CN104919432B (enExample)
DE (1) DE112013004800T5 (enExample)
GB (1) GB2518104B (enExample)
WO (1) WO2014051782A1 (enExample)

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US20140189296A1 (en) * 2011-12-14 2014-07-03 Elmoustapha Ould-Ahmed-Vall System, apparatus and method for loop remainder mask instruction
CN103946795B (zh) * 2011-12-14 2018-05-15 英特尔公司 用于生成循环对齐计数或循环对齐掩码的系统、装置和方法
US9606803B2 (en) * 2013-07-15 2017-03-28 Texas Instruments Incorporated Highly integrated scalable, flexible DSP megamodule architecture
US20160179548A1 (en) * 2014-12-22 2016-06-23 Intel Corporation Instruction and logic to perform an inverse centrifuge operation
GB2540941B (en) * 2015-07-31 2017-11-15 Advanced Risc Mach Ltd Data processing
EP3125108A1 (en) * 2015-07-31 2017-02-01 ARM Limited Vector processing using loops of dynamic vector length
US20180329708A1 (en) * 2015-09-19 2018-11-15 Microsoft Technology Licensing, Llc Multi-nullification
JP2018124877A (ja) * 2017-02-02 2018-08-09 富士通株式会社 コード生成装置、コード生成方法、およびコード生成プログラム
US10481910B2 (en) * 2017-09-29 2019-11-19 Intel Corporation Apparatus and method for shifting quadwords and extracting packed words
US20190196822A1 (en) * 2017-12-21 2019-06-27 Intel Corporation Apparatus and method for shifting packed quadwords and extracting packed words
US10963253B2 (en) * 2018-07-10 2021-03-30 Arm Limited Varying micro-operation composition based on estimated value of predicate value for predicated vector instruction
KR20210066843A (ko) * 2018-09-18 2021-06-07 옵티멈 세미컨덕터 테크놀로지스 인코포레이티드 마스킹된 벡터 명령어 구현 시스템 및 방법
US11275562B2 (en) 2020-02-19 2022-03-15 Micron Technology, Inc. Bit string accumulation
CN112492473B (zh) * 2020-11-04 2022-09-09 杭州士兰微电子股份有限公司 Mems麦克风的信号处理电路及信号处理方法
US11934327B2 (en) * 2021-12-22 2024-03-19 Microsoft Technology Licensing, Llc Systems and methods for hardware acceleration of data masking using a field programmable gate array

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JPH0744532A (ja) * 1991-12-25 1995-02-14 Nec Corp ベクトル処理装置
US5781457A (en) * 1994-03-08 1998-07-14 Exponential Technology, Inc. Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU
CN1149469C (zh) * 1995-08-31 2004-05-12 英特尔公司 支持分组数据的处理器
US5832288A (en) * 1996-10-18 1998-11-03 Samsung Electronics Co., Ltd. Element-select mechanism for a vector processor
US6006315A (en) * 1996-10-18 1999-12-21 Samsung Electronics Co., Ltd. Computer methods for writing a scalar value to a vector
US6446198B1 (en) * 1999-09-30 2002-09-03 Apple Computer, Inc. Vectorized table lookup
JP4374363B2 (ja) * 2006-09-26 2009-12-02 Ｏｋｉセミコンダクタ株式会社 ビットフィールド操作回路
JP2010204913A (ja) * 2009-03-03 2010-09-16 Nec Computertechno Ltd ベクトル処理装置
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US8953785B2 (en) * 2012-09-28 2015-02-10 Intel Corporation Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor
US9128698B2 (en) * 2012-09-28 2015-09-08 Intel Corporation Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction
US9378182B2 (en) * 2012-09-28 2016-06-28 Intel Corporation Vector move instruction controlled by read and write masks

Also Published As

Publication number Publication date
GB2518104B (en) 2020-07-01
US9122475B2 (en) 2015-09-01
KR20160130324A (ko) 2016-11-10
US20140095830A1 (en) 2014-04-03
JP6373425B2 (ja) 2018-08-15
CN104919432B (zh) 2017-12-22
JP2017107587A (ja) 2017-06-15
DE112013004800T5 (de) 2015-06-03
GB2518104A (en) 2015-03-11
JP2015534189A (ja) 2015-11-26
CN104919432A (zh) 2015-09-16
JP6092400B2 (ja) 2017-03-08
KR101817459B1 (ko) 2018-01-11
WO2014051782A1 (en) 2014-04-03
GB201500433D0 (en) 2015-02-25

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