KR20150032458A - transmitter and puncturing method thereof - Google Patents

Abstract

The present invention provides a transmitting apparatus and a puncturing method thereof. The transmitting apparatus includes: an encoding unit which encodes L1 post signaling in a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC); and a puncturing unit which performs puncturing a part of LDPC parity bits in an LDPC codeword generated by LDPC encoding. The number of punctured bits is calculated based on the modulation degree of the L1 post signaling and the number of bits usable for LDPC codeword transmission.

Description

[0001] TRANSMITTER AND PUNCTURING METHOD THEREOF [0002]

The present invention relates to a transmitting apparatus and a puncturing method thereof, and more particularly, to a transmitting apparatus for puncturing and transmitting at least a part of a parity bit and a puncturing method thereof.

In the information society of the 21st century, broadcasting and communication services are in the era of full-scale digitalization, multi-channelization, broadband and high-quality. In particular, with the spread of high-definition digital TVs, PMPs, and mobile broadcasting devices, demand for supporting various receiving methods of digital broadcasting services is increasing.

In response to these demands, the standard group has established various standards and provided various services that satisfy the needs of users. Therefore, it is required to search for ways to provide better services through better performance.

It is an object of the present invention to provide a method and apparatus for puncturing and transmitting a predetermined number of parity bits in consideration of the number of bits of an LDPC code word that can be mapped to a preamble symbol and the modulation order for L1 post- Device and a method of puncturing the same.

In order to achieve the above object, a transmitting apparatus for processing L1 signaling comprising L1 pre-signaling and L1 post signaling according to an embodiment of the present invention includes L1 post-signaling, a BCH (Bose, Chaudhuri, Hocquenghem) And a puncturing unit puncturing at least a part of LDPC parity bits in the LDPC codeword generated by the LDPC encoding, wherein the number of bits to be punctured is equal to the number of bits of the LDPC code, The number of bits available for code word transmission and the modulation order of the L1 post signaling.

Here, the puncturing unit calculates the number of bits available for transmission of the LDPC codeword, and if the number of bits of the LDPC codeword should be temporarily punctured in the LDPC parity bits so that the number of bits is equal to the calculated number of bits, Can be calculated.

Also, the puncturing unit, the number of bits available for the transmission of the LDPC codeword on the basis of the equation for N _{L1post avaiable _ _} can calculate the _bits.

Here, N _{preamble _ avaiable _ cells} is the number of possible preamble cell used to send the L1 signaling, N _L1pre is the L1 pre number of bits in the signaling, η _{MOD _ L1pre} is the L1 modulation order of the pre-signaling, N _{L1post _ FRAME} is the number of LDPC codewords and < _{RTI ID} = 0.0 ># _{MOD_L1post} < / RTI > is the modulation order of the L1 post signaling.

The puncturing unit may calculate the number of bits available for transmission of the LDPC parity bits based on the number of bits available for the LDPC codeword transmission.

Here, the puncturing section, based on the equation for the number of bits available for the transmission of the LDPC parity bit N _{L1post avaiable _ _} can calculate the _parity.

Here, N _{L1post _ avaiable _ bits} may be bits available in the LDPC codeword transmitted, K _sig is the number of bits of the L1 post-signaling that is input to the encoder, N _{bch _ parity} is BCH parity generated by the BCH encoding The number of bits.

The puncturing unit may calculate the number of bits temporarily punctured in the LDPC parity bits so as to be equal to the number of bits available for transmission of the LDPC parity bits.

Here, the puncturing unit, the number of bits punctured by temporarily popping in the LDPC parity bits based on the equation for N _{punc _} can calculate _temp.

Here, N _{ldpc parity _ _ L1post} is the number of bits of the LDPC parity bit, _{L1post_avaiable_parity} N is the number of bits available for transmission of the LDPC parity bits.

The puncturing unit may calculate the number of bits of the LDPC code word after puncturing based on the value of the number of bits of the LDPC code word excluding the number of bits that are temporarily punctured, The number of bits to be punctured in the LDPC parity bits may be calculated based on the number of bits of the LDPC codeword.

Here, the puncturing unit may calculate the number of bits N _L1post of the LDPC codeword after puncturing based on the following equation.

Here, N _{L1post _ temp} is a value other than the number of bits to be punctured as the temporary number of bits in the LDPC codeword, η _{MOD _ L1post} is a modulation order of the L1 post-signaling.

The puncturing unit may calculate the number N _punc of punctured bits in the LDPC parity bits based on the following equation.

Here, N _{punc _ temp} is the number of bits to be punctured by the temporary, N _L1post is the number of bits, N _L1post of the LDPC codeword after it has been punctured _{_ temp} may be punctured at the bit number of the LDPC codeword to the provisionally Is the value excluding the number of bits.

Meanwhile, a puncturing method of a transmission apparatus for processing L1 signaling, which is composed of L1 pre-signaling and L1 post-signaling according to an embodiment of the present invention, includes performing L1 post signaling on BCH (Bose, Chaudhuri, Hocquenghem) and LDPC And puncturing at least a portion of LDPC parity bits in an LDPC codeword generated by the LDPC encoding, wherein the number of punctured bits is less than the number of bits available for the LDPC codeword transmission The number of bits and the modulation order of the L1 post signaling.

Wherein the puncturing step calculates a number of bits available for transmission of the LDPC codeword and temporarily punctures the LDPC parity bits so that the number of bits of the LDPC codeword is equal to the calculated number of bits The number of bits can be calculated.

Further, the steps of the puncturing may calculate the number of bits available for transmission of the LDPC codeword on the basis of Equation N _{L1post avaiable _ _ bits} below.

Here, N _{preamble _ avaiable _ cells} is the number of possible preamble cell used to send the L1 signaling, N _L1pre is the L1 pre number of bits in the signaling, η _{MOD _ L1pre} is the L1 modulation order of the pre-signaling, N _{L1post _ FECFRAME} is the number of LDPC codewords and < _{EMI ID} = _1.0 & gt _; is the modulation order of the L1 post signaling.

The puncturing step may calculate the number of bits available for transmission of the LDPC parity bits based on the number of bits available for the LDPC code word transmission.

Here, the steps of the puncturing may calculate the number of bits N _{L1post _ _ avaiable parity} available for the transmission of the LDPC parity bits based on the equation below.

Here, N _{L1post _ avaiable _ bits} may be bits available in the LDPC codeword transmitted, K _sig is the number of bits of the L1 post-signaling is the encoding, N _{bch _ parity} is the BCH parity bits generated by the BCH encoding to be.

Also, the puncturing step may calculate the number of bits temporarily punctured in the LDPC parity bits so as to be equal to the number of bits available for transmission of the LDPC parity bits.

Here, the pop step of puncturing may calculate the number of bits to be punctured by a temporary pop in the LDPC parity bits based on equation N _{punc _ temp} below.

Here, N _{ldpc parity _ _ L1post} is the number of bits of the LDPC parity bit, _{L1post_avaiable_parity} N is the number of bits available for transmission of the LDPC parity bits.

The puncturing step may include calculating the number of bits of the LDPC codeword after puncturing based on the value of the number of bits of the LDPC codeword excluding the number of bits that are temporarily punctured, The number of bits punctured in the LDPC parity bits may be calculated based on the number of bits of the LDPC codeword.

Here, the puncturing step may calculate the number of bits N _L1post of the LDPC codeword after puncturing based on the following equation.

Here, N _{L1post _ temp} is a value other than the number of bits to be punctured as the temporary number of bits in the LDPC codeword, η _{MOD _ L1post} is a modulation order of the L1 post-signaling.

The puncturing step may calculate the number N _punc of punctured bits in the LDPC parity bits based on the following equation.

Here, N _{punc _ temp} is the number of bits to be punctured by the temporary, N _L1post is the number of bits, N _L1post of the LDPC codeword after it has been punctured _{_ temp} may be punctured at the bit number of the LDPC codeword to the provisionally Is the value excluding the number of bits.

According to various embodiments of the present invention as described above, the reception performance can be improved in that L1 post signaling can be efficiently transmitted to the receiver.

1 is a view for explaining a frame structure according to an embodiment of the present invention;
2 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention.
3 to 7 are diagrams for explaining a puncturing operation according to an embodiment of the present invention,
8 is a block diagram illustrating a detailed configuration of a transmitting apparatus according to an embodiment of the present invention.
9 is a block diagram illustrating a detailed configuration of a transmitting apparatus according to another embodiment of the present invention;
10 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention.
11 is a block diagram illustrating a detailed configuration of a receiving apparatus according to an embodiment of the present invention.
12 is a block diagram illustrating a detailed configuration of a receiving apparatus according to another embodiment of the present invention, and Fig.
13 is a diagram for explaining a puncturing method of a transmitting apparatus according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a view for explaining a frame structure according to an embodiment of the present invention. As shown in FIG. 1, a frame 100 includes a data symbol 110 and a preamble 110. This frame 100 is the same as that used in the Advanced Television System Committee (ATSC) 3.0 standard in an Orthogonal Frequency Division Multiplexing (OFDM) frame.

The data symbol 110 is service data (e.g., broadcast data) provided to a user and is composed of one or more physical layer pipes (PLPs). In this case, each PLP can independently perform different signal processing. For example, different modulation schemes and coding rates may be applied to each PLP.

The preamble 120 may include L1 pre-signaling information (or L1 pre-signaling information) 121 and L1 post-signaling information (or L1 post signaling information) 122.

Herein, the L1 pre-signaling 121 includes information necessary for a receiving apparatus (not shown) to receive and decode the L1 post signaling 122, and the L1 post signaling 122 includes information indicating that the receiving apparatus (not shown) And includes parameters necessary for access. In this case, the L1 post signaling 122 includes L1 configurable information 123. L1 dynamic information 124, cyclic redundancy checking (CRC) 125, L1 padding 126, and the like.

 The present invention relates to a method of processing L1 post signaling mapped to a preamble in a frame structure as shown in FIG. 1 and transmitted to a receiver, and will be described in detail with reference to the accompanying drawings.

Hereinafter, the lengths of the LDPC codeword, the information word, the parity, the L1 post signaling, the L1 pre-signaling, and the like mean the number of bits included in each of them.

2 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention. According to FIG. 2A, the transmission apparatus 200 includes an encoding unit 210 and a puncturing unit 220.

Meanwhile, the transmitting apparatus 200 may include all or some of the elements defined in the Advanced Television System Committee (ATSC) 3.0 standard. In particular, the transmitting apparatus 200 may perform L1 post signaling defined in the ATSC 3.0 standard And < / RTI >

First, the encoding unit 210 encodes BCH (Bose, Chaudhuri, Hocquenghem) and LDPC (Low Density Parity Check) of the L1 post signaling. 2B, the encoding unit 210 may include a BCH encoder 211 for performing BCH encoding and an LDPC encoder 212 for performing LDPC encoding.

Specifically, the BCH encoder 211 performs BCH coding on the L1 post signaling and outputs the BCH codeword generated by the BCH coding to the LDPC encoder 212. [ The LDPC encoder 212 may perform LDPC encoding on the bits output from the BCH encoder 211 to generate LDPC codewords.

Here, an information word can be included in a codeword in that the BCH code and the LDPC code are systematic codes. That is, in the BCH coding, the input L1 post signaling is performed with the information bits, the BCH codeword generated as a result of the BCH coding includes the L1 post signaling as the information word, and the form in which the BCH parity bits are added to the information word . In the LDPC coding, the LDPC code word generated as a result of the LDPC coding includes the L1 post signaling and the BCH parity bits, which are the information words, and the LDPC parity bits are added to the information word, Can be a form.

In the meantime, since the BCH code word and the LDPC codeword are respectively generated by coding, the BCH codeword is referred to as BCH coded bits or BCH coded blocks, and the LDPC codeword is LDPC coded Bit or LDPC-coded block.

The puncturing unit 220 punctures at least a part of the LDPC parity bits in the LDPC codeword generated by LDPC encoding.

Here, the number of bits to be punctured can be calculated based on the number of bits available for LDPC code word transmission and the modulation order of L1 post signaling.

Hereinafter, a method for calculating the number of bits to be punctured will be described in more detail.

However, as described above, the length of the L1 post signaling may be variable depending on the amount of data, in that the L1 post signaling includes a parameter for accessing data at the receiving end. Thus, if the length of the L1 post signaling is greater than a certain value, the L1 post signaling is segmented to a constant length and each of the plurality of segmented L1 post signalings can be encoded. In this case, since a plurality of LDPC codewords generated by encoding a plurality of segmented L1 post signalings are all composed of the same number of bits, the number of bits to be punctured in one LDPC codeword is How to calculate it will be explained.

First, the puncturing unit 220 calculates the number of bits available for LDPC code word transmission, and calculates the number of bits temporarily punctured in the LDPC parity bits so that the number of bits of the LDPC code word is equal to the calculated number of bits.

Specifically, the L1 post signaling is mapped to a preamble in a frame together with L1 pre-signaling and transmitted to a receiving device (not shown). Accordingly, the L1 post signaling can be mapped to the remaining cells to which the L1 pre-signaling is mapped in the preamble. In this case, each of the L1 post signaling and the L1 pre-signaling may be coded and then modulated and mapped to a cell (or a sub-carrier) of the preamble in a cell type (i.e., a coded modulation symbol).

Therefore, the puncturing unit 220 calculates the number of cells to which the L1 post signaling is mapped, excluding the cell to which the L1 pre-signaling is mapped in the preamble, and outputs the L1 post, which can be mapped to the calculated number of cells, And calculates the number of bits of the signaling. Here, the number of bits calculated may be the number of bits available for LDPC codeword transmission in that the L1 post signaling is encoded to construct an LDPC codeword.

Then, the puncturing unit 220 calculates the number of bits temporarily punctured in the LDPC parity bits constituting the LDPC codeword so as to be equal to the calculated number of bits.

Specifically, the puncture ring portion 220 on the basis of the equation (1) to calculate the total number of bits N _{L1post avaiable _ _ bits} available in the LDPC codeword transmitted. That is, the puncturing unit 220 can calculate the number of bits that can be transmitted among the bits constituting one LDPC codeword.

Here, N _{preamble _ avaiable _ cells} are L1 number of possible preamble cell used to send signaling (that is, the amount of data in the preamble symbols), N _L1pre is the number of bits of the L1 pre-signaling, η _{MOD _ L1pre} the L1 pre-signaling . Thus, N _{preamble_avaiable_cells} in Equation 1 is the number of N _L1pre / η _MOD cells _{_ L1pre} may be a number, that is, L1 post-signaling in a preamble of a possible preamble cells mapped used for transmitting the L1 post-signaling.

는 하나의 LDPC 코드워드 전송에 이용 가능한 셀의 개수가 된다. 이에 따라, L1 포스트 시그널링을 전송하기 위해 이용 가능한 프리앰블 셀에 N_{L1post _ FECFRAME} 개의 LDPC 코드워드가 균등하게 맵핑될 수 있다.In addition, N _{L1post FECFRAME _} is the number of the LDPC codeword. In that in this case, L1 post-signaling is coded and then the segments form a plurality of LDPC codewords, as described above, N _{L1post _ FECFRAME} is the same as the number of segments L1 post-signaling. Therefore, the number of available preamble cells for transmitting L1 post signaling divided by the number of LDPC codewords

Is the number of cells available for one LDPC codeword transmission. Accordingly, the available preamble cell _L1post N _{_ FECFRAME} of the LDPC codeword can be uniformly mapped to transmit the L1 post-signaling.

And, η _{MOD _ L1post} is a modulation order of the L1 post-signaling. Therefore, by multiplying the available preamble cells for transmitting one LDPC codeword by the modulation order of L1 post-signaling, the total number of bits available for one LDPC codeword transmission can be calculated. That is, it is possible to calculate how many bits one LDPC code word should be composed for transmission.

In Equation (1), the modulation order for L1 pre-signaling means the number of bits constituting the modulated L1 pre-signaling cell, and the modulation order for L1 post signaling means the number of bits constituting the modulated L1 post signaling cell do.

In addition, since the modulation order has the same value as the number of bits constituting the modulation symbol, the modulation order can have different values depending on the modulation method. For example, when the modulation method is BPSK, QPSK, 16-QAM, 64-QAM, and 256-QAM, the modulation orders are equal to 1, Therefore, if L1 pre-signaling is modulated with BPSK η _{MOD _ L1pre} is because the one may be omitted η _{MOD _ L1pre} from equation (1), if L1 post-signaling is modulated with BPSK η _{MOD _ L1post} is because the 1 in equation 1 η _{MOD _ L1post} may be omitted.

은 x보다 작은 최대 정수를 나타내며, 일 예로

가 될 수 있다. In Equation 1,

Represents a maximum integer less than x, and in one example

.

Then, the puncturing section 220 calculates the number of bits available for transmission of LDPC parity bits based on the number of bits available for LDPC code word transmission. That is, the puncturing unit 220 may calculate the number of bits that can be transmitted among the LDPC parity bits constituting one LDPC codeword based on the number of bits available for LDPC code word transmission.

Specifically, the puncture ring section 220 may calculate the number of bits available in the LDPC parity bits transmitted on the basis of Equation 2 N _{L1post _ _ avaiable} to the _parity.

Here, N _{L1post avaiable _ _ bits} is the number of bits available in the LDPC codeword transmitted, N _{bch _ parity} is the number of bits of the BCH parity bits generated by the BCH encoding.

K _sig is the number of bits of the L1 post signaling input to the encoding unit 210. In this case, when each of the L1 post signaling segmented after the L1 post signaling is segmented is input to the encoding unit 210, K _sig can be the number of bits of each of the segmented L1 signaling signals input to the encoding unit 210.

In addition, since the encoder 210 sequentially performs BCH encoding and LDPC encoding, the information bits of the LDPC codeword may be composed of BCH code information bits and BCH parity bits. In this case, the information bits of the BCH code may be L1 post signaling which is input to the encoding unit 210. [ Therefore, the value obtained by subtracting the number of bits of the L1 post-signaling and the number of bits of the BCH parity bits input to the encoding unit 210 from the number of bits available for LDPC code word transmission, as shown in Equation 2, Bit number.

Here, the number of bits available for transmission of the LDPC parity bits is equal to the number of LDPC parity bits (hereinafter referred to as the required number of parity bits) capable of ensuring a minimum bit error rate (BER) / frame error rate (FER) Or more. In this case, the required number of parity bits may be determined according to the channel environment or the like.

On the other hand, when the LDPC-code the number of bits available for the word transfer encoder 210 as the input L1 bits of post signaled and smaller than the sum of the number of bits of the BCH parity bits i.e., N _{L1post _ avaiable _ bits} <K _sig + N _{bch _ parity} case, it means that it does not have enough cells exist preamble transmit the L1 post-signaling, it is preferable that such a case does not exist in the system design.

Therefore, the above-described equation (2) may be expressed by the following equation (3). That is, the number of bits available for transmission of the LDPC parity bits may be greater than zero, as shown in Equation (3).

이다.From here,

to be.

Then, the puncturing unit 220 calculates the number of bits to be punctured in the LDPC parity bits so as to be equal to the number of bits available for transmission of the LDPC parity bits. That is, the puncturing unit 220 calculates the number of bits to be temporarily punctured in the LDPC parity bits so that the LDPC parity bits constituting one LPDC codeword are as many as the number of bits available for transmission of the LDPC parity bits .

Specifically, the puncture ring portion 220 on the basis of Equation 4 below can calculate the number of bits to be punctured as temporary N _{punc temp _} In LDPC parity bit.

이다. From here,

to be.

In this case, if the number of bits of the LDPC parity bits that can be transmitted is larger than the number of bits of the LDPC parity bits generated by the LDPC encoding, it can be seen that all generated LDPC parity bits can be transmitted to a receiving apparatus (not shown) . Therefore, in this case, the number of bits to be punctured temporarily becomes zero.

And, N _{ldpc _ parity _ L1post} is the number of bits of the LDPC parity bit (i.e., bit number of the LDPC parity bit generated by the LDPC encoding), and, N _{L1post _ avaiable _ parity} is the number of bits available for the transmission of the LDPC parity bit to be.

That is, the L1 post-signaling encoder LDPC parity bit having a constant length when the LDPC encoding by 210. That is, N _{ldpc _ parity _ L1post} of bits LDPC parity bits are generated consists, in the L1 post-signaling it can be mapped Considering the number of preamble cells, the number of bits of the LDPC parity bits that can be transmitted to a receiving apparatus (not shown) is limited to N _{L1post_avaiable_parity} .

Therefore, when the number of bits of the LDPC parity bits generated by the LDPC encoding is larger than the number of bits of the LDPC parity bits that can be transmitted, the bits of the LDPC parity bits that can be transmitted from the number of LDPC parity bits generated by the LDPC encoding The number of LDPC parity bits minus the number must be punctured. Accordingly, the puncturing unit 220 can calculate the number of bits temporarily punctured in the LDPC parity bits based on Equation (4).

On the other hand, when the number of bits of the LDPC parity bits generated by the LDPC coding is smaller than the number of bits of the LDPC parity bits that can be transmitted, it means that there is an extra preamble cell to which the L1 post signaling can be mapped. Accordingly, when the number of bits of the LDPC parity bits generated by the LDPC encoding is smaller than the number of bits of the LDPC parity bits that can be transmitted, the transmitting apparatus 200 does not perform puncturing on the LDPC parity bits, Some of the bits may be further transmitted.

Meanwhile, all of the generated LDPC parity bits may be transmitted to a receiving apparatus (not shown). Therefore, except for this case, that is, when only a part of the LDPC parity bits must be punctured, Equation (4) may be expressed as Equation (5).

In the case of Equation (5), if the number of bits of the LDPC parity bits generated by the LDPC encoding is smaller than the number of bits of the LDPC parity bits that can be transmitted (i.e., N _{punc_temp} is smaller than 0) May not perform puncturing on the LDPC parity bits or may additionally transmit some bits in the LDPC codeword.

Then, the puncturing unit 220 calculates the number of bits of the LDPC code word after puncturing based on the value excluding the number of bits temporarily punctured from the number of bits of the LDPC code word, and outputs the calculated punctured LDPC code And calculates the number of bits to be punctured in the LDPC parity bits based on the number of bits of the word.

Here, the number of bits of the LDPC codeword after puncturing may be the number of bits of the LDPC codeword after the punctured LDPC parity bit is punctured and additionally the LDPC parity bit is punctured. In this case, the additional puncturing may be performed so that the number of bits of the LDPC codeword after the LDPC parity bits are temporarily punctured is an integral multiple of the modulation order of the L1 post-signaling. Thus, if the number of bits of the LDPC codeword after the temporary LDPC parity bits are punctured satisfies an integer multiple of the modulation order of the L1 post signaling, the number of bits to be further punctured may be zero.

Specifically, the puncturing unit 220 can calculate the number of bits N _L1post of the LDPC codeword after puncturing based on Equation (6) below.

와 같이 표현될 수 있다.Here, _{侶 MOD _} L1 post is the modulation order of the L1 post signaling. N _{L1post_temp} may correspond to a value excluding the number of bits to be temporarily punctured from the number of bits of the LDPC code word. In other words, N is _{L1post temp _}

Can be expressed as

Accordingly, the number of bits of the LDPC codeword after puncturing can be an integral multiple of the modulation order of the L1 post signaling. The reason why the number of LDPC codeword bits after puncturing is an integer multiple of the modulation order of L1 post-signaling will be described later.

As a result, the puncturing unit 220 can calculate the number N _punc of punctured bits in the LDPC parity bits based on Equation (7) below.

Here, N _{punc _ temp} is temporarily puncturing of bits, N _L1post is the number of bits in the LDPC codeword after it has been punctured, that is N _{L1post _ temp} is the number of bits that are punctured temporarily in the number of bits of the LDPC codeword The value is excluded.

That is, the puncturing unit 220 adds the number of bits temporarily punctured in the LDPC parity bits and the number of bits of the LDPC codeword after the puncturing by the number of bits to an integral multiple of the modulation order of the L1 post signaling It is possible to calculate the number of bits finally punctured in the LDPC parity bits by adding the number of bits to be punctured.

The puncturing unit 220 can puncture the bits of the calculated value based on Equation (7) from the LDPC parity bits. In this case, the position of the bit to be punctured may be variable within the LDPC parity bit. For example, if the number of bits calculated based on Equation (7) is 20, the puncturing unit 220 punctures the first to twentieth bits in the LDPC parity bits, And bits 42 to 52 can be punctured.

As described above, the puncturing unit 220 calculates the number of bits to be punctured based on the number of bits available for LDPC code word transmission and the modulation order of the L1 post signaling, and punctures LDPC parity bits by the calculated number of bits .

Meanwhile, the transmitting apparatus 200 may transmit an LDPC codeword at least partially punctured in the LDPC parity bits to a receiving apparatus (not shown). For example, the transmitting apparatus 200 may map an LDPC codeword at least partially punctured in LDPC parity bits to an OFDM frame and transmit the LDPC codeword to a receiving apparatus (not shown). In this case, the LDPC codeword can be mapped to the preamble of the OFMD frame in that the L1 post-signaling is generated by being encoded.

In this case, the LDPC codeword in which at least some of the LDPC parity bits are punctured may be interleaved before being mapped to the frame, demultiplexed into cells, and then modulated and mapped to the frame. This will be described later in detail with reference to FIG.

On the other hand, in the above example, additional puncturing is performed on the LDPC parity bits so that the number of bits of the LDPC code word becomes an integral multiple of the modulation order, but this is only an example. That is, the puncturing unit 220 may insert (or add) a zero bit in place of puncturing so that the number of bits of the LDPC code word is an integer multiple of the modulation order.

Specifically, when the number of bits of the LDPC parity bits that can be transmitted is smaller than the number of bits of the LDPC parity bits generated by the LDPC encoding, the puncturing unit 220 calculates the number of bits The number of bits N _L1post of the LDPC code word can be calculated.

를 만족하며, 이 경우 N_{punc _ temp}=0이 될 수 있다.Here, _{侶 MOD _} L1 post is the modulation order of the L1 post signaling. Then, N _{L1post_temp} is

A satisfies, in which case it can be the N _{punc _ temp} = 0.

Then, the puncturing unit 220 calculates the number of zero bits N _pads to be inserted based on the following equation (9), inserts zero bits as many as the calculated number of bits, and determines whether the number of bits of the LDPC code word is an integer You can make it double.

Where N _{L1post_temp} is the number of bits of the LDPC codeword after the zero bit is inserted, and N _{L1post_temp} is the value excluding the number of bits that are temporarily punctured from the number of bits of the LDPC codeword.

Accordingly, the puncturing unit 220 may insert the N bits of the N _pad into the LDPC codeword so that the number of bits of the LDPC codeword is an integral multiple of the modulation order.

A specific example of the number of LDPC parity bits punctured according to the above-described method can be shown in Table 1 below. In the case of Table 1, it is assumed that QPSK is used as a modulation scheme and that segmentation is not performed for L1 post signaling.

Hereinafter, the puncturing operation will be described in more detail with reference to FIGS. 3 to 7 attached hereto. Meanwhile, the parameters shown in FIGS. 3 to 7 may have the same meaning as described in FIG.

As shown in FIG. 3, the L1 signaling 300 may comprise an L1 pre-signaling 310 and an L1 post signaling 320. Here, L1 post-signaling 320 may be of a N _{_ L1post FECFRAME} of L1 post-FEC frame (i.e., LDPC codeword). That is, the N _{L1post _ FECFRAME} of L1 post-FEC frame as L1 post-signaling 320 on the point and the segment so as to have a certain length that a plurality of segment L1 post-signaling each encoding, L1 post-signaling 320 in Fig. 3 As shown in Fig.

Meanwhile, each of the L1 pre-signaling 310 and the L1 post signaling 320 may be mapped to the preamble 330. [ In this case, each of the L1 post signaling and the L1 pre-signaling may be coded and then modulated and mapped to each cell constituting a preamble in a cell form.

In this case, L1 pre-signaling (310) as shown in Figure 3 is N _L1pre / η _{MOD _ L1pre} one, so the mapping to the cell, L1 post-signaling 320 includes L1 pre-signaling (310 from the available preamble cell used to send the L1 signaling It must be mapped to the N _L1pre / η _{MOD _ L1pre} cells -) is mapped and the rest of the cell i.e., N _{preamble_available_cells.}

Although the L1 pre-signaling 310 and the L1 post signaling 320 are sequentially mapped to the preamble 330 in FIG. 3, this is only an example. That is, the L1 pre-signaling 310 and the L1 post signaling 320 may be mapped to cells located at various positions in the preamble 330 and transmitted to a receiving apparatus (not shown).

On the other hand, the L1 post signaling 320 as described above, N _{L1post _ FECFRAME} of L1 post in that it consists of a FEC frame, all of the L1 post-FEC frame N _{preamble_available_cells} - N _L1pre / η _{MOD _} to be mapped to _L1pre cells each of L1 post-FEC frame is N _{L1post avaiable _ _ bits} of bits to be configured.

In this case, the L1 post FEC frame is composed of information bits and LDPC parity bits, and the information bits are composed of (K _sig + N _{bch _ parity} ) bits, the number of bits of LDPC parity bits is N _{L1post _ _ aviable} may be smaller than or meets the _parity case, the L1 post-FEC frame may be configured _L1post N _{_ _ avaiable bits} bits. Therefore, if the number of the LDPC parity bit generated by the LDPC encoding exceeds N _{L1post _ _ aviable parity,} some among the LDPC parity bits are to be punctured.

Specifically, the number of bits of the LDPC parity bit generated by the LDPC coding as shown in FIG. 4, the N _{L1post _ aviable _} greater than _parity i.e., N _{ldpc _ parity _ L1post>} N _{L1post _ aviable _ parity,} N _{punc _ temp} Of the LDPC parity bits can be temporarily punctured. However, also the number of bits of the LDPC parity bit generated by the LDPC coding as shown in FIG. 5 is smaller than N _{L1post_aviable_parity} or equal i.e., if the N _{ldpc _ parity _ L1post} ≤ N _{L1post _ aviable _ parity,} LDPC parity bits are temporarily pow It may not be executed. That is, the number of bits of the LDPC parity bits temporarily punctured may be zero. This is because all the LDPC parity bits generated by the LDPC encoding can be mapped to the preamble 330 and transmitted to the receiving apparatus (not shown) even if the LDPC parity bits are not punctured.

Accordingly, LDPC parity bits after the puncturing can be temporarily _L1post N _{_ _ aviable} less than one _parity or configure the same number of bits.

On the other hand, some LDPC parity bits may be additionally punctured such that the length of the L1 post FEC frame after the LDPC parity bits are punctured temporarily becomes an integral multiple of the modulation order of the L1 post signaling.

를 만족한다.That is, when LDPC parity bit of the N _{punc _ temp} as shown in FIG. 6 are provisionally length N _L1post of puncturing L1 post-FEC frame after _{_ temp} is not an integral multiple N _L1post the modulation order of the L1 post-signaling, N _{L1post _ temp} - N _L1post LDPC parity bits can be further punctured. Here, N _L1post may be the largest value of N _{temp _ L1post} than in integral multiple values of modulation orders of the L1 post-signaling. Accordingly, the number of LDPC parity bits that are finally punctured can be N _punc . Here, N _punc is

.

On the other hand, Fig. 6, N _{punc _} the _temp as LDPC parity bits are temporarily punctured L1 post in FEC frame N _{L1post _ temp} - LDPC parity bit by N _L1post have been described a case where the puncturing further, which one It is only an example. That is, LDPC parity number of the LDPC parity bit generated by the LDPC encoding to twice N _{L1post _ aviable _} even less than _parity or equal to, similar to the above-described method L1 post-FEC length of the order of modulation of the L1 post-signaling integer of frame The bit can be punctured.

In addition, although the LDPC parity bit is additionally punctured in FIG. 6, this is merely an example.

That is, the number of the LDPC parity bit generated by the LDPC encoding N _{L1post aviable _ _} If _parity is less than or equal to, by inserting a zero bit may be the number of bits of the LDPC codeword such that an integral multiple of the modulation order,

Meanwhile, FIG. 7 is a diagram for explaining a process of mapping L1 post-signaling to a preamble according to an embodiment of the present invention.

As shown in Fig. 7 (a), L1 signaling includes L1 pre-signaling and L1 post signaling. Here, L1 post-signaling may be of the K _{L1 _ PADDING} L1 padding bits 730, before the addition K _{ex post _ _ pad} bits, as shown in Fig. 7 (b).

On the other hand, the L1 post signaling can be segmented to a certain length. Specifically, the L1 post-signaling may be open-circuit segment N _{L1post FECFRAME _} as shown in Figure 7 (c), and the L1 post-signaling segment, each of which may be of bits K _sig.

Each of the segmented L1 post signaling is then BCH and LDPC encoded, thereby generating a plurality of LDPC codewords, i.e., a plurality of L1 post FEC frames. In this case, each LDPC codeword may be composed of information word bits and LDPC parity bits as shown in FIG. 7 (d). Herein, the information bits of the LDPC codeword can be composed of segmented L1 post signaling and BCH parity bits.

Thereafter, some LDPC parity bits may be punctured. Specifically, the N _punc LDPC parity bits can be punctured such that the length of the punctured LDPC codeword is N _{L1 post} as shown in FIG. 7 (e).

As shown in FIGS. 7 (f) and 7 (f), the LDPC codeword in which some of the LDPC parity bits are punctured may be modulated and mapped to the preamble.

와 같다. 이에 따라, 프리앰블에 맵핑되는 전체 변조 심볼의 수 N_{MOD _ L1post _ total}는

와 같다.On the other hand, the number of modulated L1 post-signaling cells, i.e., modulation symbols, mapped to the preamble is as follows. Specifically, the number of punctured LDPC codeword bits after the steps described above, N _L1post, and in that the modulation order of the L1 post-signaling η _{MOD _ L1post,} a LDPC code, the number of modulation symbols mapped to the preamble per code word N _{MOD _ L1post _ per __ FEC} is

. Accordingly, the total number of modulation symbols mapped to the preamble N _{MOD _ _ L1post total} is

.

8 is a block diagram illustrating a detailed configuration of a transmitting apparatus according to an embodiment of the present invention. 8, the transmission apparatus 200 includes a segment unit 230, a zero padding unit 240, a parity interleaver 250, an interleaver 250, and an interleaver 260 in addition to the encoding unit 210, the BCH encoder 211, and the LDPC encoder 212. 260, a demux 270, and a modulator 280. [ Here, the encoding unit 210 and the puncturing unit 220 are the same as those described with reference to Figs. 1 to 7, and a detailed description thereof will be omitted.

The segment unit 230 segments the L1 post signaling.

Specifically, the segment unit 230 segments the L1 post signaling so that the L1 post signaling has a predetermined length when the length of the L1 post signaling is greater than or equal to a predetermined value, and outputs a plurality of segmented L1 post signalings to the zero padding unit 240 can do.

In this case, each of a plurality of segmented L1 post signalings may form a bit string. However, in some cases, the segment unit 230 may add the L1 padding bits to the L1 post signaling to segment the L1 post signaling to a certain length, and segment the L1 post signaling to which the L1 padding bit is added.

Here, the constant length may be a value less than or equal to the number of bits that can be encoded by the encoding unit 210. That is, in the case of the BCH code, the segment unit 230 is configured to include the L1 post (the number of bits) that is less than or equal to the number of bits that can be encoded by the encoding unit 210 in the case that the information bits composed of a predetermined number of bits are required in the BCH encoding, The signaling can be segmented.

Accordingly, the zero padding unit 240 adds (or paddes) zero bits (or zero padding bits) to each of the segmented L1 post signaling.

Specifically, the BCH encoder 211 generates a BCH codeword by BCH encoding and outputs the BCH codeword to the LDPC encoder 212, and the LDPC encoder 212 can perform LDPC encoding using the BCH codeword as the information bits . At this time, in the case of the LDPC code performed by the LDPC encoder 212, the BCH encoder 211 must generate a BCH codeword having a predetermined length in order that a certain length of information bits are required according to the coding rate.

In order to generate the BCH codeword having a predetermined length, the BCH encoder 211 must perform BCH coding on a predetermined number of bits. Accordingly, the zero padding unit 240 adds a zero bit to each of the L1 post signaling segments so that the segmented L1 post signaling has the length of the information bits required in the BCH code, and encodes the L1 post signaling to which the zero bit is added (210).

For example, if the segmented L1 signaling is composed of K _sig bits, the number of bits of the information bits of the BCH code is K _bch and K _bch > K _sig , the zero padding unit 240 _obtains K _bch -K _sig zero bits Can be added to each of the segmented L1 signaling.

The encoding unit 210 performs BCH encoding and LDPC encoding on each of the L1 post signaling received from the zero padding unit 240 and outputs the generated plurality of LDPC codewords to the parity interleaver 250 . For this purpose, the encoding unit 210 may include a BCH encoder 211 and an LDPC encoder 212.

That is, the BCH encoder 211 performs BCH encoding on each of the L1 post signalings output from the zero padding unit 240 to generate a plurality of BCH codewords, and outputs the BCH codewords to the LDPC encoder 212. [

In this case, the BCH codeword may be composed of segmented L1 signaling, zero bits added to segmented L1 signaling, and BCH parity bits. That is, the number of bits N _bch of the BCH codeword may be K _sig + (K _bch -K _sig ) + N _{bch _ parity} , which may be equal to the number of bits K _ldpc of the information bits of the LDPC code.

Here, K _sig is the number of bits of the L1 signaling segment, (K _bch -K _sig) is the number of bits of a zero bit in addition to the segments L1 signaling, N _{bch _ parity} is the number of bits of the BCH parity bits.

The LDPC encoder 212 performs LDPC encoding on each of the BCH codewords output from the BCH encoder 211, generates a plurality of LDPC codewords, and outputs the LDPC codewords to the parity interleaver 250.

In this case, the LDPC codeword may be composed of segmented L1 signaling, zero bits added to segmented L1 signaling, BCH parity bits, and LDPC parity bits. That is, the number of bits N of _ldpc LDPC codeword may be a _sig + K (K _bch -K _sig) + N + N _{ldpc parity bch _ _ _ L1post parity.} Here, N _{ldpc parity _ _ L1post} is the number of bits of the LDPC parity bits.

The parity interleaver 250 performs parity interleaving on each of the LDPC codewords received from the encoding unit 210. [ Specifically, the parity interleaver 250 interleaves only LDPC parity bits among the bits constituting the LDPC codeword, and outputs the parity interleaved LDPC codeword to the puncturing unit 220. However, in some cases, the parity interleaver 250 may be omitted.

The puncturing unit 220 can remove the zero bit inserted by the zero padding unit 240 in each LDPC codeword output from the parity interleaver 250. [

Specifically, the puncturing unit 220 receives the zero bits padded by the zero padding unit 240 among the bits output from the parity interleaver 250 based on the positions and numbers of the zero bits inserted in the zero padding unit 240, Can be removed. Shortening means that the padded zero bit is removed after being encoded. The zero bit inserted by the zero bit unit 240 is removed by shortening and is not transmitted to the receiving apparatus (not shown).

The puncturing unit 220 punctures a part of the LDPC parity bits in each of the LDPC codewords received from the parity interleaver 250 and outputs the punctured LDPC codewords to the interleaver 260 Can be output.

와 같을 수 있다. 여기에서, N_{punc _ temp}는 LDPC 패리티 비트들에서 임시적으로 펑처링되어야 하는 비트 수이고, N_{L1post _ temp}는

와 같다. 한편, 펑처링되는 비트 수와 관련하여서는 상술한 바 있다.In this case, the number of bits to be punctured is

&Lt; / RTI &gt; Here, N _{punc _} and _temp is the number of bits that should be punctured LDPC parity bit in a temporary, N _{L1post _ temp} is

. On the other hand, the number of bits to be punctured has been described above.

In this manner, the puncturing unit 220 may perform puncturing and shortening for each LDPC codeword, and then output it to the interleaver 260. For example, the number of bits of the segment L1 signaling K _sig, BCH the bit number of parity bits N _{bch _ parity,} LDPC the bit number of parity bits N _{ldpc _ parity _ L1post,} pop number of bits to be punctured to N _punc La N _L1post = K _sig + N _{bch_parity} + (N _{ldpc_parity_L 1 post} -N _punc ) is the number of bits N _L1post of the LDPC code word output from the _puncturing unit 220. At this time, N _L1post can be an integral multiple of the modulation order.

On the other hand, in the above example, puncture ring portion 220 was in addition to the LDPC parity bit of the N _{L1post temp _} -N _L1post puncturing the N _L1post to an integral multiple of the modulation order. However, this is only an example, and the puncturing unit 220 may insert a zero bit so that the number of bits of the LDPC code word may be an integral multiple of the modulation order.

That is, the puncturing unit 220 may insert the zero bit of the N _pad into the LDPC codeword after the LDPC parity bit is temporarily punctured so that the number of bits of the LDPC codeword is an integer multiple of the modulation order. In this case, the number of bits of the LDPC codeword output from the puncture ring portion (220) N _L1post = K _sig + N _L1post is N _{bch _ parity} + (N _{ldpc parity _ _ _ L1post} -N _{punc temp} N + _pad) can be have.

The interleaver 260 interleaves each LDPC codeword received from the puncturing unit 220. In this case, the interleaver 260 may interleave the LDPC codeword using N _c columns of N _r rows, and output the interleaved LDPC codeword to the demux 270 .

More specifically, the interleaver 260 may puncture the ring from the 220 first line light the LDPC codeword bits in the column direction, the first to the second column from N _c-th column, and, LDPC codeword bits with a plurality of columns of light output from the The interleaving can be performed by reading in the row direction up to the N _r -th row. Accordingly, the bits written to the same row in each column are sequentially output, so that the order of the LDPC codeword bits can be redefined as compared with before interleaving.

Meanwhile, the interleaver 260 may selectively perform interleaving according to the modulation scheme. For example, interleaver 260 may interleave LDPC codewords only when the modulation scheme is 16-QAM, 64-QAM, or 256-QAM.

On the other hand, the number of columns N _c and the number of rows N _r of the interleaver 260 may be variously changed according to the coding rate and the modulation method. Specifically, when the coding rate of the LDPC code is 7/15, the number of columns N _c is equal to the modulation order for L1 post signaling, and the number of rows N _r is the number of bits of the LDPC code word output from the puncturing unit 220 It can be a value divided by N _c .

For example, since the number of bits of the LDPC codeword output from the _puncturing unit 220 is N _{L1 post} , when the modulation schemes are 16-QAM, 64-QAM and 256-QAM, the modulation order is 4,6, 8, the number of columns N _c is 4, 6, 8, respectively, and the number of rows N _r can be N _{L1 post} / 4, N _{L1 post} / 6, N _{L1 post} / 8.

Thus, the number of rows the number of columns of the interleaver (260) N _c equal to the modulation order of the L1 post-signaling, and is a _L1post N / N _c. Accordingly, when the number of bits of the LDPC codewords output from the puncturing unit 220 is an integral multiple of the modulation order of the L1 post signaling, the bits constituting each LDPC codeword are separated by rows and columns of the interleaver 260 Lt; / RTI &gt; Therefore, in the present invention, the number of bits of the LDPC code word after puncturing is made to be an integral multiple of the modulation order.

A demultiplexer (demultiplexer) 270 demultiplexes each of the LDPC codewords received from the interleaver 260.

Specifically, the demux 270 performs a bit-to-cell conversion on the interleaved LDPC codewords to convert the interleaved LDPC codewords into cells having a predetermined number of bits Or a data cell, and outputs the demultiplexed data to a modulator 280. [

For example, the demux 270 may output the LDPC codeword bits output from the interleaver 260 sequentially to one of a plurality of sub-streams to convert the LDPC codeword bits into cells and output the bits. In this case, bits having the same index in each of the plurality of sub-streams can constitute the same cell.

Here, the number of sub-streams is equal to the number of bits constituting the cell. For example, when the modulation scheme is BPSK, QPSK, 16-QAM, 64-QAM, or 256-QAM, the number of sub-streams may be 1, 2, 4, 6, _{N L1post, N L1post / 2,} N L1post / 4, can be an _{N L1post / 6, N L1post /} 8.

On the other hand, the demux 270 can selectively demultiplex according to the modulation scheme. For example, the demux 270 may not perform a demultiplexing operation when the modulation scheme is BPSK.

The modulator 280 may modulate the cells output from the demux 270. Specifically, the modulator 280 maps the cells output from the demux 270 to the gaming sites using various modulation methods such as BPSK, QPSK, 16-QAM, 64-QAM, and 256-QAM, have. Here, when the modulation method is BPSK, QPSK, 16-QAM, 64-QAM, or 256-QAM, the number of bits constituting the modulated cell (i.e., modulation symbol) is 1, .

Meanwhile, the transmitting apparatus 200 can transmit the modulation symbols to a receiving apparatus (not shown). For example, the transmitting apparatus 200 may map a modulation symbol to a frame and transmit it to a receiving apparatus (not shown) through an assigned channel. In this case, the modulation symbols of the L1 post signaling can be mapped to the preamble in the OFDM frame.

In the above example, the zero padding unit 240 and the encoding unit 210 are shown as separate structures. However, the present invention is not limited thereto. The padding unit 240 may be included in the encoding unit 210. That is, the encoding unit 210 may include a zero padding unit 240, a BCH encoder 211, and an LDPC encoder 212.

Also, in the above-described example, the zero padding unit 240 is described as being disposed before the BCH encoder 211, but this is merely an example. That is, the zero padding unit 240 may be disposed between the BCH encoder 211 and the LDPC encoder 212 as shown in FIG. In this case, only the arrangement of the elements is different from that described in FIG. 8, but the operations and the like performed in the respective elements are the same. Therefore, in the following, FIG. 9 will be described mainly on the above-described differences.

Referring to FIG. 9, the BCH encoder 211 performs BCH encoding on each segmented L1 post signaling to generate a plurality of BCH codewords, and outputs the generated BCH codewords to the zero padding unit 240. FIG.

The zero padding unit 240 adds zero bits to each of the BCH codewords and outputs a plurality of BCH codewords to which the zero bits are added to the LDPC encoder 212. [ For example, the length of the BCH code words _bch N (= K + K _{sig _ bhc parity),} and if the length of the information word required for LDPC code is K _ldpc, zero-padding unit 240 K _ldpc -N it is possible to pad as many as zero bits of _bch into the BCH code word.

The LDPC encoder 212 performs LDPC encoding on each of the BCH codewords to which a zero bit is added to generate a plurality of LDPC codewords and output the LDPC codewords to the parity interleaver 250. In this case, the LDPC encoder 212 performs LDPC encoding on the BCH codeword to which the zero bit is added in order that the BCH codeword to which the zero bit is added is composed of K _ldpc bits, so that the LDPC codeword having the length of N _ldpc Lt; / RTI &gt;

8 and 9, the transmitting apparatus 200 may further include a scrambler (not shown). A scrambler (not shown) may perform a function of randomizing input bits and outputting them. 8, a scrambler (not shown) for performing such a function may be disposed between the segment 230 and the zero padding 240 in the case of FIG. 8, and the segment 230 and the BCH encoder 211, As shown in FIG.

Meanwhile, the transmitting apparatus 200 according to another embodiment of the present invention may further include a controller (not shown) for controlling the operation of the transmitting apparatus 200 as a whole.

Specifically, the control unit (not shown) may calculate various parameters to control operations performed by the respective components of the transmitting apparatus 200, and may provide the parameters to the respective components. Accordingly, the encoding unit 210, the puncturing unit 220, the segment unit 230, the zero padding unit 240, the parity interleaver 250, the interleaver 260, the demux 270, and the modulating unit 280, Can perform an operation using information received from a control unit (not shown).

For example, the control unit (not shown) may calculate the segmented length of the L1 post signaling and provide the segmented portion 210 with information on the zero bit added to the segmented L1 post signaling to the zero padding unit 240 ). In addition, the control unit (not shown) may provide the coding unit 220 with information on the coding rate, the length of the codeword, and the like, and may provide information on the parity interleaving scheme to the parity interleaver 250. In addition, the control unit (not shown) may calculate the number of bits to be punctured and provide the punctured bits to the puncturing unit 220, and may provide information on the interleaving method to the interleaver 260. In addition, the control unit (not shown) may provide information on the demultiplexing scheme to the demux 270 and provide information on the modulation scheme to the modulator 280.

10 is a block diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention. 10A, a receiving apparatus 1000 includes a demultiplexing unit 1010 and a decoding unit 1020. [

The demultiplexing unit 1010 may perform the demultiplexing on the channel value of the signal received from the transmitting apparatus 200. [ Here, the channel value for the received signal may vary, and may be, for example, a log likelihood ratio (LLR) value.

Specifically, the depuncturing unit 1010 corresponds to the puncturing unit 220 of the transmitting apparatus 200, and performs an operation corresponding to the puncturing unit 220. That is, the demultiplexing unit 1010 inserts the LLR value corresponding to the LDPC parity bits punctured in the puncturing unit 220 into the LLR value, and outputs the LLR value to the decoding unit 1020. Here, the LLR value corresponding to the punctured bits may be zero.

와 같을 수 있다. In this case, information on the positions and the number of bits punctured in the puncturing unit 220 may be provided from the transmitting apparatus 200 or stored in the receiving apparatus 1000. Here, the number of bits that have been punctured in the puncturing section 220 is

&Lt; / RTI &gt;

The decoding unit 1020 performs decoding using the output value of the demultiplexing unit 1010. [ Specifically, the decoding unit 1020 is a component corresponding to the encoding unit 210 of the transmitting apparatus 200, and performs an operation corresponding to the enriching unit 210. [ For this, the decoding unit 1020 may include an LDPC decoder 1021 and a BCH decoder 1022 as shown in FIG. 10B.

Specifically, the LDPC decoder 1021 is a component corresponding to the LDPC encoder 212, and performs an operation corresponding to the LDPC encoder 330. For example, the LDPC decoder 1021 performs LDPC decoding using the LLR value output from the de-puncturing unit 1010 based on iterative decoding based on a sum-product algorithm, Can be corrected.

Here, the multiplicative algorithm exchanges messages (e.g., LLR values) via edges on a bipartite graph of a message passing algorithm and calculates output messages from messages input to variable nodes or check nodes The algorithm is shown in Fig.

The BCH decoder 1022 performs BCH decoding on the output value of the LDPC decoder 1021.

Here, in that the output value of the LDPC decoder 1021 is composed of L1 post signaling and BCH parity bits, the BCH decoder 1022 corrects the error using the BCH parity bits and sends the corrected L1 pre- Can be output.

On the other hand, LDPC and BCH decoding can be performed by various known methods.

In this case, information on a coding scheme, a coding rate, and the like, which has been performed in the transmission apparatus 200, may be provided from the transmission apparatus 200 or stored in the reception apparatus 1000.

11 is a block diagram illustrating a detailed configuration of a receiving apparatus according to an embodiment of the present invention. 11, the receiving apparatus 1000 includes a demultiplexer 1030, a multiplexer 1040, a deinterleaver 1050, a demultiplexer 1030, a demultiplexer 1030, and a demultiplexer 1030 in addition to a demultiplexing unit 1010, an LDPC decoder 1021, and a BCH decoder 1022. [ (1060), a parity deinterleaver (1070), a depadding unit (1080), and a de-segmenting unit (1090). From here,

The demodulation unit 1030 receives and demodulates the signal transmitted from the transmission apparatus 200. Specifically, the demodulator 1030 demodulates the received signal, generates a value corresponding to the LDPC codeword, and outputs the value to the mux 1040.

Here, the value corresponding to the LDPC codeword can be expressed by the channel value. There are various ways to determine the channel value, for example, a method for determining the LLR value.

Here, the LLR value can be represented by a value obtained by taking the ratio of the probability that the bit transmitted from the transmitting apparatus 200 is 0 and the probability of one day to Log. Alternatively, the LLR value may be a bit value determined according to a hard decision, and the LLR value may be a representative value determined according to a period in which the probability that the bit transmitted from the transmitting apparatus 200 is 0 or 1 belongs .

The multiplexer 1040 multiplexes the output value of the demodulator 1030 and outputs the multiplexed output to the deinterleaver 1050.

Specifically, the MUX 1040 is a component corresponding to the DEMUX 270 of the transmitting apparatus 200, and can perform an operation corresponding to the DEMUX 270. That is, the MUX 1040 can perform cell-to-bit conversion on the output value of the demodulator 1030 and rearrange the LLR values on a bit-by-bit basis.

The deinterleaver 1050 deinterleaves the output value of the MUX 1040 and outputs it to the demultiplexing unit 1010.

Specifically, the deinterleaver 1050 is a component corresponding to the interleaver 260 of the transmitting apparatus 200, and can perform an operation corresponding to the interleaver 260. That is, the deinterleaver 1050 can deinterleave the output value of the mux 1040 by performing the interleaved operation performed by the interleaver 260 inversely.

The demultiplexing unit 1010 adds a specific value to the output value of the deinterleaver 1050 and outputs it to the demultiplexing unit 1060. That is, the de-puncturing unit 1010 is a component corresponding to the punting unit 220 of the transmitting apparatus 200, and performs an operation corresponding to the puncturing unit 220.

가 될 수 있다. 이에 따라, 디펑처링부(1010)는 펑처링된 LDPC 패리티 비트들이 존재하였던 위치에 해당 개수만큼의 LLR 값을 삽입할 수 있다.Specifically, the de-puncturing unit 1010 may insert an LLR value corresponding to the bits that have been punctured in the puncturing unit 220. [ Here, the LLR value for the punctured bits may be zero. To this end, the receiving apparatus 1000 may store information on the number and position of the punctured bits in the transmitting apparatus 200, or may receive the information from the transmitting apparatus 200. Here, the number of bits that have been punctured in the puncturing section 220 is

. Accordingly, the demultiplexing unit 1010 can insert LLR values corresponding to the number of punctured LDPC parity bits.

The de-shortening unit 1060 adds a specific value to the output value of the de-puncturing unit 1010, and outputs it to the parity deinterleaver 1070. That is, the di-shortening unit 1060 corresponds to the puncturing unit 220 and the zero padding unit 240 of the transmitting apparatus 200, and corresponds to the puncturing unit 220 and the zero padding unit 240 Can be performed.

Specifically, the di-shortening unit 1060 may add LLR values corresponding to zero bits that have been added to the zero padding unit 240 and then removed from the puncturing unit 220. In this case, The bit, i. E., The LLR value corresponding to the zero bit that has been shortened, may be + [infinity] or -∞. To this end, the receiving apparatus 1000 may store information on the number, position, and bit values of the bits shortened in the transmitting apparatus 200, or may receive the information from the transmitting apparatus 200. Accordingly, the di-shortening unit 1060 can insert a corresponding number of LLR values at positions where the shortened zero bits were present.

11, the de-puncturing unit 1010 and the de-shortening unit 1060 are shown in order. However, the de-puncturing unit 1010 and the de-shortening unit 1060 may be mutually changed in order .

The parity deinterleaver 1070 performs parity deinterleaving on the output value of the deshorthing unit 1060 and outputs it to the decoding unit 1020. [

Specifically, the parity deinterleaver 1070 is a component corresponding to the parity interleaver 250 of the transmitting apparatus 200, and performs operations corresponding to the parity interleaver 250. That is, the parity deinterleaver 1070 inversely performs the interleaving operation performed by the parity interleaver 250 and deinterleaves the LLR values corresponding to the LDPC parity bits among the LLR values output from the desynchronizing unit 1060 have.

However, the parity deinterleaver 1070 may be omitted depending on whether the parity interleaver 250 is used in the transmission apparatus 200 or not.

The decoding unit 1020 performs decoding using the output value of the parity deinterleaver 1070. The decoding unit 1020 includes an LDPC decoder 1021 and a BCH decoder 1022. The decoding unit 1020 performs LDPC and BCH decoding using the LLR value output from the parity deinterleaver 1070, And outputs the L1 post signaling to the depadding unit 1080.

Specifically, the LDPC decoder 1021 performs LDPC decoding based on the output value of the parity deinterleaver 1070, and outputs the decoded result value to the BCH decoder 1022. The BCH decoder 1022 performs BCH decoding on the output value of the LDPC decoder 1021 and outputs the decoded result value to the depadding unit 1080.

Here, the output value of the LDPC decoder 1021 is divided into a BCH decoder 1022 in that it is composed of a segmented L1 post signaling, a zero bit added to the segmented L1 post signaling, and a plurality of bit strings including BCH parity bits. May correct the error using BCH parity bits and output a plurality of bit strings, each including a segmented L1 post signaling and a zero bit added to the segmented L1 post signaling, to the depadding unit 1080. [

The depadding unit 1080 may remove zero bits from the output value of the decoding unit 1020 and output the zero bits to the decompression unit 1090. [

Specifically, the de-padding unit 1080 is a component corresponding to the zero-padding unit 240 of the transmission apparatus 200, and may perform an operation corresponding to the zero-padding unit 240. [ That is, the demapping unit 1080 can remove the zero bits added by the zero padding unit 240 in each bit stream output from the BCH decoder 1022, and output a plurality of segmented L1 post signaling. To this end, information on the position and the number of zero bits added by the zero padding unit 240 may be provided from the transmitting apparatus 200 or stored in the receiving apparatus 1000.

Accordingly, the de-segment unit (or combiner) 1090 performs the de-segmentation on the output value of the depadding unit 1080.

Specifically, the decompression segment 1090 is a component corresponding to the segment segment 230 of the transmission apparatus 200, and can perform an operation corresponding to the segment segment 230. That is, since the plurality of segmented L1 post-signaling bits output from the depadding unit 1080 are in a state of being segmented by the transmitting apparatus 200, the de-segmenting unit 1080 includes a plurality of segmented The L1 post signaling is de-segmented to generate and output L1 post signaling in a state before being segmented.

On the other hand, information necessary for operation of each component may be provided from the transmission apparatus 200 or stored in the reception apparatus 1000. Herein, the information necessary for operation of each of the components may be multiplexed by a multiplexing method performed in the MUX 1040, a deinterleaving method performed in the deinterleaver 1050, a demultiplexing method performed in the demultiplexing unit 1010 and the demultiplexing unit 1060 Information on the position and number of LLR values, deinterleaving scheme performed by the parity deinterleaver 1070, order of de-segmented L1 post-signaling segmented by the de-segmenting unit 1080, and the like. In addition, the number of bits to be punctured may be calculated by the above-described method.

On the other hand, when the transmitting apparatus 200 processes and transmits the L1 post signaling using the components shown in FIG. 8, the receiving apparatus 1000 can process the L1 post signaling using the components shown in FIG. 11 .

However, when the transmitting apparatus 200 uses the components shown in FIG. 9, the receiving apparatus 1000 can process the L1 post signaling using the components shown in FIG. In this case, only the arrangement of the components is different from that described in FIG. 11, and the operations and the like performed in the respective components are the same. Therefore, the following description will focus on the above-described differences.

The LDPC decoder 1021 can output the bits generated as a result of decoding to the depadding unit 1080. In this case, the bits input to the depadding unit 1080 may be composed of segmented L1 post signaling, segmented L1 post signaling padded zero bits, and BCH parity bits.

The demapping unit 1080 may remove the zero bits from the bits output from the LDPC decoder 1021 and output the zero bits to the BCH decoder 1022.

Accordingly, the BCH decoder 1636 uses the BCH parity bits to correct the error, in that the bits input to the BCH decoder 1022 are composed of segmented L1 post signaling and BCH parity bits, and the segmented L1 post The signaling can be output to the decomposition segment 1090.

11 and 12, the receiving apparatus 1000 may further include a descrambler (not shown) when the scrambler (not shown) is used in the transmitting apparatus 200. [ A descrambler (not shown) may perform a function of outputting the bits to be input in reverse random order. 11, the descrambler (not shown) may be disposed between the depadding unit 1080 and the decompression unit 1090, and in the case of FIG. 12, the BCH decoder 1022 and the decompression unit Gt; 1090 &lt; / RTI &gt;

In the above example, the L1 post signaling is segmented and transmitted to the receiving apparatus 1000, but this is merely an example. That is, if the L1 post signaling has a length equal to or less than a certain value, it is of course possible that the L1 post signaling can be transmitted to the receiving apparatus 1000 without being segmented. In this case, the demodulation 1090 can output the L1 post signaling without any further demagnetization in that the bit stream input to the demodulation segment 1090 can be configured with L1 post-signaling.

13 is a flowchart illustrating a puncturing method of a transmitting apparatus according to an embodiment of the present invention.

First, the L1 post signaling is BCH (Bose, Chaudhuri, Hocquenghem) and LDPC (Low Density Parity Check) coding (S1310).

At least a portion of the LDPC parity bits among the LDPC codewords generated by the LDPC encoding is punctured (S1320). Here, the number of bits to be punctured is calculated based on the number of bits available for the LDPC codeword transmission and the modulation order of the L1 post signaling.

Specifically, step S1320 calculates the number of bits available for LDPC code word transmission, and calculates the number of bits to be punctured temporarily in the LDPC parity bit so that the number of bits of the LDPC code word is equal to the calculated number of bits. In this case, the number of bits available for transmission of the LDPC codeword can be calculated based on Equation (1) described above.

In addition, step S1320 may calculate the number of bits available for transmission of LDPC parity bits based on the number of bits available for LDPC code word transmission. In this case, the number of bits available for transmission of the LDPC parity bits can be calculated based on Equation (2). Here, Equation (2) may be expressed as Equation (3) as described above.

In step S1220, the number of bits to be punctured temporarily in the LDPC parity bit may be calculated to be equal to the number of bits available for transmission of the LDPC parity bit. In this case, the number of bits temporarily punctured in the LDPC parity bits can be calculated based on Equation (4). Here, Equation (4) may be expressed as Equation (5) as described above.

In step S1320, the number of bits of the LDPC codeword after puncturing is calculated based on the value excluding the number of bits temporarily punctured from the number of bits of the LDPC codeword, and the number of bits of the LDPC codeword after puncturing The number of bits to be punctured in the LDPC parity bit can be calculated.

Here, the number of LDPC codeword bits after puncturing can be calculated based on Equation (6) described above. The number of bits punctured in the LDPC parity bit can be calculated based on Equation (7).

Meanwhile, a non-transitory computer readable medium may be provided in which a program for sequentially performing the signal processing method according to the present invention is stored.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, the various applications or programs described above may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

Although the buses are not shown in the above-described block diagrams for the transmitting apparatus and the receiving apparatus, the communication between the respective elements in the transmitting apparatus and the receiving apparatus may be performed via the bus. Further, each apparatus may further include a processor such as a CPU, a microprocessor, or the like that performs the various steps described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.

200: transmitting apparatus 210:
220:

Claims (20)

1. A transmitter for processing L1 signaling comprising L1 pre-signaling and L1 post signaling,
A coding unit for performing BCH (Bose, Chaudhuri, Hocquenghem) and LDPC (Low Density Parity Check) coding on the L1 post signaling; And
A puncturing unit puncturing at least a portion of LDPC parity bits in an LDPC codeword generated by the LDPC encoding,
Wherein the number of bits to be punctured is a number
The number of bits available for the LDPC codeword transmission and the modulation order of the L1 post signaling. The method according to claim 1,
The puncturing unit includes:
The number of bits available for transmission of the LDPC codeword is calculated and the number of bits to be punctured temporarily in the LDPC parity bits so that the number of bits of the LDPC code word is equal to the calculated number of bits. Device. 3. The method of claim 2,
The puncturing unit includes:
To the number of bits available for the transmission of the LDPC codeword on the basis of Equation _L1post N _{_ _ avaiable} transmitting device to output the _bits, characterized in:

Here, N _{preamble _ avaiable _ cells} is the number of possible preamble cell used to send the L1 signaling, N _L1pre is the L1 pre number of bits in the signaling, η _{MOD _ L1pre} is the L1 modulation order of the pre-signaling, N _{L1post _ FECFRAME} is the number of LDPC codewords and &lt; _{EMI ID} = _1.0 & gt _; is the modulation order of the L1 post signaling. 3. The method of claim 2,
The puncturing unit includes:
And calculates the number of bits available for transmission of the LDPC parity bits based on the number of bits available for the LDPC code word transmission. 5. The method of claim 4,
The puncturing unit includes:
To the number of bits available for the transmission of the LDPC parity bits based on equation N _{L1post _ _ avaiable} transmission apparatus, characterized in that for calculating the _parity:

Here, N _{L1post _ avaiable _ bits} may be bits available in the LDPC codeword transmitted, K _sig is the number of bits of L1 signaling that is input to the encoder, N _{bch _ parity} is the BCH parity bits generated by the BCH encoding Number. 5. The method of claim 4,
The puncturing unit includes:
Wherein the number of bits to be punctured temporarily in the LDPC parity bits is calculated to be equal to the number of bits available for transmission of the LDPC parity bits. The method according to claim 6,
The puncturing unit includes:
To the number of bits to be punctured by a temporary pop in the LDPC parity bits based on equation N _{punc _} jingchi transmission, characterized in that for calculating the _temp:

Here, N _{ldpc parity _ _ L1post} is the number of bits of the LDPC parity bit, _{L1post_avaiable_parity} N is the number of bits available for transmission of the LDPC parity bits. 3. The method of claim 2,
The puncturing unit includes:
Calculating a number of bits of the LDPC codeword after puncturing based on the value of the number of bits of the LDPC codeword excluding the number of bits that are temporarily punctured and calculating the number of bits of the LDPC codeword after puncturing And calculates the number of bits punctured in the LDPC parity bits based on the number of bits. 9. The method of claim 8,
The puncturing unit includes:
And calculates the number of bits N _L1post of the LDPC codeword after puncturing based on the following equation:

Here, N _{L1post _ temp} is a value other than the number of bits to be punctured as the temporary number of bits in the LDPC codeword, η _{MOD _ L1post} is a modulation order of the L1 post-signaling. 9. The method of claim 8,
The puncturing unit includes:
And calculates the number N _punc of punctured bits in the LDPC parity bits based on the following equation:

Here, N _{punc _ temp} is the number of bits to be punctured by the temporary, N _L1post is the number of bits, N _L1post of the LDPC codeword after it has been punctured _{_ temp} may be punctured at the bit number of the LDPC codeword to the provisionally Is the value excluding the number of bits. 1. A puncturing method of a transmission apparatus for processing L1 signaling comprising L1 pre-signaling and L1 post signaling,
Performing BCH (Bose, Chaudhuri, Hocquenghem) and LDPC (Low Density Parity Check) coding on the L1 post signaling; And
Puncturing at least a portion of LDPC parity bits in an LDPC codeword generated by the LDPC encoding,
Wherein the number of bits to be punctured is a number
The number of bits available for the LDPC codeword transmission and the modulation order of the L1 post signaling. 12. The method of claim 11,
Wherein the puncturing comprises:
Calculating a number of bits available for the LDPC codeword transmission and calculating a number of bits to be punctured temporarily in the LDPC parity bits so that the number of bits of the LDPC code word is equal to the calculated number of bits; How to implement. 13. The method of claim 12,
Wherein the puncturing comprises:
To the number of bits available for the transmission of the LDPC codeword on the basis of Equation _L1post N _{_ _ avaiable} puncturing characterized in that for calculating the _bits:

Here, N _{preamble _ avaiable _ cells} is the number of possible preamble cell used to send the L1 signaling, N _L1pre is the L1 pre number of bits in the signaling, η _{MOD _ L1pre} is the L1 modulation order of the pre-signaling, N _{L1post _ FECFRAME} is the number of LDPC codewords and &lt; _{EMI ID} = _1.0 & gt _; is the modulation order of the L1 post signaling. 13. The method of claim 12,
Wherein the puncturing comprises:
And calculating the number of bits available for transmission of the LDPC parity bits based on the number of bits available for the LDPC code word transmission. 15. The method of claim 14,
Wherein the puncturing comprises:
On the basis of the equation to the number of bits available for the transmission of the LDPC parity bit _L1post N _{_ _ avaiable} puncturing characterized in that for calculating the _parity:

Here, N _{L1post _ avaiable _ bits} is the number of bits, K _sig available to the LDPC codeword transmission is the number of bits of L1 signaling that is encoded, N _{bch _ parity} is the number of the BCH parity bits generated by the BCH encoding . 15. The method of claim 14,
Wherein the puncturing comprises:
Wherein the number of bits to be punctured temporarily in the LDPC parity bits is calculated to be equal to the number of bits available for transmission of the LDPC parity bits. 17. The method of claim 16,
Wherein the puncturing comprises:
Puncturing method based on the equation of the following characterized in that the provisionally calculates the pop-bit number N _{punc temp _} are punctured in the LDPC parity bits:

Here, N _{ldpc parity _ _ L1post} is the number of bits of the LDPC parity bit, _{L1post_avaiable_parity} N is the number of bits available for transmission of the LDPC parity bits. 13. The method of claim 12,
Wherein the puncturing comprises:
Calculating a number of bits of the LDPC codeword after puncturing based on the value of the number of bits of the LDPC codeword excluding the number of bits that are temporarily punctured and calculating the number of bits of the LDPC codeword after puncturing And calculating a number of bits to be punctured in the LDPC parity bits based on the number of bits to be punctured. 19. The method of claim 18,
Wherein the puncturing comprises:
And calculating the number of bits N _L1post of the LDPC codeword after puncturing based on the following equation:

Here, N _{L1post _ temp} is a value other than the number of bits to be punctured as the temporary number of bits in the LDPC codeword, η _{MOD _ L1post} is a modulation order of the L1 post-signaling. 19. The method of claim 18,
Wherein the puncturing comprises:
Calculating a number N _punc of bits to be punctured in the LDPC parity bits based on the following equation: &lt; EMI ID =

Here, N _{punc _ temp} is the number of bits to be punctured by the temporary, N _L1post is the number of bits, N _L1post of the LDPC codeword after it has been punctured _{_ temp} may be punctured at the bit number of the LDPC codeword to the provisionally Is the value excluding the number of bits.

Images