KR20150025731A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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KR20150025731A
KR20150025731A KR20130103715A KR20130103715A KR20150025731A KR 20150025731 A KR20150025731 A KR 20150025731A KR 20130103715 A KR20130103715 A KR 20130103715A KR 20130103715 A KR20130103715 A KR 20130103715A KR 20150025731 A KR20150025731 A KR 20150025731A
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gate
gate portion
layer
hole accumulation
resistance
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KR20130103715A
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Korean (ko)
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KR102004768B1 (en
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서동수
박재훈
송인혁
오지연
엄기주
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삼성전기주식회사
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Priority to KR1020130103715A priority Critical patent/KR102004768B1/en
Priority to US14/451,030 priority patent/US20150060999A1/en
Publication of KR20150025731A publication Critical patent/KR20150025731A/en
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/435—Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET

Abstract

The present invention relates to a power semiconductor device which comprises: a drift layer of a first conductivity type; a hole accumulation layer of a first conductivity type formed on an upper part of the drift layer; a well layer of a second conductivity type formed on an upper part of the hole accumulation layer; an emitter region of a first conductivity type formed inside an upper part of the well layer; and a trench gate passing through the emitter region, the well layer, and the hole accumulation layer, and forming a gate insulating layer on a surface. A first gate unit, a second gate unit, and a third gate unit are divided from an upper part of the trench gate in accordance with the height of a material filled in the trench gate, and the first gate unit, the second gate unit, and the third gate unit have different resistance.

Description

[0001] Power semiconductor device [0002]

The present invention relates to a power semiconductor device having a low on resistance and simultaneously generating less noise.

An insulated gate bipolar transistor (IGBT) is a transistor having a bipolar transistor by forming a gate using MOS (Metal Oxide Silicon) and forming a p-type collector layer on the back surface.

Since the development of conventional power MOSFETs (Metal Oxide Silicon Field Emission Transistors), MOSFETs have been used in areas where high-speed switching characteristics are required.

However, bipolar transistors, thyristors and Gate Turn-off Thyristors (GTOs) have been used in areas where high voltage is required due to the structural limitations of MOSFETs.

IGBTs are characterized by low forward loss and fast switching speed and are applied to fields that could not be realized with conventional thyristors, bipolar transistors, MOSFETs (Metal Oxide Silicon Field Emission Transistors) The trend is expanding.

When the IGBT is turned on, a voltage higher than the cathode is applied to the anode, and when a voltage higher than the threshold voltage of the device is applied to the gate electrode, The polarity of the surface of the p-type well layer located at the lower end of the p-type well layer is reversed and an n-channel is formed.

The electron current injected into the drift region through the channel is injected from the high concentration p-type collector layer located under the IGBT element in the same manner as the base current of the bipolar transistor. Inducing current injection.

Concentration implantation of such minority carriers results in conductivity modulation in which the conductivity in the drift region increases from tens to hundreds of times.

Unlike a MOSFET, the resistance component in the drift region becomes very small due to the conductivity modulation, so that it can be applied at a very high voltage.

Various techniques have been developed to maximize the conductivity modulation phenomenon.

For example, there is a technique of maximizing the phenomenon of conductivity modulation by using a phenomenon in which holes are accumulated by forming a high concentration n-type semiconductor region in a lower portion of a p-type well layer.

As described above, the high concentration n-type semiconductor region formed in the lower portion of the well region is referred to as a hole accumulation layer.

In the case where the hole accumulation layer is formed, the accumulation amount of the holes increases greatly, so that the phenomenon of the conductivity modulation becomes very large. On the other hand, the holes accumulated in the hole accumulation layer affect the input signal of the trench gate.

That is, the trench gate is affected by the hole accumulation layer, which causes gate noise.

This gate noise shakes the stable supply of current.

In particular, when the switching frequency is high, the fluctuation range of the current becomes very large due to the gate noise.

Therefore, there is a need for a technique capable of reducing the gate noise while reducing the on resistance by maximizing the conductivity modulation phenomenon.

The invention disclosed in Patent Document 1 of the following prior art document relates to a power MOSFET including a low-resistance gate.

Specifically, the invention disclosed in Patent Document 1 is characterized in that a conductive seed layer is formed on the bottom of a trench, and a low-resistance material is grown thereon.

The invention disclosed in Patent Document 1 does not disclose that the resistance of a material formed in each trench is different depending on the height of each trench and does not disclose a hole accumulating layer, .

It is impossible to expect to obtain the same technical effect as the present invention due to the difference in the above-described configuration.

Korean Patent Publication No. 2008-0100209

The present invention seeks to provide a power semiconductor device which has a low on-resistance and at the same time less generation of switching noise.

A power semiconductor device according to an embodiment of the present invention includes a drift layer of a first conductivity type; A first conductive type hole accumulation layer formed on the drift layer; A well layer of a second conductivity type formed on the hole accumulation layer; An emitter region of the first conductivity type formed inside the upper portion of the well layer; And a trench gate penetrating the emitter region, the well layer, and the hole accumulation layer, and having a gate insulating layer formed on a surface thereof, wherein the material to be filled in the trench gate is a first A second gate portion, and a third gate portion, and the resistances of the first gate portion, the second gate portion, and the third gate portion may be different from each other.

In one embodiment, the first gate portion is formed at a portion corresponding to the height of the well layer, the second gate portion is formed at a portion corresponding to the height of the hole accumulation layer, And may be formed at a portion corresponding to the height of the layer.

In one embodiment, the resistance of the second gate portion may be higher than the resistance of the third gate portion.

In one embodiment, the resistance of the second gate portion may be higher than the resistance of the first gate portion.

In one embodiment, the first gate portion, the second gate portion, and the third gate portion may be electrically connected.

In one embodiment, the semiconductor device may further include an insulating member extending from the gate insulating layer at least one of the first gate portion and the second gate portion and between the second gate portion and the third gate portion have.

In one embodiment, the semiconductor device may further include a gate metal layer electrically connected to the first gate, the second gate, and the third gate and formed on an upper surface of the drift layer.

In one embodiment, the impurity concentration of the hole accumulation layer may be higher than the impurity concentration of the drift layer.

A power semiconductor device according to another embodiment of the present invention includes a drift layer of a first conductivity type; A plurality of trench gates having a predetermined interval in the drift layer and elongated in one direction and having a gate insulating layer on the surface; A well layer of a second conductivity type formed between the plurality of trench gates; An emitter region of the first conductivity type formed in the well layer so as to be in contact with the trench gate, the emitter region being formed at a predetermined interval in one direction; And a hole accumulation layer formed between the drift layer and the well layer, wherein the material to be filled in the trench gate is divided into a first gate portion, a second gate portion, and a third gate portion from an upper portion according to a height , And the resistances of the first gate portion, the second gate portion, and the third gate portion may be different from each other.

In another embodiment, the first gate portion is formed at a portion corresponding to the height of the well layer, the second gate portion is formed at a portion corresponding to the height of the hole accumulation layer, And may be formed at a portion corresponding to the height of the layer.

In another embodiment, the resistance of the second gate portion may be higher than the resistance of the third gate portion.

In another embodiment, the resistance of the second gate portion may be higher than the resistance of the third gate portion.

In another embodiment, the resistance of the second gate portion may be higher than the resistance of the first gate portion.

In another embodiment, the first gate portion, the second gate portion, and the third gate portion may be electrically connected.

In another embodiment, the insulating member may further include an insulating member extending from the gate insulating layer at least one of the first gate portion and the second gate portion and between the second gate portion and the third gate portion have.

In another embodiment, the impurity concentration of the hole accumulation layer may be higher than the impurity concentration of the drift layer.

In another embodiment, the semiconductor device may further include a gate metal layer formed on an upper surface of the drift layer, the gate metal layer being elongated in a direction perpendicular to the one direction at an end of the trench formed in one direction.

Since the resistance of the material filling the trench gate differs depending on the layer or the region in contact with the trench gate, even if the same current is applied to the material filling the trench gate, The electric field can be different.

Specifically, the portion of the trench gate corresponding to the height of the well layer is referred to as a first gate portion; A portion corresponding to the height of the hole accumulation layer is referred to as a second gate portion; When the portion corresponding to the height of the drift layer is referred to as a third gate portion, it is possible to prevent the gate voltage from fluctuating due to the holes accumulated in the hole accumulation layer by maximizing the resistance of the second gate portion.

By preventing the gate voltage from shaking, it is possible to minimize the occurrence of switching noise.

In addition, the resistance of the third gate may be minimized, so that when electrons are applied to the trench gate, electrons are attracted to the surface of the gate insulating layer of the third gate to prevent electrons from being scattered.

Since the electrons are not scattered, the inflow resistance of the electrons is reduced, thereby reducing the conduction loss.

1 is a schematic perspective view of a power semiconductor device according to an embodiment of the present invention.
2 is a schematic cross-sectional view showing flows of electrons and holes in an on operation of a power semiconductor device according to an embodiment of the present invention.
3 is a schematic side view of a power semiconductor device according to one embodiment of the present invention.
4 is a schematic cross-sectional view of a power semiconductor device according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below.

Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

The shape and size of elements in the drawings may be exaggerated for clarity.

The same reference numerals are used for the same components in the same reference numerals in the drawings of the embodiments

In the drawing, the x direction is defined as the width direction, the y direction is defined as the longitudinal direction, and the z direction is defined as the height direction.

The power switch may be implemented by any one of power MOSFET, IGBT, thyristor, and the like. Most of the novel techniques disclosed herein are described on the basis of IGBTs. However, the various embodiments of the present invention disclosed herein are not limited to IGBTs, and may be applied to other types of power switch technologies including power MOSFETs and various types of thyristors, in addition to diodes, for example. Moreover, various embodiments of the present invention are described as including specific p-type and n-type regions. However, it goes without saying that the conductivity types of the various regions disclosed herein can be equally applied to the opposite device.

The n-type and p-type used herein may be defined as a first conductive type or a second conductive type. On the other hand, the first conductive type and the second conductive type mean different conductive types.

In general, '+' means a state doped at a high concentration, and '-' means a state doped at a low concentration.

1 is a schematic perspective view of a power semiconductor device according to an embodiment of the present invention.

Hereinafter, a structure of a power semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

A power semiconductor device according to an embodiment of the present invention includes a drift layer 10 of a first conductivity type; A first conductive type hole accumulation layer (40) formed on the drift layer (10); A well layer 20 of a second conductivity type formed on the hole accumulation layer 40; An emitter region (30) of a first conductivity type formed inside the upper portion of the well layer (20); And a trench gate (50) penetrating the emitter region (30), the well layer (20), and the hole accumulation layer (40) and having a gate insulating layer (52) formed on the surface thereof. The material to be filled in the trench gate 50 is divided into a first gate portion 51a, a second gate portion 51b and a third gate portion 51c from the top depending on the height, The resistances of the electrodes 51a, 51b, and 51c may be different from each other.

In addition, the structure of the power semiconductor device according to an embodiment of the present invention includes a drift layer 10 of a first conductivity type; A plurality of trench gates (50) formed on the drift layer (10) at predetermined intervals and elongated in one direction and having a gate insulating layer (52) on the surface; A second conductivity type well layer (20) formed between the plurality of trench gates (50); An emitter region (30) of the first conductivity type formed in the well layer (20) so as to be in contact with the trench gate (50) and formed at a predetermined interval in one direction; And a hole accumulation layer (40) formed between the drift layer (10) and the well layer (20), wherein the material filling the trench gate (50) The second gate portion 51b and the third gate portion 51c and the resistances of the first to third gate portions 51a, 51b and 51c may be different from each other.

Specifically, the first gate portion 51a is formed at a portion corresponding to the height of the well layer 20, and the second gate portion 51b is formed at a portion corresponding to the height of the hole accumulation layer 40 And the third gate portion 51c may be formed at a portion corresponding to the height of the drift layer 10. [

The first conductivity type may be n-type, and the second conductivity type may be p-type.

The drift layer 10 may be formed to have a low concentration n-type conductivity type impurity in order to maintain the breakdown voltage of the device.

An emitter metal layer 60 may be formed on the exposed top surface of the well layer 20 and on the exposed top surface of the collector area 30. [

A buffer layer 11 may be further formed under the drift layer 10.

The buffer layer 11 may be an n + type or a p + type. In the case of the n + type, the buffer layer 11 may operate as a MOSFET. In the case of the p + type, the buffer layer may function as an IGBT.

The buffer layer 11 may further include a collector metal layer 70 under the buffer layer 11.

In the case of the IGBT, since the buffer layer 11 is p + type, holes can be injected when the power semiconductor element is turned on.

Conductivity modulation phenomenon in which the conductivity in the drift layer 10 is increased by tens to hundreds of times is caused by the high concentration of holes injected.

In order to maximize the conductivity modulation phenomenon, a hole accumulation layer 40 of the first conductivity type may be formed on the drift layer 10.

The hole accumulation layer 40 has the same conductivity type as the drift layer 10, but may have a much higher impurity concentration than the drift layer 10.

Specifically, the hole accumulation layer 40 may have an n + -type conductivity type.

Since the hole accumulation layer 40 has a high concentration of n-type impurities, the holes injected from the buffer layer 11 are accumulated in the hole accumulation layer 40.

Therefore, holes are accumulated at a high concentration in the lower portion of the well layer 20, thereby maximizing the conductivity modulation phenomenon.

However, when excessive holes accumulate in the hole accumulation layer 40, the voltage applied to the trench gate 50 is affected by the charge of the holes.

That is, the voltage applied to the trench gate 50 is shaken by the holes of the hole accumulation layer 40, and noise is generated when the power semiconductor device performs the switching operation.

Therefore, there is a limit in raising the impurity concentration of the first conductivity type (n-type) of the hole accumulation layer 40 to a predetermined value or more.

A power semiconductor device according to an embodiment of the present invention includes a first gate portion 51a, a portion corresponding to a height of the well layer 20, according to a height of a material to be filled in the trench gate 50; A portion corresponding to the height of the hole accumulation layer 40 is referred to as a second gate portion 51b; The resistance of the first to third gate portions 51a, 51b and 51c may be different from each other when the portion corresponding to the height of the drift layer 10 is referred to as a third gate portion 51c.

The gate voltage required depends on the height of the well layer 20, the hole accumulation layer 40, and the drift layer 10.

Hereinafter, with reference to FIG. 2, the gate voltage required for each layer will be described.

2 is a schematic cross-sectional view showing flows of electrons and holes in an on operation of a power semiconductor device according to an embodiment of the present invention.

The well layer 20 is a portion where a channel is formed during an on operation of the power semiconductor device.

During the on operation of the power semiconductor device, a + voltage is applied to the trench gate.

Accordingly, electrons are attracted to the surface of the trench gate 50 by the + electric field formed by the + voltage, as shown in FIG. 2, and a conductive channel is formed in the well layer 20 to form a gap between the emitter and the collector Current flows.

The conductive channel is related to a turn-on voltage (Vth), and the well layer 20 is closely related to the breakdown voltage of the device.

Since the well layer 20 affects various characteristics of the device, the resistance of the first gate 51a should be adjusted in consideration of such characteristics.

The hole accumulation layer 40 is formed to maximize the conductivity modulation phenomenon of the power semiconductor device.

That is, since the hole accumulation layer 40 is formed by injecting a high concentration n-type impurity, holes are accumulated in the hole accumulation layer 40, as shown in FIG.

Since the holes have positive charges, the holes accumulated in the hole accumulation layer 40 generate both electric fields.

The electric field generated in the holes affects the second gate portion 51b.

Let's look at this in detail.

Since a large amount of positively charged holes are accumulated in the hole accumulation layer 40, a strong positive electric field is generated by the accumulated holes in the hole accumulation layer 40.

When a positive voltage is applied to the second gate portion 51b, a positive hole having a positive charge is generated in the second gate portion 51b. The positive electric field generated by the holes accumulated in the hole accumulation layer 40 The holes generated in the second gate portion 51b are pushed out to the periphery.

That is, since the holes generated in the second gate portion 51b are pushed to the first gate portion 51a, the first gate portion 51a has a higher concentration of holes than the conventional gate.

Therefore, the first gate portion 51a has a strong positive electric field due to a high hole concentration, and attracts more electrons to the surface of the trench gate 50 corresponding to the height of the first gate portion 51a .

As a result, the Vth voltage is increased, and further, a wider channel is formed and more current flows.

As the above-described phenomenon is repeated, the voltage applied to the trench gate 50 is shaken and the current waveform is shaken to generate noise.

Therefore, by increasing the resistance of the second gate portion 51b, it is possible to prevent noise from being generated by reducing the amount of holes generated in the second gate portion 51b.

In addition, since holes move very slowly compared to electrons, they can not disappear rapidly when the power semiconductor device switches to an off operation.

Therefore, even when the power semiconductor device switches off operation, the holes accumulated in the hole accumulation layer 40 still affect the second gate portion 51b.

Therefore, when the power semiconductor device is switched off, the voltage applied to the second gate portion 51b is shaken by the holes accumulated in the hole accumulation layer 40, and switching noise is generated.

In order to reduce the switching noise, the resistance of the second gate portion 51b may be set to a high value.

By increasing the resistance of the second gate portion 51b, it is possible to reduce the influence of the electric field generated by the holes accumulated in the hole accumulation layer 40, on the second gate portion 51b.

That is, since the resistance of the second gate portion 51b is high, even if the holes accumulated in the hole accumulation layer 40 affect the second gate portion 51b, the second gate portion 51b, So that the voltage applied to the gate electrode is damped.

The voltage applied to the second gate portion 51b is insensitive to the electric field generated by the holes accumulated in the hole accumulation layer 40, so that the switching noise is remarkably reduced.

The third gate portion 51c formed at a height corresponding to the drift layer 10 may be formed to have a low resistance.

Since the third gate portion 51c has a low resistance, when a voltage is applied, a voltage drop is small and a relatively high voltage is obtained.

Therefore, when the power semiconductor device is turned on as shown in FIG. 2, electrons are attracted to the periphery of the third gate portion 51c.

That is, electrons can be prevented from scattering by attracting more electrons to the third gate portion 51c.

Since the electrons are not scattered, the inflow resistance of the electrons is reduced, thereby reducing the conduction loss.

The first gate portion 51a, the second gate portion 52b, and the third gate portion 52c may be connected to one gate metal layer.

Since the first to third gate portions 51a, 51b and 51c are connected to the same gate metal layer, the first to third gate portions 51a, 51b and 51c may be electrically connected to each other.

That is, the same voltage may be applied to the first to third gate portions 51a, 51b, and 51c. .

However, since the first to third gate portions 51a, 51b, and 51c have different resistance values, even if the same voltage is applied, they have different voltages due to the voltage drop.

Specifically, when the resistance of the second gate portion 51b is higher than the resistance of the third gate portion 51c, even if the same voltage is applied to the second and third gate portions 51b and 51c by the gate metal layer The voltage of the second gate part 51b becomes lower than the voltage of the third gate part 51c.

Accordingly, the second gate portion 51b is insensitive to an electric field generated in the charge accumulated in the hole accumulation layer 40, and the third gate portion 51c is formed on the surface of the third gate portion 51c You can attract more electrons.

Therefore, the power semiconductor device according to an embodiment of the present invention can simultaneously achieve two effects, namely, reduction in switching noise and reduction in on resistance.

As another example, when the resistance of the second gate portion 51b is higher than the resistance of the first gate portion 51a, even if the same voltage is applied to the first and second gate portions 51a and 51b by the gate metal layer The voltage drop of the first gate portion 51a becomes smaller than the voltage drop of the second gate portion 51b.

That is, it is possible to precisely control the voltage of the first gate part 51a to be higher than the voltage of the second gate part 51b.

Therefore, the voltage of the first gate part 51a can be precisely adjusted to adjust the power semiconductor device to have a good performance, and to reduce the switching noise.

The trench gate 50 may be formed by etching the drift layer 10, forming a gate insulating layer 52 on the surface, and filling the inside with polysilicon.

The polysilicon may be charged by doping a material capable of controlling resistance according to the first gate 51a, the second gate 51b and the third gate 51c.

For example, polysilicon filled in the second gate portion 51b may be formed by doping a high-resistance material, and polysilicon filled in the third gate portion 51c may be doped with a low- .

Different materials may be filled in the first to third gate portions 51a, 51b and 51c, respectively, if the resistance is different.

3 is a schematic side view of a power semiconductor device according to one embodiment of the present invention.

The power semiconductor device according to an embodiment of the present invention is electrically connected to the first gate 51a, the second gate 51b and the third gate 51c, and the drift layer 10, And a gate metal layer 80 formed on an upper surface of the gate electrode layer 80.

The gate metal layer 80 may be formed to extend in the direction perpendicular to the one direction at the end of the trench gate 40 formed in the one direction when the power semiconductor device is viewed from above.

4 is a schematic cross-sectional view of a power semiconductor device according to another embodiment of the present invention.

Referring to FIG. 4, the power semiconductor device according to another embodiment of the present invention includes the first gate part 51a and the second gate part 51b, and the second gate part 51b and the third gate part 51b. And an insulating member 53 extending from the gate insulating layer 52 at least one of the gate portions 51c.

The insulating member 53 does not completely insulate the first to third gate portions 51a, 51b and 51c but narrows the width of the portion where the first to third gate portions 51a, 51b and 51c are connected can do.

The embodiments described above are not independent from each other, and the embodiments can be combined.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken as a limitation upon the scope of the invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

10: drift layer
11: buffer layer
20: Well layer
30: Emitter area
40: hole accumulation layer
50: trench gate
51a: first gate portion
51b:
51c: third gate portion
52: Gate insulating layer
60: Emitter metal layer
70: collector metal layer
80: gate metal layer

Claims (16)

A drift layer of a first conductivity type;
A first conductive type hole accumulation layer formed on the drift layer;
A well layer of a second conductivity type formed on the hole accumulation layer;
An emitter region of the first conductivity type formed inside the upper portion of the well layer; And
And a trench gate penetrating the emitter region, the well layer, and the hole accumulation layer, and having a gate insulating layer formed on a surface thereof,
Wherein the material filled in the trench gate,
A first gate portion, a second gate portion, and a third gate portion,
And the resistances of the first gate portion, the second gate portion, and the third gate portion are different from each other. The method according to claim 1,
Wherein the first gate portion is formed at a portion corresponding to the height of the well layer,
The second gate portion is formed at a portion corresponding to the height of the hole accumulation layer,
And the third gate portion is formed at a portion corresponding to the height of the drift layer. The method according to claim 1,
Wherein the resistance of the second gate portion is higher than the resistance of the third gate portion. The method according to claim 1,
Wherein the resistance of the second gate portion is higher than the resistance of the first gate portion. The method according to claim 1,
And the first gate portion, the second gate portion, and the third gate portion are electrically connected to each other. The method according to claim 1,
And an insulating member extending from the gate insulating layer at least one of the first gate portion and the second gate portion and the second gate portion and the third gate portion. The method according to claim 1,
And a gate metal layer electrically connected to the first gate portion, the second gate portion, and the third gate portion, the gate metal layer being formed on an upper surface of the drift layer. The method according to claim 1,
And the impurity concentration of the hole accumulation layer is higher than the impurity concentration of the drift layer. A drift layer of a first conductivity type;
A plurality of trench gates having a predetermined interval in the drift layer and elongated in one direction and having a gate insulating layer on the surface;
A well layer of a second conductivity type formed between the plurality of trench gates;
An emitter region of the first conductivity type formed in the well layer so as to be in contact with the trench gate, the emitter region being formed at a predetermined interval in one direction;
And a hole accumulation layer formed between the drift layer and the well layer,
Wherein the material filled in the trench gate,
A first gate portion, a second gate portion, and a third gate portion,
And the resistances of the first gate portion, the second gate portion, and the third gate portion are different from each other. 10. The method of claim 9,
Wherein the first gate portion is formed at a portion corresponding to the height of the well layer,
The second gate portion is formed at a portion corresponding to the height of the hole accumulation layer,
And the third gate portion is formed at a portion corresponding to the height of the drift layer. 10. The method of claim 9,
Wherein the resistance of the second gate portion is higher than the resistance of the third gate portion. 10. The method of claim 9,
Wherein the resistance of the second gate portion is higher than the resistance of the first gate portion. 10. The method of claim 9,
And the first gate portion, the second gate portion, and the third gate portion are electrically connected to each other. 10. The method of claim 9,
And an insulating member extending from the gate insulating layer at least one of the first gate portion and the second gate portion and the second gate portion and the third gate portion. 10. The method of claim 9,
And the impurity concentration of the hole accumulation layer is higher than the impurity concentration of the drift layer. 10. The method of claim 9,
A trench formed in the trench in a direction perpendicular to the one direction,
And a gate metal layer formed on an upper surface of the drift layer.
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