KR20150014281A

KR20150014281A - IC reset circuit and method thereof

Info

Publication number: KR20150014281A
Application number: KR1020130089758A
Authority: KR
Inventors: 이재순
Original assignee: 삼성전기주식회사
Priority date: 2013-07-29
Filing date: 2013-07-29
Publication date: 2015-02-06

Abstract

The present invention relates to an IC reset circuit and a method thereof.
According to another aspect of the present invention, there is provided a power supply apparatus including: a power supply unit generating and outputting a power supply signal; A reset signal output unit for outputting a reset signal when the power supply signal of the power supply unit falls below a predetermined reference voltage; And a reset signal processing unit for delaying the reset signal output from the reset signal output unit and outputting the delayed signal to the IC chip, and a method thereof.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC reset circuit,

The present invention relates to an IC reset circuit and a method thereof.

Currently, many devices that use IC chips (IC chips) are widely used in our daily life.

For example, almost all IC chips are used in mobile phones, MP3, DMB, PMP, Navy and other consumer electronics controllers.

As electronic products change from analog to digital markets, more discrete circuits have been replaced with IC chips.

Typically, the IC chip has a reset state in which various circuits of the IC chip are initialized before normal operation is started.

For example, a reset state is entered when the power is first turned on or when an internal or external condition occurs that may suspend the normal operation of the IC chip.

When the reset state is input, the IC chip is initialized to a known state, and then normal operation is permitted.

A typical IC chip has a reset pin for receiving an external reset signal for resetting the IC chip due to interruption of the power supply as described above.

That is, a hardware reset pin is added to the IC chip to smoothly operate the operation of the IC chip and the power consumption, and these pins are operated with a power sequence.

The conventional IC has a structure in which the input voltage Vin is simultaneously applied to the VCC stage and the reset stage.

In this case, the reset stage is set to match the power sequence from the outside by a normal method.

However, in this case, the operation is performed in a normal environment, and the ESD or shock causes the power to be excited by external influences, resulting in a failure of normal operation.

In case of the above-mentioned phenomenon, if it is controllable from the outside, the idle state can be released by externally controlling and resetting by hardware, but in case of the system that is automatically returning, a reset sequence is artificially created from the outside, I have a problem that needs to be done.

Korean Patent Laid-Open Publication No. 1999-0045152 Korean Patent Laid-Open Publication No. 2000-0043620

According to an aspect of the present invention, there is provided an IC reset circuit including an AND gate circuit for receiving a reset signal and a reset signal, And to provide such a method.

According to an aspect of the present invention, there is provided a power supply apparatus including: a power supply unit generating and outputting a power supply signal; A reset signal output unit for outputting a reset signal when the power supply signal of the power supply unit falls below a predetermined reference voltage; And a reset signal processing unit for delaying the reset signal output from the reset signal output unit and outputting the delayed signal to the IC chip.

The reset signal processing unit of the present invention delays the reset signal until a time when a signal output from the power supply unit is recovered to a predetermined reference voltage or higher, and outputs the delayed reset signal.

The reset signal output unit of the present invention receives a power supply signal from a power supply unit, receives a reset signal from a reset signal output unit, and performs a logical OR to output the reset signal.

According to another aspect of the present invention, the AND gate circuit receives a power supply signal from a power supply unit, receives a reset signal from a reset signal output unit and performs a logical OR to output a reset signal to the power supply unit, The output of the reset signal is delayed.

The reset signal processing unit of the present invention is located between the output terminal of the reset signal output unit and the ground and receives the output signal of the reset signal output unit and outputs the delayed signal to the IC chip.

The reset signal processing unit according to an aspect of the present invention further includes a resistance element positioned between the output terminal of the reset signal output unit and the capacitor.

According to another aspect of the present invention, the reset signal output unit is a comparator that receives a power supply signal from the power supply unit and outputs a reset signal when the power supply signal of the power supply unit falls below a predetermined reference voltage.

According to another aspect of the present invention, there is provided a method of driving a plasma display panel, comprising the steps of: (A) outputting a power supply signal falling below a predetermined reference voltage while the power supply unit is maintaining a constant voltage; (B) outputting a reset signal when the reset signal output unit is turned off when the power supply signal of the power supply unit falls below a predetermined reference voltage; And (C) the reset signal processing unit delays the reset signal output from the reset signal output unit and outputs the delayed signal to the IC chip.

According to another aspect of the present invention, in the step (C), the reset signal processing unit delays the reset signal until a time when a signal output from the power supply unit is recovered to a predetermined reference voltage or more.

In another aspect of the present invention, the step (C) includes the steps of: (C-1) receiving the power supply signal from the power supply unit by the AND gate circuit constituting the reset signal output unit; (C-2) the AND gate circuit receiving a reset signal at a reset signal output unit; And (C-3) the AND gate circuit performing a logical OR of the power supply signal and the reset signal and outputting the logical sum.

According to another aspect of the present invention, in the step (C-3), the AND gate circuit performs a logical OR of a power supply signal and a reset signal, and outputs a reset signal until a signal output from the power supply unit is restored to a predetermined reference voltage or higher And outputs the delayed reset signal.

According to another aspect of the present invention, the step (C) includes the steps of: (C-1) receiving a reset signal from a reset signal output unit of a capacitor constituting the reset signal processing unit; And (C-2) the capacitor delays and outputs the reset signal.

Prior to this, terms and words used in the present specification and claims should not be construed in a conventional, dictionary sense, and should not be construed as defining the concept of a term appropriately in order to describe the inventor in his or her best way. It should be construed in accordance with the meaning and concept consistent with the technical idea of the present invention.

According to the present invention, it is possible to prevent an IC from being left in a system malfunction state due to a sequence between a reset signal and a power source, have.

1 is a configuration diagram of an IC reset circuit according to an embodiment of the present invention.
Fig. 2 is a signal waveform diagram of the IC reset circuit of Fig. 1 in a steady state. Fig.
Fig. 3 is a waveform diagram of each signal in the abnormal state of the IC reset circuit of Fig. 1. Fig.
4 is a configuration diagram of the reset signal output unit of FIG.
5 is a configuration diagram of an IC reset circuit according to another embodiment of the present invention.
6 is a flowchart of an IC reset method according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, specific advantages and novel features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements are assigned the same number as much as possible even if they are displayed on different drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an IC reset circuit according to the present invention.

Referring to FIG. 1, the reset circuit of the IC according to the present invention includes a power supply unit 10, a reset signal output unit 20, and a reset signal processing unit 30. Here, the reset signal processing section 30 includes an AND gate circuit 31.

The power supply unit 10 is connected to a power input terminal of the IC chip 1 and supplies power to the IC chip 1. [

The power supply unit 10 supplies power to the reset signal output unit 20.

Also, the power supply unit 10 supplies power to the power input terminal of the AND gate circuit 31, which is the reset signal processing unit 30.

The reset signal output section 20 outputs a reset signal to the reset signal input terminal of the AND gate circuit 31. [

The reset signal output unit 20 outputs a reset signal when the power supplied from the power supply unit 10 is higher than the first reference voltage.

The reset signal output unit 20 outputs a reset signal when the power supplied from the power supply unit 10 falls below the second reference voltage.

The AND gate circuit 31 receives power from the power supply unit 10 through a power input terminal and receives a reset signal from the reset signal output unit 20 to perform a logical sum operation and outputs a reset signal corresponding to the reset signal to the IC And outputs it to the reset signal input terminal of the chip 1.

The operation of the IC reset circuit according to the present invention will now be described.

First, in a normal state, the power supply unit 10 supplies a signal having a rising time t1 shown in (a) of FIG. 2 to the reset signal output unit 20, the AND gate circuit 31, and the IC chip 1).

At this time, when a signal having a rise time t1 shown in FIG. 2A is inputted from the power supply unit 10 at the power supply unit 10, the reset signal output unit 20 outputs a reset And outputs a signal.

An example of a reset signal output from the reset signal output unit 20 is shown in FIG. 2 (b). The reset signal is generated at a time point when the magnitude of the voltage output from the power supply unit 10 is set to a certain value Depending on the reference voltage.

The AND gate circuit 31 performs a logical OR of the power supplied from the power supply unit 10 and the reset signal output from the reset signal output unit 20 so that the power supplied from the power supply unit 10 is not less than a predetermined reference value And outputs a reset signal to the IC chip 1 when the voltage of the reset signal output from the reset circuit output section 20 becomes equal to or higher than a predetermined reference value.

In the normal state, the AND gate circuit 31 causes the voltage supplied from the power supply unit 10 of FIG. 2A to be equal to or higher than a predetermined reference value (V1, first reference voltage) The reset signal output from the reset signal output unit 20 is the same as the reset signal output from the reset signal output unit 20.

In an abnormal state, the power supply unit 10 provides the signal shown in FIG. 3A to the reset signal output unit 20, the AND gate circuit 31, and the IC chip 1.

This abnormal condition occurs when ESD or shock causes the power to run out due to external influences and the normal operation can not be performed.

At this time, the reset signal output unit 20 outputs a reset signal at a time when a voltage shown in FIG. 3A is inputted from the power supply unit 10 to a voltage equal to or lower than a predetermined magnitude (V2, second reference voltage) do.

An example of a reset signal output from the reset signal output unit 20 is shown in FIG. 3 (b). The reset signal is generated when the magnitude of the voltage output from the power supply unit 10 is set to a certain value Depending on the reference voltage.

The AND gate circuit 31 performs a logical OR of the power supplied from the power supply unit 10 and the reset signal output from the reset signal output unit 20 so that the power supplied from the power supply unit 10 is not less than a predetermined reference value When the voltage of the reset signal output from the reset circuit output portion 20 becomes equal to or higher than a certain reference value (this reference value becomes the first reference voltage), the IC chip 1) to output a reset signal as shown in (c) of FIG.

In the abnormal state, the AND gate circuit 31 does not output the reset signal because the condition that the voltage supplied from the power supply unit 10 of FIG. 3 (a) is below a certain reference value does not satisfy this condition.

If the voltage supplied from the power supply unit 10 of FIG. 3 (a) is recovered to a predetermined reference value or more, the voltage supplied from the power supply unit 10 becomes equal to or higher than a predetermined reference value, The AND gate circuit 31 outputs a reset signal.

According to the present invention as described above, a reset signal is input to the reset terminal of the IC when the signal input to the VCC stage becomes a voltage equal to or greater than a predetermined magnitude under abnormal conditions, thereby reducing the error rate of the IC.

That is, according to the present invention, it is possible to prevent a state in which the IC is left in a system malfunction state due to a sequence between a reset signal and a power source and remains in an idle state without performing a normal operation It is effective.

4 is a configuration diagram of the reset signal output unit of FIG.

Referring to FIG. 4, the reset signal output unit of FIG. 1 includes a first comparator 21 and a second comparator 22.

The first comparator 21 receives power from the power supply unit 10 and receives a first reference voltage V1 at a reference voltage input terminal. The first comparator 21 receives the first reference voltage V1 from the power supply unit 10, And outputs a reset signal when it becomes larger.

The second comparator 22 receives power from the power supply unit 10 and receives a second reference voltage V2 at a reference voltage input terminal. The second comparator 22 receives the second reference voltage V2 from the power supply unit 10, V2), the reset signal is outputted.

In the above configuration, the first comparator 21 outputs a reset signal when normal power is supplied from the power supply unit 10, and the second comparator 22 outputs a reset signal when the abnormal power is supplied from the power supply unit 10 And outputs a reset signal.

5 is a configuration diagram of an IC reset circuit according to another embodiment of the present invention.

5, an IC reset circuit according to another embodiment of the present invention includes a reset signal processing unit 30 and a reset signal output unit 20. The reset signal processing unit 30 includes a resistive element R1 and a resistive element R1, And a capacitor C1 connected between the other terminal and the ground.

The reset signal processing unit 30 including the resistor R1 and the capacitor C1 delays a reset signal output from the reset signal output unit 20 in an abnormal state by a predetermined time.

As a result, a reset signal is input to the reset terminal of the IC when the signal input to the VCC stage becomes a voltage equal to or greater than a predetermined magnitude under abnormal conditions, thereby reducing the error occurrence rate of the IC.

6 is a flowchart of an IC reset method according to an embodiment of the present invention.

Referring to FIG. 6, in the IC reset method according to the embodiment of the present invention, first, in a normal state, the power supply unit 10 resets a signal having a rising time t1 shown in FIG. The signal output unit 20, the reset signal processing unit 30, and the IC chip 1 (S110).

At this time, when a signal having a rise time t1 shown in FIG. 2A is inputted from the power supply unit 10 at the power supply unit 10, the reset signal output unit 20 outputs a reset And outputs a signal (S112).

When the reset signal processing unit 30 is the AND gate circuit 31, the power supply unit 10 performs the logical OR of the power supplied from the power supply unit 10 and the reset signal output from the reset signal output unit 20, When the voltage of the reset signal output from the reset circuit output section 20 becomes equal to or greater than a predetermined reference value, the reset signal (reset signal) is supplied to the IC chip 1, (S114).

Alternatively, when the reset signal processing unit 30 includes the resistor Rl and the capacitor C1 of FIG. 5, the reset signal processing unit 30 outputs a delayed reset signal.

When the reset signal is input from the reset signal processing unit 30, the IC chip 1 performs a reset operation (S116).

In the abnormal state, the power supply unit 10 provides the signal shown in FIG. 3A to the reset signal output unit 20, the reset signal processing unit 30, and the IC chip 1 (S118).

At this time, the reset signal output unit 20 outputs a reset signal at a time when a voltage shown in FIG. 3A is inputted from the power supply unit 10 to a voltage equal to or lower than a predetermined magnitude (V2, second reference voltage) (S120).

When the AND gate circuit 31 is used in the reset signal processing unit 30, the power supply unit 10 performs a logical OR of the power supplied from the power supply unit 10 and the reset signal output from the reset signal output unit 20, 10) becomes equal to or greater than a predetermined reference value (this reference value becomes the first reference voltage), and the voltage of the reset signal output from the reset circuit output section 20 is a predetermined reference value 3 >), the IC chip 1 outputs a reset signal as shown in Fig. 3 (c).

If the voltage supplied from the power supply unit 10 of FIG. 3 (a) is recovered to a predetermined reference value or more, the voltage supplied from the power supply unit 10 becomes equal to or higher than a predetermined reference value, The AND gate circuit 31 outputs a reset signal (S122).

When the reset signal is input from the reset signal processing unit 30, the IC chip 1 performs a reset operation (S124).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. And changes may be made without departing from the spirit and scope of the invention.

1: IC chip 10: Power supply unit
20: reset signal output unit 21, 22: comparator
30: reset signal processing unit 31: AND gate circuit

Claims

A power supply unit for generating and outputting a power supply signal;
A reset signal output unit for outputting a reset signal when the power supply signal of the power supply unit falls below a predetermined reference voltage; And
And a reset signal processing section for delaying the reset signal output from the reset signal output section and outputting the delayed signal to the IC chip.

The method according to claim 1,
Wherein the reset signal processing unit delays the reset signal until a time point at which the signal output from the power supply unit is recovered to a predetermined reference voltage or higher, and outputs the delayed reset signal.

The method according to claim 1,
Wherein the reset signal output unit is an AND gate circuit that receives a power supply signal from a power supply unit, receives a reset signal from a reset signal output unit, and performs an OR operation to output the reset signal.

The method of claim 3,
The AND gate circuit receives a power supply signal from a power supply unit, receives a reset signal from the reset signal output unit, performs a logical OR operation, and outputs a reset signal until a signal output from the power supply unit is recovered to a predetermined reference voltage or higher An IC reset circuit for delaying and outputting.

The method according to claim 1,
Wherein the reset signal processing unit is a capacitor which is located between an output terminal of the reset signal output unit and the ground and receives the output signal of the reset signal output unit and outputs the delayed output to the IC chip.

The method of claim 5,
Wherein the reset signal processing section further comprises a resistance element positioned between the output terminal of the reset signal output section and the capacitor.

The method according to claim 1,
Wherein the reset signal output unit is a comparator that receives a power supply signal from the power supply unit and outputs a reset signal when the power supply signal of the power supply unit falls below a predetermined reference voltage.

(A) outputting a power supply signal falling below a predetermined reference voltage while the power supply unit is maintaining a constant voltage;
(B) outputting a reset signal when the reset signal output unit is turned off when the power supply signal of the power supply unit falls below a predetermined reference voltage; And
(C) the reset signal processing unit delays the reset signal output from the reset signal output unit and outputs the delayed signal to the IC chip.

The method of claim 8,
Wherein the reset signal processing unit delays the reset signal until a time point when the signal output from the power supply unit is recovered to a predetermined reference voltage or higher.

The method of claim 8,
The step (C)
(C-1) an AND gate circuit constituting the reset signal output unit receiving a power supply signal from a power supply unit;
(C-2) the AND gate circuit receiving a reset signal at a reset signal output unit; And
(C-3) the AND gate circuit performing a logical sum of the power supply signal and the reset signal and outputting the same.

The method of claim 10,
In the step (C-3), the AND gate circuit performs an OR operation between the power supply signal and the reset signal to output a reset signal to the IC, which delays the reset signal until the signal output from the power supply unit is recovered to a predetermined reference voltage or higher Reset method.

The method of claim 8,
The step (C)
(C-1) receiving a reset signal from a reset signal output unit of a capacitor constituting the reset signal processing unit; And
(C-2) the capacitor delays and outputs the reset signal.