JP7216539B2 - switching control circuit - Google Patents

Description

The present invention relates to a switching control circuit for controlling on/off of switching elements.

2. Description of the Related Art In recent years, vehicle-related devices have become more computerized, and demand for communication ICs (Integrated Circuits) has increased. However, since the communication IC is a source of noise, it is necessary to strengthen measures against noise in order to improve the reliability of on-vehicle equipment.

Also, in electrical equipment such as personal computers and portable equipment, since the integration and miniaturization of circuits are progressing, there is a demand for enhanced noise countermeasures.

Japanese Patent Application Laid-Open No. 2006-129593 (Fig. 3)

The switching regulator proposed in Patent Document 1 suppresses noise generated from the switching regulator by slowing the slew rate of a control signal that drives a switching element when a device susceptible to noise is in the ON state. making it smaller.

However, in the switching regulator proposed in Patent Document 1, the slew rate of the control signal that drives the switching element is fixed when the device susceptible to noise is in the ON state. The resulting EMI noise frequency is concentrated on a specific frequency. This increases the peak value of EMI noise at a specific frequency.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a switching control circuit capable of reducing the peak value of EMI noise generated when switching elements are driven.

To achieve the above object, a switching control circuit according to the present invention includes: a first current source; a second current source; a first switch provided between the first current source and a gate of a switching element; a second switch provided between the second current source and the gate of the switching element, wherein the first switch and the second switch are complementarily turned on/off in response to a pulse signal to perform the switching; The value of the current supplied to the gate of the switching element by the first current source at one of both edges of each pulse of the signal generated according to the on/off of the element varies and/or both edges On the other hand, the value of the current extracted from the gate of the switching element by the second current source is variable (first configuration).

Further, in the switching control circuit having the first configuration, an integrated value of the current supplied to the gate of the switching element on one of the two edges and the current extracted from the gate of the switching element on the other of the edges may be substantially constant (second configuration).

In the switching control circuit having the first or second configuration, the value of the current supplied to the gate of the switching element by the first current source is variable at one of the edges, and The current source comprises a plurality of first sub-current sources, each of the plurality of first sub-current sources has a different on-timing, and/or the second current source at the other of the two edges from the gate of the switching element. A configuration (a third configuration) in which the value of the drawn current is variable, the second current source includes a plurality of second sub-current sources, and the plurality of second sub-current sources have different on-timings. may

Further, in the switching control circuit having the third configuration, a plurality of delay circuits may be provided, and the degree of difference in the ON timing may be determined by the outputs of the plurality of delay circuits (fourth configuration). .

In the switching control circuit having the fourth configuration, each of the plurality of delay circuits may be configured to receive the pulse signal or an inverted signal of the pulse signal as an input signal (fifth configuration).

In the switching control circuit having the fourth configuration, at least two of the plurality of delay circuits may be connected in series (sixth configuration).

Further, in the switching control circuit having any one of the first to sixth configurations, at both edges of each pulse of the signal generated according to the ON/OFF of the switching element, the switching element at one edge A configuration (seventh configuration) in which the sum of the rising slew rate time of the signal supplied to the gate and the falling slew rate time of the signal supplied to the gate of the switching element at the other edge is substantially constant; There may be.

Further, a communication apparatus according to the present invention has a configuration (eighth configuration) including a switching control circuit having any one of the first to seventh configurations and the switching element.

Further, a switching power supply device according to the present invention has a configuration (ninth configuration) including the switching control circuit having any one of the first to seventh configurations and the switching element.

Further, a vehicle according to the present invention has a configuration (tenth configuration) including at least one of the communication device of the eighth configuration and the switching power supply device of the ninth configuration.

Further, an electronic apparatus according to the present invention has a configuration (eleventh configuration) including at least one of the communication device having the eighth configuration and the switching power supply device having the ninth configuration.

According to the present invention, it is possible to reduce the peak value of EMI noise generated when the switching element is driven. As a result, it is possible to reduce the adverse effects of EMI noise generated when the switching element is driven on surrounding devices.

FIG. 2 is a diagram schematically showing a switching control circuit according to the first embodiment; Time chart showing voltage waveforms of each part of the switching control circuit according to the first embodiment FIG. 4 is a diagram schematically showing EMI noise caused by the rising slew rate of the gate signal supplied to the switching element in the switching control circuit according to the first embodiment; A diagram schematically showing EMI noise caused by the rising slew rate of the control signal that drives the switching element in the switching regulator proposed in Patent Document 1. The figure which showed schematically the switching control circuit which concerns on 2nd Embodiment. The figure which showed roughly the switching control circuit which concerns on 3rd Embodiment. The figure which showed roughly the switching control circuit which concerns on 4th Embodiment. The figure which showed roughly the other switching control circuit which concerns on 4th Embodiment. The figure which showed roughly the other switching control circuit which concerns on 4th Embodiment. FIG. 4 is a diagram schematically showing a connection state between a communication IC and another device; Schematic diagram of a switching power supply Diagram showing the appearance of the vehicle Diagram showing appearance of mobile device FIG. 4 schematically shows a modification of the switching control circuit;

<First Embodiment>
FIG. 1 is a schematic diagram of a switching control circuit according to the first embodiment. The switching control circuit according to this embodiment includes inverters N1 and N2, delay circuits DEL11, DEL12, DEL21, and DEL22, current sources 1 and 2, and switches Q1 and Q2. Current source 1 is a parallel circuit of constant current sources CS10-CS12, and current source 2 is a parallel circuit of constant current sources CS20-CS22. The switching control circuit according to the present embodiment drives the switching element Q3 to control ON/OFF of the switching element Q3. In this embodiment, a P-channel MOS [metal oxide semiconductor] field effect transistor is used as the switch Q1, an N-channel MOS field effect transistor is used as the switch Q2, and an N-channel MOS field effect transistor is used as the switching element Q3. A field effect transistor is used.

Terminal T1 is connected to the input end of inverter N1. The output terminal of the inverter N1 is connected to each input terminal of the delay circuit DEL11, the delay circuit DEL21, and the inverter N2. The output of inverter N2 is connected to the gates of switches Q1 and Q2 and to the inputs of delay circuits DEL21 and DEL22.

The source of switch Q1 is connected to the low potential end of current source 1; A constant voltage Vcc is applied to the high potential end of the current source 1 . The drains of switches Q1 and Q2 are connected to the gate of switching element Q3. The source of switch Q2 is connected to the high potential end of current source 2; The low potential end of the current source 2 is connected to the ground potential application end.

A circuit formed by diodes D1 and D2, resistor R1 and switching element Q3 produces an output voltage Vout. A constant voltage Vcc is applied to the anode of the diode D1. The cathode of diode D1 is connected to the anode of diode D2 through resistor R1. The cathode of diode D1 is connected to the drain of switching element Q3. The source of the switching element Q3 is connected to the ground potential application end. A terminal T2 is connected to a connection node between the resistor R1 and the diode D2.

A pulse signal D is supplied to the terminal T1 of the switching control circuit according to the present embodiment having the above configuration. The inverter N1 supplies the inverted signal XD of the pulse signal D to each input terminal of the delay circuit DEL11, the delay circuit DEL21, and the inverter N2. The inverter N2 supplies the pulse signal D to each input terminal of the delay circuits DEL21 and DEL22.

The delay circuit DEL11 generates a delayed signal by delaying the inverted signal XD of the pulse signal D by a predetermined time Δ1. A delay signal output from the delay circuit DEL11 is supplied to the constant current source CS11. The delay circuit DEL12 generates a delayed signal by delaying the inverted signal XD of the pulse signal D by a predetermined time Δ2. A delay signal output from the delay circuit DEL12 is supplied to the constant current source CS12. Note that the predetermined time Δ2 is longer than the predetermined time Δ1.

The delay circuit DEL21 generates a delayed signal by delaying the pulse signal D by a predetermined time Δ3. A delay signal output from the delay circuit DEL21 is supplied to the constant current source CS21. The delay circuit DEL22 generates a delayed signal by delaying the pulse signal D by a predetermined time Δ4. A delay signal output from the delay circuit DEL22 is supplied to the constant current source CS22. Note that the predetermined time Δ4 is longer than the predetermined time Δ3.

Inverter N2 also provides pulse signal D to the gates of switches Q1 and Q2. Thereby, the switches Q1 and Q2 are complementarily turned on/off according to the pulse signal D. FIG. Although the ON/OFF states of the switches Q1 and Q2 are completely reversed in this embodiment, a simultaneous OFF period (dead time) may be provided. That is, the term "complementary" used in this specification means that the ON/OFF states of the switches Q1 and Q2 are completely reversed, and that a simultaneous OFF period (dead time) is provided. Including cases where

When switch Q1 is on, current source 1 supplies current to the gate of switching element Q3. Constant current source CS11 in current source 1 is enabled when the delay signal output from delay circuit DEL11 is at high level, and is disabled when the delay signal output from delay circuit DEL11 is at low level. becomes. The constant current source CS12 in the current source 1 is enabled when the delay signal output from the delay circuit DEL12 is at high level, and disabled when the delay signal output from the delay circuit DEL12 is at low level. Sable state. Therefore, the ON timings of the constant current sources CS10, CS11, and C12 are different, and the degree of difference is determined by each delay signal output from the delay circuits DEL11 and DEL12. As a result, the value of the current supplied by the current source 1 to the gate of the switching element Q3 when the switch Q1 is on varies at each rising edge of the output voltage Vout.

More specifically, as shown in FIG. 2, the value of current supplied by current source 1 to the gate of switching element Q3 when switch Q1 is on is pulsed at each falling edge of output voltage Vout. A first period T1 from the falling edge of D until a predetermined time Δ1 elapses; a second period T2 from the end of the first period until a predetermined time (Δ2−Δ1) elapses; Each of the three periods T3 is different. The value of the current supplied to the gate of the switching element Q3 during the second period T2 is greater than the value of the current supplied to the gate of the switching element Q3 during the first period T1, and the current supplied to the gate of the switching element Q3 during the third period T3. The value of the current supplied is greater than the value of the current supplied to the gate of the switching element Q3 during the second period T2.

On the other hand, when the switch Q2 is on, the current source 2 draws current from the gate of the switching element Q3. The constant current source CS21 in the current source 2 is enabled when the delay signal output from the delay circuit DEL21 is at high level, and is disabled when the delay signal output from the delay circuit DEL21 is at low level. becomes. The constant current source CS22 in the current source 1 is enabled when the delay signal output from the delay circuit DEL22 is at high level, and disabled when the delay signal output from the delay circuit DEL22 is at low level. Sable state. Therefore, the ON timings of the constant current sources CS20, CS21, and C22 are different, and the degree of difference is determined by each delay signal output from the delay circuits DEL21 and DEL22. As a result, the value of the current drawn from the gate of the switching element Q3 by the current source 2 when the switch Q2 is on varies at each rising edge of the output voltage Vout.

More specifically, as shown in FIG. 2, the value of the current drawn from the gate of switching element Q3 by current source 1 when switch Q2 is on is equal to that of pulse signal D at each rising edge of output voltage Vout. A fourth period T4 from the rising edge until a predetermined time Δ3 elapses, a fifth period T5 from the end of the fourth period until a predetermined time (Δ4−Δ3) elapses, and a sixth period after the end of the fifth period T5. Each T6 is different. The value of the current drawn from the gate of the switching element Q3 during the fifth period T5 is greater than the value of the current drawn from the gate of the switching element Q3 during the fourth period T4, and the current drawn from the gate of the switching element Q3 during the sixth period T6. The value of the current is greater than the value of the current drawn from the gate of the switching element Q3 during the fifth period T5.

The output voltage Vo, which is generated according to the on/off state of the switching element Q3 and is output from the terminal T2, becomes low level (substantially the same level as the ground potential) when the switching element Q3 is on, and the switching element Q3 is off. , it becomes high level (substantially the same level as the constant voltage Vcc).

The rising slew rate of the gate signal supplied to the switching element Q3 depends on the drive capability of the current source 1. FIG. Therefore, at each falling edge of the output voltage Vout, there are three rising slew rates of the gate signal supplied to the switching element Q3. As a result, at each falling edge of the output voltage Vout, the frequencies of the EMI noise caused by the rising slew rate of the gate signal supplied to the switching element Q3 can be dispersed into three as shown in FIG. This frequency dispersion can reduce the peak value PK1 of EMI noise. Note that FIG. 3 also shows a peak value PK0, which will be described later, for reference.

On the other hand, if the rising slew rate of the control signal that drives the switching element is fixed as in the switching regulator proposed in Patent Document 1, the rise slew rate of the control signal that drives the switching element becomes the cause. The frequency of EMI noise is fixed to one as shown in FIG. As a result, the peak value PK0 of EMI noise caused by the fixed rising slew rate of the control signal for driving the switching element increases.

The EMI noise caused by the falling slew rate of the gate signal supplied to the switching element Q3 is also affected by frequency dispersion in the same manner as the EMI noise caused by the rising slew rate of the gate signal supplied to the switching element Q3. The peak value of EMI noise can be reduced.

As described above, the switching control circuit according to the present embodiment can reduce the peak value of EMI noise generated when the switching element Q3 is driven. As a result, it is possible to reduce the adverse effects of EMI noise generated when the switching element Q3 is driven on surrounding devices.

Further, according to the switching control circuit according to the present embodiment, since the current source 1, the switch Q1, the switch Q2, and the current source 2 are connected in series, it is possible to prevent the switches Q1 and Q2 from being turned on at the same time. By doing so, it is possible to prevent a through current from flowing. That is, the control for preventing the through current from flowing is simple. Even if a through current flows, the current source 1 or 2 limits the through current, so the IC (the IC including the switching control circuit according to the present embodiment) is not destroyed. .

In contrast, the switching regulator proposed in Patent Document 1 has a configuration in which two upper switches are connected in parallel and two lower switches are connected in parallel. The flow of through current cannot be prevented unless at least one of the lower switches and the two lower switches are prevented from being turned on at the same time. That is, the control for preventing the through current from flowing is complicated.

Further, according to the switching control circuit according to the present embodiment, the value of the current supplied by the current source 1 to the gate of the switching element Q3 when the switch Q1 is on, and the current source when the switch Q2 is on. 2 changes during one edge of the output voltage Vout. As a result, even in terms of time, the frequency of EMI noise caused by the rising slew rate of the gate signal supplied to the switching element Q3 and the falling slew rate of the gate signal supplied to the switching element Q3 cause The frequency of the EMI noise is finely distributed (within one edge of the output voltage Vout). Therefore, it is possible to prevent EMI noise from concentrating on a specific frequency even in terms of time.

Note that the integrated value of the current supplied to the gate of the switching element Q3 at the falling edge of the output voltage Vout (current integrated value in the first to third periods T1 to T3 shown in FIG. 2) and the rising edge of the output voltage Vout It is desirable that the sum of the integrated value of the current supplied to the gate of the switching element Q3 at the edge (current integrated value in the fourth to sixth periods T4 to T6 shown in FIG. 2) is substantially constant. According to such a configuration, it is possible to prevent the on-duty of the output voltage Vout from fluctuating due to the influence of the slew rate of the gate signal supplied to the gate of the switching element Q3. In other words, at both edges of each pulse of the output voltage Vout, the rising slew rate time of the signal supplied to the gate of the switching element Q3 at one edge and the rising slew rate time of the signal supplied to the gate of the switching element Q3 at the other edge Since the sum of the falling slew rate time of the signal is substantially constant, it is possible to suppress the on-duty of the output voltage Vout from fluctuating due to the slew rate of the gate signal supplied to the gate of the switching element Q3. .

<Second embodiment>
FIG. 5 is a schematic diagram of a switching control circuit according to the second embodiment. The switching control circuit according to the present embodiment differs from the switching control circuit according to the first embodiment in that the delay circuit DEL12 receives the delay signal output from the delay circuit DEL11 instead of the inverted signal XD of the pulse signal D, and delays The difference is that the circuit DEL22 receives not the pulse signal D but the delay signal output from the delay circuit DEL21. That is, in this embodiment, the delay circuit DEL11 and the delay circuit DEL12 are connected in series, and the delay circuit DEL21 and the delay circuit DEL22 are connected in series.

According to the switching control circuit according to the present embodiment, similarly to the switching control circuit according to the first embodiment, it is possible to reduce the peak value of EMI noise generated when the switching element Q3 is driven. As a result, it is possible to reduce the adverse effects of EMI noise generated when the switching element Q3 is driven on surrounding devices.

Further, in the present embodiment, unlike the first embodiment, the delay time of the delay circuit DEL11 and the delay time of the delay circuit DEL12 can be made the same, and the delay time of the delay circuit DEL21 and the delay time of the delay circuit DEL22 can be made the same. can be In the present embodiment, similarly to the first embodiment, the delay time of the delay circuit DEL11 and the delay time of the delay circuit DEL12 are set to be different times, and the delay time of the delay circuit DEL21 and the delay time of the delay circuit DEL22 are different from each other. Different times may be used.

<Third Embodiment>
FIG. 6 is a schematic diagram of a switching control circuit according to the third embodiment. The switching control circuit according to the present embodiment differs from the switching control circuit according to the first embodiment in that the delay circuits DEL11 and DEL12 input the pulse signal D instead of the inverted signal XD of the pulse signal D, and the constant current source CS11 A switch Q11 (P-channel MOS field effect transistor Q11) is connected in series, a switch Q12 (P-channel MOS field effect transistor Q12) is connected in series to a constant current source CS12, and a delay signal output from a delay circuit DEL11 is supplied to the gate of the switch Q11 instead of the constant current source CS11, and the delay signal output from the delay circuit DEL12 is supplied to the gate of the switch Q12 instead of the constant current source CS12.

According to the switching control circuit according to the present embodiment, similarly to the switching control circuit according to the first embodiment, it is possible to reduce the peak value of EMI noise generated when the switching element Q3 is driven. As a result, it is possible to reduce the adverse effects of EMI noise generated when the switching element Q3 is driven on surrounding devices.

<Fourth Embodiment>
7A to 7C are diagrams schematically showing switching control circuits according to a fourth embodiment. The switching control circuit according to this embodiment differs from the switching control circuit according to the first embodiment in that it does not use a constant current source.

In the configuration shown in FIG. 7A, the delay circuits DEL11 and DEL12 receive the pulse signal D instead of the inverted signal XD of the pulse signal D, the resistor R10 is used instead of the constant current source CS10, and the resistor R10 is used instead of the constant current source CS11. A switch Q11 (P-channel MOS field effect transistor) is turned on when the delay signal output from R11 and the delay circuit DEL11 is at a low level and turned off when the delay signal output from the delay circuit DEL11 is at a high level. Q11), instead of the constant current source CS12, it turns on when the delay signal output from the resistor R12 and the delay circuit DEL12 is at a low level, and the delay signal output from the delay circuit DEL12 is at a high level. A series circuit with a switch Q12 (P-channel MOS field effect transistor Q12) that is turned off when it is at level is used. Furthermore, in the configuration shown in FIG. 7A, a resistor R20 is used instead of the constant current source CS20, and instead of the constant current source CS21, the resistor R21 and the delay circuit DEL21 are turned on when the delay signal output from the delay circuit DEL21 is at a high level. A series circuit with a switch Q21 (N-channel MOS field effect transistor Q21) that is turned off when the delay signal output from the delay circuit DEL21 is at a low level is used, instead of the constant current source CS22, a resistor R22 and A switch Q22 (N-channel MOS field effect transistor Q22) which is turned on when the delay signal output from the delay circuit DEL22 is at high level and turned off when the delay signal output from the delay circuit DEL22 is at low level. A series circuit with

In the configuration shown in FIG. 7B, the delay circuits DEL11 and DEL12 receive the pulse signal D instead of the inverted signal XD of the pulse signal D, and the constant current sources CS10 to CS12 are replaced by P-channel MOS field effect transistors Q10 to Q12. N-channel MOS field effect transistors Q20 to Q22 are used instead of the constant current sources CS20 to CS22, respectively.

In the configuration shown in FIG. 7C, the delay circuits DEL11 and DEL12 receive the pulse signal D instead of the inverted signal XD of the pulse signal D, and PNP bipolar transistors Q10 to Q12 are used instead of the constant current sources CS10 to CS12. NPN bipolar transistors Q20-Q22 are used in place of current sources CS20-CS22, respectively.

According to the switching control circuit according to the present embodiment, similarly to the switching control circuit according to the first embodiment, it is possible to reduce the peak value of EMI noise generated when the switching element Q3 is driven. As a result, it is possible to reduce the adverse effects of EMI noise generated when the switching element Q3 is driven on surrounding devices. However, in the switching control circuit according to the present embodiment, the current sources 1 and 2 are not composed of constant current sources, so the drive capabilities of the current sources 1 and 2 are likely to fluctuate due to temperature and the like.

Further, the same change as that of the switching control circuit according to the first embodiment to the switching control circuit according to the fourth embodiment can also be made to the switching control circuit according to the second embodiment.

<Application>
Applications of the switching control circuit described above will be described. For example, the entire circuit shown in FIG. 1 may be used as the output stage of the communication IC 10 shown in FIG. The communication IC 10 shown in FIG. 8 functions as a communication device and outputs an output voltage Vout, which is a pulse signal, to another device 12 from the terminal T2 via the bus line 11. FIG. When the communication IC 10 is mounted on a vehicle, the bus line 11 may be, for example, a LIN (Local Interconnect Network) bus line.

Also, for example, the entire circuit shown in FIG. 1 may be used as the output stage of the switching power supply IC 20 shown in FIG. The switching power supply IC 20, inductor L1, output capacitor CO, and voltage dividing resistors Rd1 and Rd2 shown in FIG. 9 function as a step-down switching power supply. The inductor L1 and the output capacitor CO smooth the output voltage Vout output from the terminal T2 of the switching power supply IC20 to generate the voltage Vo. The voltage dividing resistors Rd1 and Rd2 divide the voltage Vo and supply the divided voltage of the voltage Vo to the switching power supply IC20. The switching power supply IC 20 generates a pulse signal D based on the voltage division of the voltage Vo.

FIG. 10 is an external view showing a vehicle X equipped with at least one of the communication IC 10 and the switching power supply IC 20 described above.

FIG. 11 is an external view showing an example of an electronic device (portable terminal (smartphone) Z) in which at least one of the communication IC 10 and the switching power supply IC 20 described above is installed. However, the mobile terminal X is merely an example of an electronic device in which a communication device or a switching power supply device is suitably mounted, and the communication IC 10 and the switching power supply IC 20 described above can be applied to a wide variety of electronic devices required electronic equipment).

<Modification>
The above embodiments should be considered illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above embodiments. It should be understood that all modifications that fall within the meaning and range of equivalents of the claims are included.

For example, multiple embodiments and modifications shown in this specification may be implemented in combination to the extent possible.

Further, for example, in each of the above-described embodiments, two delay circuits for outputting delay signals are provided in the current source 1, and at each falling edge of the output voltage Vout, the rising slew rate of the gate signal supplied to the switching element Q3 is Two delay circuits for outputting delay signals to the current source 2 are provided, and three rising slew rates of the gate signal supplied to the switching element Q3 are provided at each rising edge of the output voltage Vout. However, the present invention is not limited to these examples, m and n are arbitrary natural numbers, and m delay circuits for outputting delay signals to the current source 1 are provided, and at each falling edge of the output voltage Vout, the switching element The rising slew rate of the gate signal supplied to Q3 is (m+1) types, n delay circuits are provided to output the delay signal to the current source 2, and the signal is supplied to the switching element Q3 at each rising edge of the output voltage Vout. The rising slew rate of the gate signal may be (n+1) types. Furthermore, one of m and n may be zero instead of a natural number. For example, if the first embodiment is modified to have n=0, the configuration shown in FIG. 12 is obtained.

1, 2 current source 10 communication IC
20 switching power supply IC
D Pulse signal DEL11, DEL12, DEL21, DEL22 Delay circuit Q1, Q2 Switch Q3 Switching element Y Vehicle Z Portable terminal

Claims (8)

a first current source;
a second current source;
a first switch provided between the first current source and a gate of a switching element;
a second switch provided between the second current source and the gate of the switching element;
a plurality of delay circuits;
with
the first switch and the second switch are complementarily turned on/off in response to a pulse signal;
each of the plurality of delay circuits receives the pulse signal or an inverted signal of the pulse signal as an input signal;
The value of the current supplied to the gate of the switching element by the first current source at one of both edges of each pulse of the signal generated according to the on/off of the switching element is variable , and The current source includes a plurality of first sub-current sources, each of the plurality of first sub-current sources has a different on-timing , and/or
The value of the current drawn from the gate of the switching element by the second current source at the other of the two edges is variable , and the second current source includes a plurality of second sub-current sources, and the plurality of second sub-current sources The on-timing of each sub-current source is different,
A switching control circuit, wherein the degree of difference in the on-timings is determined by the outputs of the plurality of delay circuits. 3. The sum of an integrated value of the current supplied to the gate of the switching element on one of the edges and an integrated value of the current drawn from the gate of the switching element on the other of the edges is substantially constant. 2. The switching control circuit according to 1. 3. The switching control circuit according to claim 1 , wherein at least two of said plurality of delay circuits are connected in series. At both edges of each pulse of the signal generated according to the ON/OFF of the switching element, the rising slew rate time of the signal supplied to the gate of the switching element at one edge and the rising slew rate time of the signal supplied to the gate of the switching element at the other edge 4. The switching control circuit according to any one of claims 1 to 3 , wherein the sum of the signal supplied to the gate of the switching element and the fall slew rate time is substantially constant. A communication device, comprising: the switching control circuit according to any one of claims 1 to 4 ; and the switching element. A switching power supply device comprising: the switching control circuit according to any one of claims 1 to 4 ; and the switching element. A vehicle comprising at least one of the communication device according to claim 5 and the switching power supply device according to claim 6 . An electronic device comprising at least one of the communication device according to claim 5 and the switching power supply device according to claim 6 .

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