KR20150008489A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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KR20150008489A
KR20150008489A KR1020147034961A KR20147034961A KR20150008489A KR 20150008489 A KR20150008489 A KR 20150008489A KR 1020147034961 A KR1020147034961 A KR 1020147034961A KR 20147034961 A KR20147034961 A KR 20147034961A KR 20150008489 A KR20150008489 A KR 20150008489A
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substrate
layer
semiconductor element
resin
fiber
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KR1020147034961A
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Korean (ko)
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하루히코 마에다
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스미토모 베이클리트 컴퍼니 리미티드
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145Organic substrates, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

The semiconductor device 10 includes a substrate 2, a semiconductor element 3 mounted on the substrate 2, and an encapsulating material 4 for encapsulating the semiconductor element 3. The substrate 2 has at least one fiber base layer 211 and a resin layer 212 impregnated in the fiber base layer 211. The volume occupied rate A of the fiber substrate layer 211 in the region from the center plane C located at the center in the thickness direction of the substrate 2 to the semiconductor element mounting surface is smaller than the volume occupation rate A of the substrate 2, Is higher than the volume occupancy rate B of the fiber substrate layer 211 in the region from the center plane C located at the center in the thickness direction of the semiconductor element mounting surface to the surface opposite to the semiconductor element mounting surface.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device and a method of manufacturing the same,

The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device.

Conventionally, a prepreg is used for a substrate on which a semiconductor device is mounted. For example, Patent Document 1 discloses a prepreg impregnated with a resin in a fiber substrate. This prepreg has a structure in which the thickness of a pair of outer resin layers on the outer side of the fiber substrate is different. Patent Document 1 discloses that two prepregs are prepared, the thicker side of the outer resin layer is laminated so as to be in contact with the inner layer circuit, and the outer side copper foil is laminated on both sides thereof to obtain a substrate.

Japanese Patent Application Laid-Open No. 2004-216784

It has been found that there are the following problems when manufacturing a semiconductor device using such a substrate.

The substrate described in Patent Document 1 has a structure in which the fiber base layer is disposed in a vertically symmetrical manner with the center line of the thickness therebetween. Therefore, the substrate is not easily warped as a single substrate. However, when a semiconductor element is mounted on such a substrate and sealed with an encapsulating material, it has been found that the substrate is largely bent into a concave shape (so-called smile type) due to curing shrinkage or the like of the encapsulating material, thereby affecting the productivity of the semiconductor device.

Therefore, there is a demand for development of a semiconductor device having a structure with better manufacturing stability and a manufacturing method thereof.

According to the present invention, there is provided a semiconductor device comprising a substrate, a semiconductor element mounted on the substrate, and an encapsulant for sealing the semiconductor element, the encapsulant being formed on the substrate and made of a thermosetting resin composition, And a resin layer impregnated in the fiber substrate layer, wherein in the substrate, a volume occupied rate A of the fiber substrate layer in a region from a center in the thickness direction of the substrate to a semiconductor element mounting surface is larger than a volume occupied rate A volume occupation rate B of the fiber substrate layer in a region from the center in the thickness direction to the surface opposite to the semiconductor element mounting surface is provided.

In the present invention, the volume occupancy A of the fibrous substrate in the region from the center in the thickness direction of the substrate to the semiconductor element mounting surface is in the range from the center in the thickness direction of the substrate to the surface (back surface) opposite to the semiconductor element mounting surface Is higher than the volume occupancy rate B of the fibrous substrate in the step (a). This makes it difficult for the substrate to shrink in a region from the center of the thickness of the substrate to the semiconductor element mounting surface, and the region from the center to the back surface of the substrate has a structure in which heat shrinks easily. Therefore, in the substrate itself, warpage is likely to occur so that the semiconductor element mounting surface side becomes convex. However, by providing the sealing material on the substrate, the force of the sealing material such as shrinkage or the like acts on the substrate, and the warping of the substrate is eliminated. Therefore, the semiconductor device becomes a semiconductor device having a small amount of warping of the substrate, and the productivity of the semiconductor device is improved.

Therefore, the semiconductor device of the present invention can be said to be a structure having excellent manufacturing stability.

Further, according to the present invention, the above-described method of manufacturing a semiconductor device can be also provided.

That is, according to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: mounting a semiconductor element on a substrate; and sealing the semiconductor element by curing an encapsulating material comprising a thermosetting resin composition, And a volume occupied rate A of the fibrous substrate layer in a region from the center of the substrate in the thickness direction to the semiconductor element mounting surface is smaller than a volume occupied rate A in the thickness direction of the substrate The volume occupied rate B of the fiber substrate layer in the region from the center of the semiconductor element mounting surface to the surface opposite to the semiconductor element mounting surface can be provided.

According to the present invention, a semiconductor device having a structure with excellent manufacturing stability and a manufacturing method of the semiconductor device are provided.

The foregoing and other objects, features and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments thereof with reference to the accompanying drawings.
1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view showing a manufacturing process of a semiconductor device.
3 is a cross-sectional view showing a semiconductor device according to a modified example of the present invention.
4 is a cross-sectional view showing a semiconductor device according to a modified example of the present invention.
5 is a cross-sectional view showing a semiconductor device according to a modified example of the present invention.
6 is a cross-sectional view showing a semiconductor device according to a modified example of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same constituent elements are denoted by the same reference numerals, and the detailed description thereof is appropriately omitted so as not to be duplicated.

Fig. 1 shows a semiconductor device 10 of the present embodiment.

First, the outline of the semiconductor device 10 of the present embodiment will be described.

The semiconductor device 10 includes a substrate 2, a semiconductor element 3 mounted on the substrate 2, and an encapsulating material 4 made of a thermosetting resin composition for encapsulating the semiconductor element 3. The substrate 2 has at least one fiber base layer 211 and a resin layer 212 impregnated in the fiber base layer 211. The volume occupied rate A of the fiber substrate layer 211 in the region from the center plane C located at the center in the thickness direction of the substrate 2 to the semiconductor element mounting surface is smaller than the volume occupation rate A of the substrate 2, Is higher than the volume occupancy rate B of the fiber substrate layer 211 in the region from the center plane C located at the center in the thickness direction of the semiconductor element mounting surface to the surface opposite to the semiconductor element mounting surface.

Here, when the substrate has a solder resist layer that exposes a circuit layer on the semiconductor element mounting surface side, the semiconductor element mounting surface becomes the surface of the solder resist layer.

Similarly, when the substrate has a solder resist layer that exposes a circuit layer on the opposite side to the semiconductor element mounting surface, the surface opposite to the semiconductor element mounting surface becomes the surface of the solder resist layer.

(Configuration of Semiconductor Device)

Next, the semiconductor device 10 of the present embodiment will be described in detail.

(Board)

The substrate 2 includes a core layer 21, a circuit layer 22 provided on the top and bottom surfaces of the core layer 21, and a solder resist layer 23 provided on the core layer 21.

The core layer 21 includes a fiber base layer 211 and an insulating resin layer 212. A through hole 213 is formed in the core layer 21 and a conductor 214 made of a metal such as copper is filled in the through hole 213.

The thickness of the core layer 21 is, for example, 50 占 퐉 or more and 100 占 퐉 or less.

The fiber substrate layer 211 is not particularly limited, but may be a fiberglass substrate such as glass cloth, a polyamide-based fiber such as polybenzoxazole resin fiber, polyamide resin fiber, aromatic polyamide resin fiber or wholly aromatic polyamide resin fiber A synthetic fiber substrate composed mainly of one or more of polyester resin fibers such as resin fiber, polyester resin fiber, aromatic polyester resin fiber and wholly aromatic polyester resin fiber, polyimide resin fiber and fluororesin fiber, Or an organic fiber substrate such as a paper substrate mainly composed of kraft paper, cotton linters, brine of a linter and kraft pulp, and the like. Of these, glass cloth is particularly preferable in terms of strength and water absorption. Further, by using the glass cloth, the thermal expansion coefficient of the resin layer can be further reduced.

Examples of the glass constituting the glass fiber base material include E glass, C glass, A glass, S glass, D glass, NE glass, T glass, UT glass, L glass and H glass. Any one or more of them can be used. Of these, S glass, UT glass or T glass is preferable. As a result, the thermal expansion coefficient of the glass fiber substrate can be reduced, and the coefficient of thermal expansion of the prepreg can be reduced accordingly.

A glass fiber base material used in the present embodiment has a basis weight (1m 2 weight per fiber base) is 4g / m 2 at least 150g / m 2 or less is preferable, more preferably 8g / m 2 at least 110g / m 2 or less, More preferably 12 g / m 2 or more and 60 g / m 2 or less, further preferably 12 g / m 2 or more and 30 g / m 2 or less, still more preferably 12 g / m 2 or more and 24 g / m 2 or less.

When the basis weight is more than the upper limit, the impregnation property of the resin composition in the fiber substrate is lowered, and there is a concern that the strand shape and the insulation reliability are lowered, and it is difficult to form a through hole by laser such as carbon dioxide, UV, There is a concern. When the basis weight is lower than the above lower limit value, the strength of the glass cloth or the prepreg is lowered, which may reduce the handling property and make the preparation of the prepreg difficult, or the effect of reducing the warpage of the substrate.

Among the above glass fiber substrates, glass fiber substrates having a coefficient of linear expansion of 6 ppm / ° C or less are preferable, glass fiber substrates of 4 ppm / ° C or less are more preferable, and glass fiber substrates of 3.5 ppm / . By using the glass fiber base material having such a linear expansion coefficient, warpage of the element mounting board of the present embodiment can be further suppressed.

The Young's modulus of the fiber substrate used in the present embodiment is preferably 60 GPa or more and 100 GPa or less, more preferably 65 GPa or more and 95 GPa or less, further preferably 80 GPa or more and 95 GPa or less, particularly preferably 86 GPa or more 92 GPa or less. By using the glass fiber base material having such Young's modulus, for example, deformation of the wiring board due to reflow heat at the time of semiconductor mounting can be effectively suppressed, so that the connection reliability of the electronic component is further improved.

The glass fiber substrate used in the present embodiment preferably has a dielectric constant at 1 MHz of from 3.5 to 7.0, more preferably from 3.5 to 6.8, and still more preferably from 3.5 to 5.5. By using the glass fiber base material having such a dielectric constant, the dielectric constant of the element mounting board can be further reduced, which is suitable for a semiconductor package using a high-speed signal.

Examples of the glass fiber substrate having the above-mentioned coefficient of linear expansion, Young's modulus and dielectric constant include E glass, S glass, NE glass, T glass, UN glass, UT glass, L glass and HP glass.

The thickness of the fiber substrate layer is not particularly limited, but is preferably 5 占 퐉 or more and 100 占 퐉 or less, more preferably 10 占 퐉 or more and 60 占 퐉 or less, and further preferably 12 占 퐉 or more and 35 占 퐉 or less. By using the fibrous base material having such a thickness, the handling property at the time of producing the prepreg is further improved, and the effect of reducing the warpage is remarkable.

When the thickness of the fiber base layer exceeds the upper limit value, the impregnation property of the resin composition in the fiber base material is lowered, and there is a fear that the strand shape and the insulation reliability are lowered. In addition, There is a fear that it becomes difficult to form. When the thickness of the fibrous substrate layer is lower than the lower limit described above, the strength of the fibrous substrate or the prepreg is lowered, and the handling property is lowered, the preparation of the prepreg becomes difficult or the effect of warping of the substrate is lowered have.

In addition, the number of fibers used is not limited to one, and a plurality of thin fiber substrates may be stacked. When a plurality of fiber substrates are stacked, it is preferable that the total thickness satisfies the above range.

The substrate 2 is excellent in low linear expansion coefficient and high elastic modulus by impregnating a fiber-based layer such as a glass fiber substrate with a resin composition, and has a low warpage in a thin multi-layer wiring board and a semiconductor package in which a semiconductor chip is mounted on the multi- Heat resistance and thermal shock resistance can be obtained. Among them, high strength, low absorption, and low thermal expansion can be achieved by impregnating a fiber base layer such as a glass fiber base with a resin composition.

The resin layer 212 is impregnated in the fiber substrate layer 211 and the impregnated region impregnated in the fiber substrate layer 211 and the surface of the fiber substrate layer 211 And a second area covering the back surface of the fibrous substrate layer 211. The second area covers the first area and the second area.

Here, the thickness D1 of the first region is thinner than the thickness D2 of the second region. The fiber base layer 211 of the core layer 21 is located on the surface of the core layer 21 (the side of the substrate on which the semiconductor element is mounted) than the center position in the thickness direction of the core layer 21, . The volume occupancy of the fiber base layer 211 in the region from the center in the thickness direction of the core layer 21 to the surface of the core layer 21 on the semiconductor element mounting surface side of the substrate is smaller than the volume occupancy of the core layer 21 Is higher than the volume occupied rate of the fiber-based layer 211 in the region from the center of the thickness direction to the back surface of the core layer 21 opposite to the surface.

For example, D2 / D1 is preferably 2 or more and 5 or less. By making D2 / D1 equal to or larger than 2, it is possible to suppress the occurrence of concave warpage (smoothing warpage) as viewed from the mounting surface of the semiconductor element of the substrate 2.

On the other hand, by setting D2 / D1 to 5 or less, occurrence of excessive bending (creeping) of the substrate 2 can be suppressed.

For example, D1 is 2 to 10 mu m and D2 is 5 to 30 mu m.

Here, the resin composition constituting the resin layer 212 is not particularly limited, but it is preferable that it has a low linear expansion coefficient and a high elastic modulus, and is excellent in the reliability of thermal shock resistance.

The glass transition temperature of the resin composition is preferably 160 占 폚 or more and 270 占 폚 or less, and more preferably 180 占 폚 or more and 240 占 폚 or less. Use of the resin composition having such a glass transition temperature can provide an effect of further improving the heat resistance of the lead-free solder reflow.

The resin composition constituting the resin layer 212 preferably includes a thermosetting resin.

Specific examples of the thermosetting resin include novolak type phenol resins such as phenol novolac resin, cresol novolak resin and bisphenol A novolac resin, unmodified resol phenol resin, tung oil, flaxseed oil, A phenol resin such as a resol-type phenol resin which is denatured and oil-resolved phenol resin, a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol S type epoxy resin, a bisphenol E type epoxy resin, a bisphenol M type epoxy Bisphenol type epoxy resins such as bisphenol P type epoxy resin and bisphenol Z type epoxy resin, novolak type epoxy resins such as phenol novolak type epoxy resin and cresol novolak type epoxy resin, biphenyl type epoxy resin, biphenyl type epoxy resin, A quarternary epoxy resin, an arylalkylene type epoxy resin, a naphthalene type epoxy resin, an anthracene type epoxy resin, a phenoxy type epoxy resin, a dicyclopentadiene type Epoxy resins such as epoxy resin, norbornene epoxy resin, adamantane epoxy resin and fluorene epoxy resin, urea (urea) resin, resin having triazine ring such as melamine resin, unsaturated polyester resin, bismaleimide resin , Polyurethane resin, diaryl phthalate resin, silicone resin, resin having benzoxazine ring, cyanate resin, polyimide resin, polyamideimide resin and benzocyclobutene resin.

One of these may be used alone, or two or more types having different weight average molecular weights may be used in combination, or one or more types of these prepolymers may be used in combination.

Among these, a cyanate resin (including a prepolymer of a cyanate resin) is particularly preferable. By using a cyanate resin, the thermal expansion coefficient of the resin layer can be reduced. The cyanate resin is also excellent in electrical characteristics (low dielectric constant, low dielectric loss tangent) and mechanical strength.

The cyanate resin can be prepared, for example, by reacting a halogenated cyanide compound with a phenol, or by prepolymerizing by a method such as heating if necessary. Specific examples thereof include bisphenol-type cyanate resins such as novolak-type cyanate resins, bisphenol A-type cyanate resins, bisphenol E-type cyanate resins and tetramethyl bisphenol F-type cyanate resins, naphthol- Cyanate resin, dicyclopentadiene type cyanate resin and biphenyl alkyl type cyanate resin obtained by reaction with cyan. Any one or more of them may be used. Among them, a novolak type cyanate resin is preferable. The use of a novolac cyanate resin increases crosslink density and improves heat resistance. Therefore, the flame retardancy of the resin composition and the like can be improved.

For this reason, the novolac cyanate resin forms a triazine ring after the curing reaction. Further, the novolac cyanate resin is considered to have a high proportion of benzene rings due to its structure and is likely to be carbonized. Further, even when the core layer 21 has a thickness of 0.6 mm or less, the substrate including the resin layer formed by curing the novolac cyanate resin has excellent rigidity. Particularly, since such a substrate is excellent in rigidity at the time of heating, the reliability at the time of semiconductor element mounting is also excellent.

As the novolac cyanate resin, for example, those represented by the following general formula (I) can be used.

Figure pct00001

The average repeating unit n of the novolak type cyanate resin represented by the general formula (I) is an arbitrary integer and is not particularly limited, but is preferably 1 or more and 10 or less, particularly preferably 2 or more and 7 or less. When the average recurring unit n is too small, the novolak-type cyanate resin may deteriorate in heat resistance and may be volatilized during heating. If the average repeating unit n is too large, the melt viscosity becomes too high and the moldability of the resin layer may be lowered.

As the cyanate resin, a naphthol-type cyanate resin represented by the following general formula (II) is suitably used. The naphthol-cyanate resin represented by the following general formula (II) is obtained by reacting naphthols such as? -Naphthol or? -Naphthol with p-xylylene glycol,?,? -Dimethoxy-p- Di (2-hydroxy-2-propyl) benzene and the like, and a cyanic acid. It is more preferable that n in the general formula (II) is 10 or less. When n is 10 or less, there is a tendency that the resin viscosity is not high and the impregnation property with respect to the substrate is good and the performance as an element mounting board is not deteriorated. Further, intramolecular polymerization hardly occurs at the time of synthesis, and the liquidity at the time of washing is improved, so that a decrease in the yield tends to be prevented.

Figure pct00002

(Wherein R represents a hydrogen atom or a methyl group, and n represents an integer of 1 or more).

As the cyanate resin, a dicyclopentadiene-type cyanate resin represented by the following general formula (III) can also be suitably used. In the dicyclopentadiene-type cyanate resin represented by the following general formula (III), n in the following general formula (III) is more preferably 0 or more and 8 or less. When n is 8 or less, the resin viscosity is not high and the impregnation property to the substrate is good, so that the performance as the substrate on which the device is mounted can be prevented from deteriorating. Further, by using dicyclopentadiene type cyanate resin, it is excellent in low hygroscopicity and chemical resistance.

Figure pct00003

(n represents an integer of 0 or more and 8 or less.)

The weight average molecular weight (Mw) of the cyanate resin is not particularly limited, but is preferably, for example, Mw 500 to 4,500, more preferably 600 to 3,000. If the Mw is too small, adhesion may occur when the resin layer is produced, and when the resin layers are brought into contact with each other, they may adhere to each other, or resin may be transferred. On the other hand, if the Mw is too large, the reaction may become too fast, resulting in poor molding or poor interlayer peel strength.

The Mw of the cyanate resin and the like can be measured by, for example, GPC (gel permeation chromatography, standard material: in terms of polystyrene).

The cyanate resin may be used alone, or two or more types having different Mw may be used together, or one or more types of cyanate resins may be used in combination with these prepolymers.

The content of the thermosetting resin contained in the resin composition may be suitably adjusted according to the purpose and is not particularly limited, but is preferably 10% by weight or more and 80% by weight or less, more preferably 20% by weight or more and 50% . If the content of the thermosetting resin is too small, the handling property of the prepreg may deteriorate or it may become difficult to form the resin layer. If the content is too large, the strength and flame retardancy of the resin layer may decrease and the coefficient of linear expansion of the resin layer may increase The effect of reducing the warping of the substrate (substrate 21) on which the element is mounted may be lowered.

The resin composition preferably contains an inorganic filler. Thus, even when the substrate on which the element is mounted is made thinner, it is possible to give more excellent strength. In addition, it is possible to further improve the thermal expansion of the element-mounted substrate.

Examples of the inorganic filler include silicates such as talc, calcined clay, unbaked clay, mica and glass, oxides such as titanium oxide, alumina, boehmite, silica and fused silica, calcium carbonate, magnesium carbonate, hydrotalcite, Hydroxides such as carbonates of aluminum hydroxide, magnesium hydroxide and calcium hydroxide, sulfates or sulfites of barium sulfate, calcium sulfate and calcium sulfite, zinc borate, barium metaborate, aluminum borate, calcium borate and sodium borate Nitrides such as boronate, aluminum nitride, boron nitride, silicon nitride and carbon nitride, and titanate salts such as strontium titanate and barium titanate.

As the inorganic filler, one of them may be used alone, or two or more of them may be used in combination. Of these, silica is particularly preferable, and fused silica (particularly spherical fused silica) is preferable because of its excellent low-temperature expansion property. The shape of the fused silica includes crushed and spherical. In order to ensure the impregnation property with respect to the fiber substrate, it is possible to employ a method suitable for the purpose, for example, by using spherical silica to lower the melt viscosity of the resin composition.

The average particle diameter of the inorganic filler is not particularly limited, but is preferably 0.01 탆 or more and 5.0 탆 or less, more preferably 0.01 탆 or more and 2.0 탆 or less, and particularly preferably 0.1 탆 or more and 2.0 탆 or less. When the particle size of the inorganic filler is too small, the viscosity of the varnish becomes high, which may affect the workability in the production of the resin layer. If the particle size of the inorganic filler is too large, the phenomenon such as settling of the inorganic filler may occur in the varnish.

The average particle diameter can be measured by, for example, a particle size distribution meter (LA-500, manufactured by HORIBA).

The inorganic filler is not particularly limited, but an inorganic filler having an average particle diameter of monodispersed may be used, or an inorganic filler having a polydispersity of an average particle diameter may be used. The inorganic fillers having an average particle diameter of monodisperse and / or polydispersity may be used alone or in combination of two or more.

The inorganic filler is preferably spherical silica having an average particle diameter of 5.0 m or less (particularly spherical fused silica), particularly spherical fused silica having an average particle diameter of 0.01 m or more and 2.0 m or less. Thus, the filling property of the inorganic filler can be further improved.

The lower limit of the content of the inorganic filler is not particularly limited, but is preferably 20% by weight or more, more preferably 30% by weight or more, and even more preferably 50% by weight or more based on the whole resin composition. The upper limit value of the content of the inorganic filler is not particularly limited, but is preferably 80% by weight or less, more preferably 75% by weight or less, based on the whole resin composition. When the content is within the above range, it is possible to achieve particularly low thermal expansion and low absorption. In particular, it is possible to reduce warpage of the substrate on which elements are mounted.

The resin composition used in the present embodiment may also be blended with a rubber component. For example, rubber particles can be used. Preferable examples of the rubber particles include core-shell type rubber particles, crosslinked acrylonitrile-butadiene rubber particles, crosslinked styrene-butadiene rubber particles, acrylic rubber particles, silicone particles and the like.

The core-shell-type rubber particles are rubber particles having a core layer and a shell layer, for example, a two-layer structure in which the shell layer of the outer layer is composed of a glassy polymer and the core layer of the inner layer is a rubbery polymer, Layer structure in which the intermediate layer is composed of a rubber-like polymer and the core layer is composed of a glass-like polymer, and the like. The glassy polymer layer is composed of, for example, a polymer of methyl methacrylate, and the rubbery polymer layer is composed of, for example, a butyl acrylate polymer (butyl rubber). Specific examples of the core-shell-type rubber particles include STAPHILLOID AC3832, AC3816N (trade name, manufactured by Gansu Chemical Industry Co., Ltd.) and Metablen KW-4426 (trade name, manufactured by Mitsubishi Rayon Co., Ltd.). Specific examples of the crosslinked acrylonitrile butadiene rubber (NBR) particles include XER-91 (average particle size 0.5 mu m, manufactured by JSR Corporation).

Specific examples of the crosslinked styrene-butadiene rubber (SBR) particles include XSK-500 (average particle diameter 0.5 탆, manufactured by JSR Corporation). Specific examples of the acrylic rubber particles include Metablen W300A (average particle diameter 0.1 mu m) and W450A (average particle diameter 0.2 mu m) (manufactured by Mitsubishi Rayon Co., Ltd.).

The silicone particles are not particularly limited as long as they are rubber elastic fine particles formed of an organopolysiloxane. For example, fine particles made of a silicone rubber (organopolysiloxane crosslinked elastomer) itself and a core portion made of silicon of a two- And core shell structure particles coated with silicon as a main component. As silicone rubber fine particles, commercial products such as KMP-605, KMP-600, KMP-597, KMP-594 (manufactured by Shinetsu Kagaku), Trefil E-500 and Trefil E-600 (manufactured by Toray Dow Corning) Can be used.

The content of the rubber particles is not particularly limited, but is preferably 20% by weight or more and 80% by weight or less, particularly preferably 30% by weight or more and 75% by weight or less based on the total amount of the inorganic fillers. If the content is within the range, low absorption can be achieved.

An epoxy resin (substantially not containing a halogen atom) may be used in addition to a cyanate resin (particularly, a novolak type cyanate resin, a naphthol type cyanate resin, a dicyclopentadiene type cyanate resin) as a thermosetting resin . Examples of the epoxy resin include epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol M type epoxy resin, bisphenol P type epoxy resin and bisphenol Z type epoxy resin Novolak type epoxy resins such as bisphenol type epoxy resin, phenol novolak type epoxy resin and cresol novolak type epoxy resin, aryl alkylene type epoxy resins such as biphenyl type epoxy resin, xylene type epoxy resin and biphenyl aralkyl type epoxy resin , Naphthalene type epoxy resin, non-naphthyl type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin, dicyclopentadiene type epoxy resin, norbornene type epoxy resin, adamantane type epoxy resin, fluorene type epoxy resin and the like .

As the epoxy resin, one type of epoxy resin may be used alone, or two or more types having different weight average molecular weights may be used in combination, or one type or two or more types thereof may be used in combination with these prepolymers.

Of these epoxy resins, aryl alkylene type epoxy resins are particularly preferable. This makes it possible to further improve heat resistance and flame retardancy of the moisture absorption solder.

An arylalkylene type epoxy resin means an epoxy resin having at least one arylalkylene group in the repeating unit. For example, xylene type epoxy resin, biphenyl dimethylene type epoxy resin and the like. Among them, a biphenyl dimethylene type epoxy resin is preferable. The biphenyl dimethylene type epoxy resin can be represented, for example, by the following general formula (IV).

Figure pct00004

The average repeating unit n of the biphenyl dimethylene type epoxy resin represented by the general formula (IV) is an arbitrary integer, and is not particularly limited, but is preferably 1 or more and 10 or less, particularly preferably 2 or more and 5 or less. If the average repeating unit n is too small, the biphenyl dimethylene type epoxy resin tends to crystallize, and the solubility in a general-purpose solvent is relatively lowered, which makes handling difficult. In addition, when the average repeating unit n is too large, the flowability of the resin is lowered, which may cause defective molding or the like.

As the other epoxy resins, novolak type epoxy resins having condensed ring aromatic hydrocarbon structures are preferable. As a result, the heat resistance and the low thermal expansion performance can be further improved.

The novolak type epoxy resin having a condensed ring aromatic hydrocarbon structure may be selected from the group consisting of naphthalene, anthracene, phenanthrene, tetracene, chrysene, pyrene, triphenylene and tetraphen and other condensed ring aromatic hydrocarbon structures Is a novolak type epoxy resin. The novolak type epoxy resin having a condensed ring aromatic hydrocarbon structure is excellent in low thermal expansion because a plurality of aromatic rings can be regularly arranged. In addition, since the glass transition temperature is high, the heat resistance is excellent. In addition, since the repeating structure has a large molecular weight, it is excellent in flame retardancy as compared with conventional novolak type epoxy resins, and can be improved in combination with a cyanate resin to improve weakness of weakness of cyanate resin. Therefore, when used in combination with a cyanate resin, the glass transition temperature becomes higher, and therefore, the reliability in mounting reliability for lead-free is excellent.

The novolak type epoxy resin having a condensed ring aromatic hydrocarbon structure is obtained by epoxidizing a novolak type phenolic resin synthesized from a phenol compound, a formaldehyde compound and a condensed ring aromatic hydrocarbon compound.

Examples of the phenol compound include, but are not limited to, cresols such as phenol, o-cresol, m-cresol and p-cresol, 2,3- Xylenol such as 2,6-xylenol, 3,4-xylenol and 3,5-xylenol, trimethylphenols such as 2,3,5-trimethylphenol, o-ethylphenol, methylphenol, p-ethylphenol and the like, alkylphenols such as isopropylphenol, butylphenol and t-butylphenol, o-phenylphenol, m-phenylphenol, p-phenylphenol, catechol, Naphthalene diols such as 5-dihydroxynaphthalene, 1,6-dihydroxynaphthalene and 2,7-dihydroxynaphthalene, resorcinol such as resorcin, catechol, hydroquinone, pyrogallol, And alkylpolyphenols such as polyhydric phenols, alkyl resorcin, alkyl catechol and alkyl hydroquinone. Among them, phenol is preferable in terms of cost and effect on the decomposition reaction.

The aldehyde compound is not particularly limited and includes, for example, formaldehyde, paraformaldehyde, trioxane, acetaldehyde, propionaldehyde, polyoxymethylene, chloral, hexamethylenetetramine, furfural, glyoxal, n -Butyl aldehyde, caproaldehyde, allyl aldehyde, benzaldehyde, crotonaldehyde, acrolein, tetraoxymethylene, phenylacetaldehyde, o-toraldehyde, salicylaldehyde, dihydroxybenzaldehyde, trihydroxybenzaldehyde, 3-methoxyaldehyde paraformaldehyde, and the like.

Examples of the condensed ring aromatic hydrocarbon compound include, but are not limited to, naphthalene derivatives such as methoxynaphthalene and butoxynaphthalene, anthracene derivatives such as methoxyanthracene, phenanthrene derivatives such as methoxyphenanthrene, and other tetracene derivatives, Phenylene derivatives, derivatives of triphenylene and tetraphene, and the like.

The novolak type epoxy resin having a condensed ring aromatic hydrocarbon structure is not particularly limited, and examples thereof include methoxynaphthalene-modified orthocresol novolac epoxy, butoxynaphthalene-modified meta (para) cresol novolac epoxy and methoxynaphthalene- Epoxy, and the like. Among them, a novolak type epoxy resin having a condensed ring aromatic hydrocarbon structure represented by the following formula (V) is preferable.

Figure pct00005

(Wherein Ar is a condensed ring aromatic hydrocarbon group and R may be the same or different and is a hydrogen atom, a hydrocarbon group having 1 to 10 carbon atoms or an aryl group such as a halogen atom, a phenyl group, a benzyl group, or a glycidyl ether And n, p and q are integers of 1 or more, and the values of p and q may be the same or different for each repeating unit.)

(In the formula (V), Ar is a structure represented by (Ar1) to (Ar4) in the formula (VI), R in the formula (VI) may be the same or different, and is preferably a hydrogen atom, a hydrocarbon having 1 to 10 carbon atoms Group or an organic group containing an aryl group such as a halogen atom, a phenyl group or a benzyl group, and a glycidyl ether.

As the other epoxy resins, naphthol type epoxy resins are preferable. As a result, the heat resistance and the low thermal expansion performance can be further improved. Examples of the naphthol type epoxy resin include the following formula (VII-1), the following formula (VII-2) for the naphthalene diol type epoxy resin and the following formula (VII-3) for the bifunctional to tetrafunctional epoxy naphthalene resin: (VII-4) (VII-5), and the naphthylene ether type epoxy resin can be represented by the following general formula (VII-6). Of these, tetrafunctional epoxy-type naphthalene resins and naphthylene ether-type epoxy resins are particularly preferred from the viewpoints of flame retardance, heat resistance, inherent shear temperature and low thermal expansion.

Figure pct00007

(n represents an average number of 1 or more and 6 or less, and R represents a glycidyl group or a hydrocarbon group having 1 to 10 carbon atoms.)

Figure pct00008

Figure pct00009

Figure pct00010

(Wherein R 1 represents a hydrogen atom or a methyl group, each R 2 independently represents a hydrogen atom, an alkyl group having 1 to 4 carbon atoms or an aralkyl group or a naphthalene group or a glycidyl ether group-containing naphthalene group, o and m is an integer of 0 to 2, and either o or m is 1 or more.

The content of the epoxy resin is not particularly limited, but is preferably 1% by weight or more and 55% by weight or less, particularly preferably 2% by weight or more and 40% by weight or less based on the entire resin composition. If the content of the epoxy resin is too small, the reactivity of the cyanate resin may be lowered or the moisture resistance of the obtained product may be lowered. If the content is too large, the heat resistance may be lowered.

The weight average molecular weight (Mw) of the epoxy resin is not particularly limited, but is preferably 500 to 20,000, more preferably 800 to 15,000. If the Mw is too small, the resin layer may become sticky. If the Mw is too large, the impregnation property with respect to the fiber substrate may decrease during production of the resin layer, so that a uniform product may not be obtained. The Mw of the epoxy resin can be measured by GPC, for example.

Examples of the thermosetting resin include cyanate resins (especially novolak type cyanate resins, naphthol type cyanate resins, dicyclopentadiene type cyanate resins), epoxy resins (aryl alkylene type epoxy resins, especially biphenyl dimethylene type epoxy resins, A novolak type epoxy resin having a condensed ring aromatic hydrocarbon structure, or a naphthol type epoxy resin), it is preferable to further use a phenol resin. Examples of the phenol resin include novolak type phenol resins, resol type phenol resins, aryl alkylene type phenol resins and the like. As the phenol resin, one kind may be used alone, or two or more kinds having different weight average molecular weights may be used together, or one kind or two or more kinds thereof may be used in combination with these prepolymers. Of these, an arylalkylene type phenol resin is particularly preferable. This makes it possible to further improve the heat resistance of the moisture absorption solder.

Examples of the arylalkylene type phenol resin include xylylene type phenol resins and biphenyl dimethylene type phenol resins. The biphenyl dimethylene type phenol resin can be represented, for example, by the following general formula (VIII).

Figure pct00011

The repeating unit n of the biphenyl dimethylene type phenol resin represented by the general formula (VIII) is an arbitrary integer and is not particularly limited, but is preferably 1 or more and 12 or less, particularly preferably 2 or more and 8 or less. If the average repeating unit n is too small, the heat resistance may decrease. In addition, if the average repeating unit n is too large, compatibility with other resins is lowered and workability may be lowered.

Mentioned cyanate resins (particularly, novolak type cyanate resins, naphthol type cyanate resins, dicyclopentadiene type cyanate resins), epoxy resins (aryl alkylene type epoxy resins, especially biphenyl dimethylene type epoxy resins, condensed rings A novolak type epoxy resin having an aromatic hydrocarbon structure, a naphthol type epoxy resin) and an arylalkylene type phenol resin, the reactivity can be easily controlled by adjusting the crosslinking density.

The content of the phenolic resin is not particularly limited, but is preferably 1% by weight or more and 55% by weight or less, particularly preferably 5% by weight or more and 40% by weight or less, based on the entire resin composition. If the content of the phenol resin is too small, the heat resistance may be lowered. If the content is too large, the characteristics of the low thermal expansion may be impaired.

The weight average molecular weight (Mw) of the phenol resin is not particularly limited, but is preferably from 400 to 18,000, more preferably from 500 to 15,000. If the Mw is too small, the resin layer may become sticky. If the Mw is too large, the impregnation property with respect to the fiber substrate may decrease during the production of the resin layer, so that a uniform product may not be obtained. The Mw of the phenolic resin can be measured by GPC, for example.

In addition, a cyanate resin (particularly a novolak type cyanate resin, a naphthol type cyanate resin, a dicyclopentadiene type cyanate resin), a phenol resin (aryl alkylene type phenol resin, particularly biphenyl dimethylene type phenol resin) When a substrate (particularly a circuit board) is produced by using a combination of a resin (an arylalkylene type epoxy resin, particularly a biphenyl dimethylene type epoxy resin, a novolak type epoxy resin having a condensed ring aromatic hydrocarbon structure, a naphthol type epoxy resin) , Particularly excellent dimensional stability can be obtained.

The content of the cyanate resin is preferably 10 to 30 wt% with respect to the total amount of the resin composition.

In addition, if necessary, additives such as a coupling agent, a curing accelerator, a curing agent, a thermoplastic resin and an organic filler can be appropriately added to the resin composition. The resin composition used in the present invention can be suitably used in the form of a liquid in which the above components are dissolved and / or dispersed in an organic solvent or the like.

By using the coupling agent, the wettability of the interface between the thermosetting resin and the inorganic filler is improved, and the resin composition can be uniformly fixed to the fiber substrate. Therefore, it is preferable to use a coupling agent, and heat resistance, particularly solder heat resistance after moisture absorption, can be improved.

The coupling agent may be any as long as it is generally used as a coupling agent. Specifically, one or more kinds selected from an epoxy silane coupling agent, a cationic silane coupling agent, an aminosilane coupling agent, a titanate type coupling agent and a silicone oil type coupling agent It is preferable to use a coupling agent. As a result, the wettability with the interface of the inorganic filler can be increased, thereby further improving the heat resistance.

The amount of the coupling agent to be added depends on the specific surface area of the inorganic filler, and is not particularly limited, but is preferably 0.05 parts by weight or more and 3 parts by weight or less, particularly preferably 0.1 parts by weight or more and 2 parts by weight or less, based on 100 parts by weight of the inorganic filler. If the content of the coupling agent is too small, the inorganic filler can not be sufficiently coated, so that the effect of improving the heat resistance may be deteriorated. If too large, the reaction may be affected and the bending strength and the like may be lowered.

As the curing accelerator, known ones can be used. Examples thereof include organic metal salts such as zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, cobalt (II) bishiacetate cobalt (II) and trisacetylacetonate cobalt (III), triethylamine, tributylamine, Tertiary amines such as diazabicyclo [2,2,2] octane, 2-phenyl-4-methylimidazole, 2-ethyl-4-ethylimidazole, Imidazoles such as 2-phenyl-4-methyl-5-hydroxyimidazole and 2-phenyl-4,5-dihydroxyimidazole, phenol compounds such as phenol, bisphenol A and nonylphenol, Organic acids such as salicylic acid and paratoluenesulfonic acid, and onium salt compounds, and mixtures thereof. As the curing accelerator, one kind or a derivative thereof may be used alone, or two or more kinds of these derivatives may be used in combination.

The onium salt compound is not particularly limited, and for example, an onium salt compound represented by the following general formula (IX) can be used.

Figure pct00012

(Wherein P is a phosphorus atom, R 1 , R 2 , R 3 and R 4 are each an organic group having a substituted or unsubstituted aromatic ring or heterocyclic ring, or a substituted or unsubstituted aliphatic group, A - represents an anion of n (n > = 1) protons donor having at least one proton capable of releasing out of the molecule, or an anion thereof.

The content of the curing accelerator is not particularly limited, but is preferably 0.01 to 5% by weight, more preferably 0.1 to 2% by weight based on the whole resin composition. If the content is too small, the effect of accelerating the curing may not be exhibited. If the content is too large, the preservability of the resin layer may be lowered.

Examples of the resin composition include thermoplastic resins such as phenoxy resin, polyimide resin, polyamideimide resin, polyphenylene oxide resin, polyether sulfone resin, polyester resin, polyethylene resin and polystyrene resin, styrene- A thermoplastic elastomer such as a polyolefin thermoplastic elastomer, a polyamide elastomer and a polyester elastomer; a diene such as a polybutadiene, an epoxy-modified polybutadiene, an acrylic-modified polybutadiene or a methacryl-modified polybutadiene; Based elastomer may be used in combination.

Examples of the phenoxy resin include a phenoxy resin having a bisphenol skeleton, a phenoxy resin having a naphthalene skeleton, a phenoxy resin having an anthracene skeleton, and a phenoxy resin having a biphenyl skeleton. Further, a phenoxy resin having a plurality of these skeletons may be used.

Among them, it is preferable to use a phenoxy resin having a biphenyl skeleton and a bisphenol S skeleton as the phenoxy resin. This makes it possible not only to increase the glass transition temperature of the phenoxy resin due to the rigidity of the biphenyl skeleton but also to improve the adhesion between the phenoxy resin and the metal by the presence of the bisphenol S skeleton. As a result, it is possible not only to improve the heat resistance of the element-mounted substrate but also to improve the adhesion of the wiring layer to the element-mounted substrate in the case of producing the circuit board. As the phenoxy resin, it is also preferable to use a phenoxy resin having a bisphenol A skeleton and a bisphenol F skeleton. As a result, the adhesion of the wiring layer to the element mounting substrate can be further improved at the time of manufacturing the circuit board.

It is also preferable to use a phenoxy resin having a bisphenol acetophenone structure represented by the following general formula (X).

Figure pct00013

(Wherein R 1 may be the same or different and is a hydrogen atom, a hydrocarbon group having 1 to 10 carbon atoms or a halogen atom, R 2 is a hydrogen atom, a hydrocarbon group having 1 to 10 carbon atoms or halogen And R 3 is a hydrogen atom or a hydrocarbon group having 1 to 10 carbon atoms, and m is an integer of 0 or more and 5 or less.

Since the phenoxy resin having a bisphenol acetophenone structure has a bulky structure, it is excellent in solvent solubility and compatibility with a thermosetting resin component to be compounded. In addition, since the rough surface can be formed with low roughness (low roughness), the fine wiring formation property is excellent.

The phenoxy resin having a bisphenol acetophenone structure can be synthesized by a known method such as a method of high molecular weight polymerization using an epoxy resin and a phenol resin as a catalyst.

The phenoxy resin having a bisphenol acetophenone structure may contain a structure other than the bisphenol acetophenone structure of the general formula (X), and its structure is not particularly limited, but a bisphenol A type, a bisphenol F type, a bisphenol S type, A phenol novolak type, and a cresol novolak type structure. Among them, it is preferable to include a biphenyl-type structure because the glass transition temperature is high.

The content of the bisphenol acetophenone structure in the general formula (X) in the phenoxy resin containing the bisphenol acetophenone structure is not particularly limited, but is preferably from 5 mol% to 95 mol%, more preferably from 10 mol% to 85 mol% Or less, more preferably 15 mol% or more and 75 mol% or less. If the content does not reach the lower limit value, there is a possibility that the effect of improving heat resistance and moisture resistance reliability may not be obtained. On the other hand, if the content exceeds the upper limit value, the solubility of the solvent becomes poor, which is not preferable.

The weight average molecular weight (Mw) of the phenoxy resin is not particularly limited, but is preferably 5,000 or more and 100,000 or less, more preferably 10,000 or more and 70,000 or less, most preferably 20,000 or more and 50,000 or less. If the Mw exceeds the upper limit, compatibility with other resins and solubility in solvents will be significantly deteriorated. If the Mw is less than the lower limit, the film-forming properties become worse, which causes defects when used in the production of circuit boards.

The content of the phenoxy resin is not particularly limited, but is preferably 5 wt% or more and 40 wt% or less, more preferably 10 wt% or more and 20 wt% or less, of the resin composition excluding the filler. If the content is less than the above lower limit value, the mechanical strength of the insulating resin layer may be lowered or the plating adhesion with the conductor circuit may be deteriorated. If the content exceeds the upper limit value, the thermal expansion coefficient of the insulating resin layer may be increased or the heat resistance may be lowered .

In addition, additives other than the above components such as pigments, dyes, defoaming agents, leveling agents, ultraviolet absorbers, foaming agents, antioxidants, flame retardants and ion scavengers may be added to the resin composition, if necessary.

Examples of the pigment include inorganic pigments such as kaolin, synthetic iron oxide red, cadmium yellow, nickel titanium yellow, strontium yellow, chromium hydrous oxide, chromium oxide, cobalt aluminate and synthetic ultramarine blue, polycyclic pigments such as phthalocyanine, .

The dyes include isoindolinone, isoindoline, quinophthalone, xanthene, diketopyrrolopyrrole, perylene, perinone, anthraquinone, indigoid, oxazine, quinacridone, benzimidazolone, Phthalocyanine, azomethine, and the like.

It is preferable that the average linear expansion coefficient of the core layer 21 in the in-plane direction of the substrate at 50 캜 to 70 캜 is 3 ppm / 캜 or more and 10 ppm / 캜 or less, particularly 5 ppm / 캜 or less.

(Circuit layer)

The circuit layer 22 is provided on the top and bottom surfaces of the core layer 21, and is formed of a metal such as copper. The thickness of the circuit layer 22 is not particularly limited, but is, for example, 10 to 15 占 퐉. The thickness of the pair of circuit layers 22 is the same.

(Solder resist layer)

The solder resist layer 23 is provided on the front and back surfaces of the core layer 21, respectively. An opening is formed in the solder resist layer 23, and a part of the circuit layer 22 is exposed from this opening. Here, the thickness of the pair of solder resist layers 23 is the same.

The solder resist layer 23 is made of, for example, an organic resin material. Specific examples of the organic resin material include epoxy resin, (meth) acrylate resin and polyimide resin. These may be used alone or in combination of two or more.

The thickness of the solder resist layer 23 is not particularly limited, but is, for example, 10 to 50 占 퐉.

As described above, the substrate 2 of the present embodiment has the volume occupancy rate of the fiber base layer 211 in the region a from the center plane C located at the center in the thickness direction of the substrate 2 to the semiconductor element mounting surface A is higher than the volume occupancy rate B of the fiber substrate layer 211 in the region b from the center plane C located at the center in the thickness direction of the substrate 2 to the surface opposite to the semiconductor element mounting surface. The rigidity of the substrate 2 on the element mounting surface side can be enhanced and the substrate 2 softened and the position of the semiconductor element 3 and the substrate 2 It is possible to prevent the occurrence of misalignment.

Among them, from the viewpoint of reliably reducing the warping of the substrate 2 in the semiconductor device 10, A / B is preferably 1.1 or more, and more preferably 1.2 or more.

The fiber base material layer 211 may be present only in the region a and the fiber base material layer 211 may not be present in the region b. As shown in Fig. For example, the volume occupancy rate of the fiber base layer 211 in the region a may be 50 to 90%, while the volume occupancy rate of the fiber base layer 211 in the region b may be 30 to 70%. The upper limit value of A / B is not particularly limited, but is preferably 2.0 or less from the viewpoint of warping of the substrate. By setting the A / B ratio to 2.0 or less, the warpage of the substrate itself is not excessively increased, and the circuit formation can be easily performed when a circuit is formed on the substrate. In addition, mounting of a semiconductor element on a substrate can be easily carried out.

In addition, the volume occupancy rate of the fiber base material layer 211 in the region a can be calculated as follows.

Volume occupancy ratio = (length in the longitudinal direction of the fibrous substrate layer x transverse direction length of the fibrous substrate layer x thickness of the fibrous substrate layer present in the area a) / (length in the longitudinal direction x length in the transverse direction x substrate thickness x 1/2)

The thickness of the fiber substrate layer 211 present in the region a is the average value obtained by measuring the thickness of the fiber substrate layer in the region a at 10 positions.

The volume occupancy of the fiber base layer in the region b can also be calculated by the same calculation method.

In this embodiment, the distance D3 from the surface of the fiber substrate layer to the substrate surface in the substrate 2 is shorter than the distance D4 from the surface of the fiber substrate layer to the surface of the substrate.

The average coefficient of linear expansion of the substrate 2 differs depending on the pattern of the circuit layer 22. For example, the average coefficient of linear expansion? In the in-plane direction of the substrate at 50 占 폚 to 70 占 폚 is 1 ppm / Lt; 0 > C or less. When it is 25 ppm / 占 폚 or lower, the coefficient of linear expansion with the semiconductor element 3 to be mounted can be made small, and the manufacturing stability can be made excellent. On the other hand, when it is 1 ppm / 占 폚 or higher, the difference in thermal expansion coefficient from the encapsulant is reduced and the effect of reducing warpage is obtained. Among them,? Is preferably 8 ppm / ° C or more and 20 ppm / ° C or less.

The average linear expansion coefficient can be measured in the following manner.

A 5 mm x 20 mm sample was cut out from the substrate 2 and the sample was heated from room temperature (25 deg. C) at 5 deg. C / min using TMA (TA Instruments Co., Ltd.) And the linear expansion coefficient in the in-plane direction is calculated. Then, the coefficient of linear expansion in an in-plane direction at 50 ° C to 70 ° C is calculated.

(Semiconductor device)

The semiconductor element 3 is mounted on the solder resist layer 23 of the substrate 2 with the die attach film F therebetween. The substrate 2 is larger than the semiconductor element 3 in a plan view (in a plan view) from the substrate surface side and the semiconductor element 3 is electrically connected to the substrate 2 by bonding wires W.

(Sealing material)

The encapsulant 4 covers the semiconductor element 3 while covering the surface of the substrate 2. The sealing material 4 is composed of a thermosetting resin composition.

Examples of the thermosetting resin composition include a thermosetting resin, a curing agent, and an inorganic filler.

The thermosetting resin is preferably an epoxy resin, and the epoxy resin preferably has two or more, more preferably three or more, epoxy groups in one molecule. Examples thereof include bisphenol type epoxy resins such as novolak type epoxy resins such as phenol novolak type epoxy resins and cresol novolak type epoxy resins, bisphenol A type epoxy resins and bisphenol F type epoxy resins, and N, N-diglycidyl Aromatic glycidylamine type epoxy resins such as dianiline, N, N-diglycidyl toluidine, diaminodiphenyl methane type glycidyl amine and aminophenol type glycidyl amine, hydroquinone type epoxy resins, biphenyl Type epoxy resin, triphenylmethane type epoxy resin, triphenylmethane type epoxy resin, stilbene type epoxy resin, triphenol methane type epoxy resin, triphenolpropane type epoxy resin, alkyl modified triphenol methane type epoxy resin, An epoxy resin, a naphthalene type epoxy resin, a phenol aralkyl type epoxy resin having phenylene and / or biphenylene skeleton, an epoxy resin having phenylene and / or biphenylene skeleton Alicyclic epoxy resins such as cyclohexanedimethanol, cyclohexanedimethanol, cyclohexanedimethanol, cyclohexanedimethanol, cyclohexanedimethanol, cyclohexanedimethanol, cyclohexanedimethanol, and cyclohexanedimethanol; These may be used alone or in combination of two or more.

The lower limit value of the content of the thermosetting resin is not particularly limited to 100% by weight of the total amount of the thermosetting resin composition, but is preferably 1% by weight or more and 30% by weight or less, more preferably 5% by weight or more and 20% By weight is not more than 10% by weight.

The curing agent is not particularly limited, but phenol resin can be used, for example. These phenolic resin-based curing agents are generally monomers, oligomers and polymers having two or more, more preferably three or more phenolic hydroxyl groups in one molecule, and their molecular weight and molecular structure are not particularly limited. For example, phenol novolak Novolak type resins such as resin, cresol novolak resin and naphthol novolac resin; A multifunctional phenol resin such as triphenol methane type phenol resin; Modified phenolic resins such as terpene-modified phenol resin and dicyclopentadiene-modified phenol resin; Phenolic aralkyl resins having phenylene skeleton and / or biphenylene skeleton, aralkyl resins such as naphthol aralkyl resin having phenylene and / or biphenylene skeleton; And bisphenol compounds such as bisphenol A and bisphenol F, and the like. These may be used alone or in combination of two or more. Such a phenol resin-based curing agent improves balance among flame retardancy, moisture resistance, electrical properties, curability, storage stability, and the like. Particularly, from the viewpoint of the curability, for example, the hydroxyl group equivalent of the phenol resin-based curing agent can be 90 g / eq or more and 250 g / eq or less.

Examples of the curing agent that can be used in combination include a curing agent of a middle part type, a catalyst type curing agent, and a condensation type curing agent.

Examples of the curing agent of the middle part type include aliphatic polyamines such as diethylenetriamine (DETA), triethylenetetramine (TETA) and metaoxylenediamine (MXDA), diaminodiphenylmethane (DDM), m- Polyamine compounds including dicyandiamide (DICY), organic acid dihydrazide and the like in addition to aromatic polyamines such as diamine (MPDA) and diaminodiphenylsulfone (DDS); Alicyclic acid anhydrides such as hexahydrophthalic anhydride (HHPA) and methyltetrahydrophthalic anhydride (MTHPA), anhydrides such as trimellitic anhydride (TMA), pyromellitic acid anhydride (PMDA) and benzophenone tetracarboxylic acid Acid anhydrides including acid anhydrides and the like; Polymercaptan compounds such as polysulfide, thioester, and thioether; Isocyanate compounds such as isocyanate prepolymer and blocked isocyanate; And organic acids such as carboxylic acid-containing polyester resin.

Examples of catalyst type curing agents include tertiary amine compounds such as benzyldimethylamine (BDMA) and 2,4,6-trisdimethylaminomethylphenol (DMP-30); Imidazole compounds such as 2-methylimidazole and 2-ethyl-4-methylimidazole (EMI24); And Lewis acids such as BF3 complexes.

Examples of the condensation type curing agent include urea resins such as methylol group-containing urea resins; And melamine resins such as methylol group-containing melamine resins.

When these other curing agents are used in combination, the lower limit of the content of the phenolic resin-based curing agent is preferably 20% by weight or more, more preferably 30% by weight or more, and particularly preferably 50% by weight or more based on the total curing agent. When the blend ratio is within the above range, good fluidity can be exhibited while maintaining flame resistance and soldering resistance. The upper limit of the content of the phenol resin-based curing agent is not particularly limited, but is preferably 100% by weight or less based on the total curing agent.

The lower limit of the total content of the curing agent to the thermosetting resin composition of the present invention is not particularly limited, but is preferably 0.8% by weight or more, more preferably 1.5% by weight or more based on 100% by weight of the total amount of the thermosetting resin composition. When the lower limit of the mixing ratio is within the above range, good curability can be obtained. The upper limit of the total content of the curing agent is not particularly limited, but is preferably 12% by weight or less, more preferably 10% by weight or less based on 100% by weight of the total amount of the thermosetting resin composition.

Examples of the inorganic filler include fused silica, spherical silica, crystalline silica, alumina, silicon nitride, and aluminum nitride. The particle size of the inorganic filler is preferably 0.01 탆 or more and 150 탆 or less from the viewpoint of the filling property with respect to the mold cavity.

The content of the inorganic filler is preferably 60% by weight or more, more preferably 80% by weight or more, still more preferably 83% by weight or more, and even more preferably 86% by weight or less based on 100% by weight of the total amount of the thermosetting resin composition. %. When the lower limit is within the above range, the increase in the moisture absorption amount and the decrease in the strength accompanying the curing of the thermosetting resin composition obtained can be reduced. The amount of the inorganic filler is preferably 95% by weight or less, more preferably 93% by weight or less, and still more preferably 91% by weight or less based on the total amount of 100% by weight of the thermosetting resin composition. When the upper limit is within the above range, the obtained thermosetting resin composition has good flowability and good moldability.

Further, the thermosetting resin composition may contain a curing accelerator. The curing accelerator may be one which accelerates the reaction between the epoxy group of the epoxy resin and the hydroxyl group of the phenolic resin curing agent, and a commonly used curing accelerator may be used.

Specific examples of the curing accelerator include phosphorus atom-containing compounds such as organic phosphine, phosphobetaine compounds, adducts of phosphine compounds and quinone compounds, and the like.

The thickness of the sealing material 4 is not particularly limited, but is, for example, 300 to 500 mu m.

The encapsulant (cured product) 4 preferably has an average coefficient of linear expansion? At 50 占 폚 to 70 占 폚 of 8 ppm / 占 폚 to 25 ppm / 占 폚. Among them, it is more preferable to be 9 ppm / ° C or more and 15 ppm / ° C or less.

By setting the average coefficient of linear expansion? To 25 ppm / DEG C or less, it is possible to suppress the largely shrinkage of the sealing material 4 after curing. On the other hand, when the average linear expansion coefficient? Is 8 ppm / 占 폚 or more, the shrinkage force of the sealing material 4 generated in the step of cooling the sealing material 4 after curing or the like is applied to the substrate 2, It is possible to reliably provide a small semiconductor device 10.

Here, it is preferable that? -? Is -6 ppm / 占 폚 or higher and 12 ppm / 占 폚 or lower. It is possible to prevent the reliability of the semiconductor device 10 from deteriorating in a temperature cycle test or the like by setting? -? to -6 ppm / 占 폚 or more and 12 ppm / 占 폚 or less.

Next, a manufacturing method of the semiconductor device 10 of the present embodiment will be described.

Will be described with reference to Figs. 1 and 2. Fig.

First, the substrate 2 is prepared.

Here, the substrate 2 can be manufactured as follows.

First, a prepreg composed of a resin layer 212 and a fiber base layer 211 is prepared. In this prepreg, the fibrous substrate layer 211 is shifted from the central position in the thickness direction of the prepreg toward the prepreg surface side. A prepreg having such a structure can be produced, for example, as follows. The fiber base layer 211 is sandwiched by a pair of film-like resin layers (composed of the resin layer 212) having different thicknesses. Then, a pair of resin layers are melted and impregnated into the fiber base layer 211. Thereby, in the thickness direction, prepregs in which the fibrous substrate layer 211 is unevenly distributed can be obtained.

Then, a pair of metal layers 22 '(for example, a copper layer) is disposed so as to sandwich the prepregs therebetween (see FIG. As a result, the resin layer 212 is completely cured to obtain the laminate 20. Here, since the fibrous substrate layer 211 is localized on the surface side of one side of the prepreg in the thickness direction, the laminated sheet 20 is formed such that one side of the front side is convex (Convex) surface shape, and is bent in a convex shape (so-called cry bending). In other words, the laminated plate 20 is inverted U-shaped.

Next, a through hole 213 is formed in the laminated plate 20. Thereafter, a first plating layer is formed on the inner surface of the through hole 213 and the metal layer 22 ', and the conductor 214 is filled in the through hole 213. Subsequently, a second plating layer is further formed on the first plating layer so as to cover the conductor 214, and then etching is performed to form the circuit layer 22. Next,

Thereby, a laminate in which the core layer 21 and the circuit layer 22 are laminated is obtained. Thereafter, a solder resist layer 23 is formed on the circuit layer 22, and openings are formed in the solder resist layer 23 to expose the circuit layer 22.

Thereby, the substrate 2 can be obtained as shown in Fig. 2 (b).

The substrate 2 has a convex shape warped toward the side where the semiconductor element 3 is mounted at 25 占 폚. The bending amount of the substrate 2 is, for example, -30 mu m to-100 mu m. - means that the element mounting surface side of the substrate 2 is warped in a convex shape and + means that the surface of the substrate 2 opposite to the semiconductor element mounting surface is warped in a convex shape.

The bending amount can be measured in the following manner.

The measurement is carried out using a temperature-variable laser three-dimensional measuring instrument (LS200-MT100MT50: manufactured by Titech Co., Ltd.). The distance from the laser head to the laser head was measured at 25 占 폚 by measuring the laser beam on the surface of the substrate 2 (the side on which the semiconductor element was mounted) with a measuring range of 13 mm x 13 mm, Let the car be the deflection amount.

Then, the semiconductor element 3 is mounted on the substrate 2.

A die attach film F is attached to the semiconductor element 3 and the semiconductor element 3 is mounted on the substrate 2 via the die attach film F. [ Thereafter, the semiconductor element 3 and the substrate 2 are electrically connected by a wire W. When the wire bonding is performed, the substrate 2 and the semiconductor element 3 are heated at 100 to 200 DEG C for 2 to 5 minutes, for example. While this heating is being performed, the warpage of the substrate 2 is removed by heating, and the substrate 2 becomes approximately flat.

Here, as described above, in the substrate 2, the volume occupancy A of the fiber substrate layer 211 in the region from the center face C located at the center in the thickness direction of the substrate 2 to the semiconductor element mounting face Is higher than the volume occupancy rate B of the fiber substrate layer 211 in the region from the center face C to the surface opposite to the semiconductor element mounting surface. As a result, the rigidity of the side of the semiconductor element mounting surface becomes high, so that the semiconductor element can be mounted at a desired position even when the substrate 2 is heated while the semiconductor element 3 is mounted on the substrate 2.

When the wire bonding is completed, the substrate 2 and the semiconductor element 3 are cooled to room temperature.

At this time, as shown in Fig. 2 (c), the substrate 2 becomes convex toward the side where the semiconductor element 3 is mounted at 25 占 폚. The amount of bending of the substrate 2 is, for example, -30 mu m to-100 mu m. The method of measuring the amount of bending is as described above.

Thereafter, the semiconductor element 3 is sealed with the sealing material 4. The encapsulating method may be any of potting, transfer molding, and compression molding.

In this sealing step, the sealing material 4, the semiconductor element 3, and the substrate 2 are heated at 175 占 폚, for example, and the sealing material 4 is cured. Thereafter, the sealing material 4, the semiconductor element 3, and the substrate 2 are cooled, and the semiconductor device 10 is obtained (see Fig. 1).

Here, the sealing material 4 is hardened and shrunk in the curing step and shrinks in the cooling step. The sealing member 4 is contracted, and the element mounting surface side of the substrate 2 is attracted to the sealing member 4 side.

Particularly, in the case where the amount of shrinkage of the sealing material in the curing process and the cooling process is larger than the shrinkage amount of the substrate, the side of the substrate 2 on which the device is mounted tends to be attracted to the sealing material 4 side. The semiconductor device 10 is warped due to the difference between the shrinkage amount of the sealing material 4 and the shrinkage amount of the substrate. In this embodiment, since the substrate 2 warped in a convex shape is used in the case of the substrate alone, The amount of warping of the substrate 2 after the sealing process becomes a small value, and the semiconductor device 10 with reduced warpage can be obtained.

The substrate 2 in the semiconductor device 10 is in a state in which the flat surface or the surface opposite to the semiconductor element mounting surface is slightly bent in a convex shape (so-called smile warpage).

Here, the amount of warping of the substrate 2 at 25 DEG C in the step of preparing the substrate 2 is M, the amount of warping of the substrate 2 in the semiconductor device 10 after the sealing step is N, M is from -30 mu m to-100 mu m, and N is from 0 mu m to +100 mu m.

In measuring the amount of bending of the substrate 2 in the state of the semiconductor device 10, the back surface of the substrate (the surface opposite to the semiconductor element mounting surface) may be measured with a laser.

Here, the conventional technology level will be described.

When a flat substrate is incorporated in a semiconductor device as disclosed in Patent Document 1, the substrate is greatly curved (smile warp) in a convex shape toward the side opposite to the semiconductor element side. In the case of encapsulating a semiconductor element with an encapsulating material, the encapsulation material largely shrinks and the substrate is largely bent.

On the other hand, in the present embodiment, the substrate 2 bent in a convex shape (so-called cry bending) is used on the side of the semiconductor element mounting surface in the state of the substrate alone. The volume occupancy rate A of the fibrous substrate layer 211 in the substrate 2 is made higher than the volume occupancy rate B. [ Thus, the substrate 2 is hardly shrunk in the area from the center plane C located at the center in the thickness direction of the substrate 2 to the semiconductor element mounting surface, and the area from the center plane C to the surface opposite to the semiconductor element mounting surface The region becomes a structure which is easy to shrink heat. Therefore, in the substrate 2 itself, the semiconductor element mounting surface side is bent so as to have a convex shape. However, by disposing the sealing material 4 on the substrate 2, the shrinkage force in the curing shrinking and cooling steps of the sealing material 4 acts on the substrate 2. As a result, the warpage of the substrate 2 is eliminated. The substrate 2 in the semiconductor device 10 has a flat surface or a surface opposite to the semiconductor element mounting surface in a convex shape in a slightly warped state (so-called smile warpage).

As described above, Patent Document 1 discloses a prepreg in which a fiber substrate layer is distributed in a thickness direction. However, in a substrate using the prepreg, the fiber base layer is symmetric Respectively. That is, in the substrate disclosed in Patent Document 1, the volume occupancy A of the fibrous substrate layer in the area up to the semiconductor element mounting surface and the volume occupancy A of the fiber in the area from the center of the substrate thickness to the surface opposite to the semiconductor element mounting surface The volume occupancy B of the substrate is made equal.

In Patent Document 1, since the fiber base layers are arranged symmetrically with the center line of the thickness of the substrate interposed therebetween, it is considered that warping in a single substrate state is reduced. Conventionally, in order to obtain a semiconductor device free from warpage, it has been thought that it is important to reduce the warpage in the state of a single substrate, so Patent Document 1 adopts such a structure. Therefore, it can not be assumed at all from Patent Document 1 that the volume occupancy A of the fibrous base material is higher than the volume occupancy B.

The present invention is not limited to the above-described embodiments, and variations, modifications, and the like within the scope of achieving the object of the present invention are included in the present invention.

For example, in the above embodiment, the substrate 2 is a so-called core substrate composed of a core layer 21, a circuit layer 22, and a solder resist layer 23, . A buildup substrate 5 having a core layer 21 and buildup layers 51 and 52 is used as shown in Fig. The build-up layer 51 of the substrate 5 is laminated on the surface of the core layer 21 on the side of the semiconductor element mounting surface. The buildup layer 51 is composed of a so-called prepreg, and includes a fiber base layer 511 and an insulating resin layer 512. The fiber base layer 511 may be the same as the fiber base layer 211 described above. The resin layer 512 may be the same as the resin layer 212 of the core layer 21 described above.

The fibrous substrate layer 511 of each buildup layer 51 is located on the semiconductor element mounting surface side of the substrate 2 with respect to the center position of the thickness of the buildup layer 51,

On the other hand, the buildup layer 52 is laminated on the back surface side of the core layer 21. The buildup layer 52 is composed of a resin layer and does not include a fiber substrate layer. As the resin layer, the same resin layer 212 as that of the core layer 21 described above can be used.

In the substrate 5, the build-up layer 51 and the circuit layer 53 are alternately arranged, and a build-up layer 51 is provided with a via hole. The inside of the via hole is filled with a conductor 513 such as copper.

On the buildup layer 51, a solder resist layer 54 is provided. The solder resist layer 54 includes a resin layer 542 composed of the same solder resist layer 23 as in the above embodiment and a fiber base layer 541. The resin base layer 541 has a resin layer 541, (542) is impregnated. The fiber base layer 541 is disposed on the side of the semiconductor element 3 more than the center position of the thickness of the solder resist layer 54. The fiber base material constituting the fiber base material layer 541 is the same as the fiber base material layer 211 of the above-described embodiment.

In the substrate 5, the buildup layer 52 and the circuit layer 53 are alternately arranged, and a build-up layer 52 is provided with a via hole. A conductor 523 such as copper is filled in the via hole. A solder resist layer 23 is provided on the buildup layer 51.

The semiconductor element 3 and the substrate 5 are connected via a solder bump.

The volume occupation rate A of the fiber substrate layers 211 and 511 in the region from the center face C of the substrate 5 to the semiconductor element mounting face is smaller than the volume occupation rate A of the substrate 5 in the semiconductor device 50, Is higher than the volume occupancy rate B of the fibrous substrate layer in the region from the thickness center face C of the substrate to the surface opposite to the semiconductor element mounting surface. Thus, the same effects as those of the above-described embodiment can be obtained.

The semiconductor device of the present invention may be a semiconductor device 60 as shown in Fig.

The substrate 6 of the semiconductor device includes a core layer 21 and a buildup layer 51. The fiber base layer 511 of each buildup layer 51 located above the core layer 21 of FIG. 4 is located on the semiconductor element mounting surface side of the substrate 2 with respect to the center position of the thickness of the buildup layer 51, Respectively.

The semiconductor element 3 and the substrate 5 are connected via a solder bump.

In this semiconductor device 60, the volume occupancy A of the fibrous substrate layers 211 and 511 in the region from the center face C of the substrate 6 to the semiconductor element mounting face is larger than the center Is higher than the volume occupancy rate B of the fiber substrate layer 511 in a region from the surface C to the surface opposite to the semiconductor element mounting surface. Thus, the same effects as those of the above-described embodiment can be obtained.

Particularly, when manufacturing the semiconductor devices 50 and 60 shown in Figs. 3 and 4, it is necessary to mount the semiconductor element 3 on the substrates 5 and 6, and then reflow at a high temperature. Therefore, the substrates 5 and 6 are easily softened and the warpage of the substrates 5 and 6 is deteriorated. As a result, the connection reliability between the semiconductor element 3 and the substrates 5 and 6 may deteriorate. , 6) on the side of the semiconductor element mounting surface are high, it is possible to suppress the deterioration of the warpage and the deterioration of the connection reliability.

4, the fiber base layer 511 of the buildup layer 51 below the core layer 21 is located on the opposite side of the center of the thickness of the buildup layer 51 from the semiconductor element mounting surface. Similarly, in the solder resist layer 54 lower than the core layer 21 in Fig. 4, the fiber base layer 541 is located on the opposite side of the thickness center position from the semiconductor element mounting surface. Even if the fiber substrate layer is unevenly distributed, the volume occupied rate A of the fiber substrate layer in the area from the center face C of the substrate 6 to the semiconductor element mounting face is smaller than the volume occupancy A of the substrate 6 from the center face C The volume occupied rate B of the fibrous substrate layer in the region up to the maximum.

The semiconductor device of the present invention may be a semiconductor device 70 as shown in Fig.

The substrate 7 of this semiconductor device has a core layer 21 and a build-up layer 52.

The volume occupancy A of the fiber substrate layer 211 in the region from the center face C of the substrate 7 to the semiconductor element mounting face is smaller than the volume occupancy A of the substrate 7 from the center face C of the substrate 7 to the semiconductor element mounting face Is higher than the volume occupancy rate (B) of the fibrous substrate layer in the area up to the opposite surface. Thus, the same effects as those of the above-described embodiment can be obtained.

The semiconductor device of the present invention may be a semiconductor device 80 of a chip size package as shown in Fig. This semiconductor device 80 has a substrate 8 having a core layer 21, a circuit layer 22 and a solder resist layer 23. A resin layer 81 (underfill) is filled between the substrate 8 and the semiconductor element 3. The volume occupancy A of the fibrous substrate layer 211 in the region from the center face located at the center in the thickness direction of the substrate 8 to the semiconductor element mounting face is smaller than the volume occupied ratio A Is higher than the volume occupancy rate B of the fibrous substrate layer (211) in a region from the surface opposite to the semiconductor element mounting surface to the surface. Thus, the same effects as those of the above-described embodiment can be obtained.

In the semiconductor devices 50 and 60 shown in Figs. 3 and 4, the contact area between the sealing material 4 and the substrates 6 and 7 is relatively small. In the semiconductor device 80 shown in Fig. 6, the sealing material 4 and the substrate 8 are not in contact with each other. However, since the contractile force of the sealing material 4 acts on the substrates 6, 7 and 8, the same effects as those of the above embodiments can be obtained.

In each modification described above, the coefficient of linear expansion of the substrate is in the same range as in the above-described embodiment, and the semiconductor device can be obtained by the same manufacturing method as in the above-described embodiment. Also, the change in the warpage of the substrate is the same as in the above-described embodiment.

That is, similarly to the above-described embodiment, the substrates 5 to 8 are bent in a convex shape toward the side where the semiconductor element 3 is mounted at 25 占 폚. When the semiconductor element 3 is mounted, the warpage of the substrates 5 to 8 is eliminated by heating, and the substrates 5 to 8 become substantially flat. Subsequently, the substrates 5 to 8 and the semiconductor element 3 are cooled. After cooling, the substrates 5 to 8 are bent in convex form toward the semiconductor element 3 at 25 占 폚. Thereafter, the bending of the substrates 5 to 8 is relieved by performing the sealing, and the surfaces of the substrates 5 to 8 are flat or the surface opposite to the semiconductor element mounting surface is in a slightly warped state in a convex shape.

In the above embodiment, the step of manufacturing one semiconductor device has been described, but a plurality of semiconductor devices may be manufactured at one time.

For example, the substrate 2 may be a substrate having a plurality of element mounting regions divided by a dicing region, and the semiconductor elements may be mounted on each of the element mounting regions of the substrate. Thereafter, after sealing each semiconductor element, the substrate may be cut along the dicing region.

Example

Next, an embodiment of the present invention will be described.

(evaluation)

In the Examples and Comparative Examples, the following evaluations were carried out.

(1) bending of the substrate

The warping of the substrate at 25 占 폚 was measured using a temperature-variable laser three-dimensional measuring instrument (LS200-MT100MT50: manufactured by Tatech Co., Ltd.). The surface of the substrate was measured with a laser in a range of 13 mm x 13 mm, and the distance from the laser head was determined as the difference between the maximum point and the latest point.

Further, the warpage of the substrate sandwiched by the semiconductor device was measured by irradiating the surface of the substrate opposite to the semiconductor element mounting surface with a laser. The number of samples was 10, and the average value was defined as warpage.

(2) Average coefficient of linear expansion (CTE1)

The average linear expansion coefficient of the substrate was measured as follows.

A 5 mm x 20 mm test piece was prepared and the linear expansion coefficient in the in-plane direction (XY direction) at 50 캜 to 90 캜 was measured at 5 캜 / min using a TMA apparatus (TA Instruments) Lt; 0 > C to 70 < 0 > C.

The average linear expansion coefficient of the encapsulant was measured as follows.

The resin composition to be a raw material of the sealing material was molded into a width of 5 mm, a length of about 20 mm and a thickness of 4 mm and cured in an oven at 175 ° C for 5 hours. The sample was measured for the coefficient of linear expansion at 50 ° C to 90 ° C at a rate of 5 ° C / min using a TMA device (TA Instruments), and the average linear expansion coefficient at 50 ° C to 70 ° C was calculated.

(3) Elastic modulus

The elastic modulus of the substrate was measured as follows.

A width of 10 mm, a length of about 150 mm, and a thickness of 4 mm, and a 10 mm x 60 mm test piece was cut out from the laminate and heated at a rate of 3 ° C / min using a dynamic viscoelasticity measuring apparatus (DMA983, TA Instruments).

The elastic modulus of the sealing material was measured in the following manner.

The resin composition to be a raw material of the sealing material was molded into a width of 10 mm, a length of about 150 mm and a thickness of 4 mm and cured in an oven at 175 ° C for 5 hours. The sample was heated at a rate of 3 DEG C / min using a dynamic viscoelasticity measuring apparatus (DMA983, TA Instruments Inc.) and measured.

(4) Reliability test

Four semiconductor devices fabricated in Examples and Comparative Examples were treated at 60 ° C and 60% for 40 hours, then treated in an IR reflow furnace (peak temperature: 260 ° C) three times, And then subjected to 2000 cycles at 55 占 폚 (15 minutes) and 125 占 폚 (15 minutes). Subsequently, it was observed that there was no abnormality in the semiconductor device by using an ultrasonic imaging apparatus (FS300 made by Hitachi Kenki Fine Tech Co., Ltd.).

◎: No abnormality in semiconductor device.

○: A crack was found in a part of semiconductor device.

(Example 1)

(Preparation of prepreg)

1. Preparation of varnish A of resin composition

, 11.0 parts by weight of biphenyl aralkyl type novolak epoxy resin (NC-3000, manufactured by Nippon Kayaku Co., Ltd.), 8.8 parts by weight of biphenyl dimethylene type phenol resin (GPH-103 made by Nippon Kayaku Co., 16.0 parts by weight of PrimaSet PT-30 manufactured by Lonza Japan Co., Ltd.) and 4.0 parts by weight of a bisphenol A cyanate resin (Prima Set BA230, manufactured by Lonza Japan) were dissolved and dispersed in methyl ethyl ketone. 60.0 parts by weight of spherical fused silica (SO-32R, manufactured by Admatechs Co., Ltd., average particle diameter 1 μm) as filler A and 0.2 parts by weight of γ-glycidoxypropyltrimethoxysilane (A187 manufactured by Momentive Performance Inc.) And the mixture was stirred for 30 minutes using a high-speed stirrer and adjusted to a nonvolatile content of 50% by weight to prepare a resin varnish (resin varnish).

2. Manufacture of Carrier Material

The resin varnish obtained above was coated on a PET film (polyethylene terephthalate, Purex film, manufactured by Teijin Dupont Film Co., Ltd., thickness 36 mu m) so as to have a thickness of 15.0 mu m after drying using a die coater, And dried in a drying apparatus at 160 캜 for 5 minutes to obtain a resin sheet with a first PET film (first carrier material).

The resin varnish was similarly coated on a PET film and dried in a drier at 160 캜 for 5 minutes so that the thickness of the resin layer after drying was 22.0 탆 to obtain a resin sheet with a second PET film (second carrier material).

3. Preparation of prepreg

The first carrier material and the second carrier material were placed on both sides of a glass fiber substrate (46 占 퐉 thick, Nitoboseki Co., Ltd., WEA-1280, IPC standard 1280) so that the resin layer faced the fiber substrate and vacuum laminator The resin composition was impregnated with a drying apparatus to obtain a prepreg in which a PET film was laminated.

Specifically, the first and second carrier materials are placed on both sides of the glass fiber substrate so as to be located at the center in the width direction of the glass fiber substrate, and are superimposed under pressure at a pressure of 9.999 × 10 4 Pa (about 750 Torr) Lt; RTI ID = 0.0 > 80 C < / RTI >

Here, in the inner region of the widthwise dimension of the glass fiber substrate, the resin layers of the first carrier material and the second carrier material are bonded to both surfaces of the glass fiber substrate, The resin layers of the first carrier material and the second carrier material were bonded to each other.

Next, the joint was passed through a transverse conveying type hot-air drying apparatus set at 120 占 폚 for 2 minutes, and heat treatment was performed without applying pressure to obtain a prepreg.

At this time, the distance from the surface of the fiber substrate layer to the surface of the resin layer (corresponding to the distance D1 in Fig. 1) was 4 占 퐉, the thickness of the glass fiber substrate layer was 46 占 퐉, 1) of 10 mu m and a total thickness of 60 mu m.

(Fabrication of Substrate)

Next, using the prepreg obtained above, a substrate was produced in the same manner as in the above-described embodiment.

The PET film was peeled from the obtained prepreg, and 12 占 퐉 copper foil (3EC-VLP foil manufactured by Mitsui Mining and Mining Company) was overlaid on the front and back surfaces of the prepreg and heated and pressed at 220 占 폚 and 3 MPa for 2 hours to form a metal layer To obtain a laminated board. The thickness of the obtained core layer (a portion made of prepreg) of the obtained laminate was 60 탆.

At this time, one side of the laminate was curved in a convex surface shape and warped in a convex shape (cry bending) (see Fig. 2 (a)).

Next, a through hole was formed in this laminated plate with a carbonic acid laser. Thereafter, the inside of the through-hole was immersed in a swelling liquid (Swellingsip Sekirligant P, manufactured by Artec Co., Ltd.) at 60 DEG C for 5 minutes and further immersed in a potassium permanganate aqueous solution (Arttech Japan Co., Concentrate Compact CP) After immersion for 10 minutes, the mixture was neutralized and subjected to harmony treatment. After the steps of degreasing, catalyst addition, and activation were performed, a plating layer was formed on the inner surface of the through hole and the metal layer, and the conductor was filled in the through hole. Next, a plating layer was further formed on the plating layer so as to cover the conductor, and then a circuit layer (residual ratio of 70%, L / S = 50/50 탆) was formed by etching. The thickness of the circuit layer was 15 mu m. The circuit layers are provided on the front and back surfaces of the laminate.

Subsequently, a solder resist layer (trade name: AUS410, thickness 20 占 퐉, manufactured by TAIYO INK MFG. CO., LTD.) Was superimposed on each circuit layer and superposed thereon by vacuum heating and pressing at a temperature of 150 DEG C and a pressure of 1 MPa for 120 seconds using a vacuum pressure type laminator. Thereafter, heat curing was carried out at 220 DEG C for 60 minutes in a hot-air drying apparatus. The solder resist layer is provided on the front and back surfaces of the laminate. Then, a blind via hole (non-through hole) was formed by a carbonic acid laser so that the circuit layer was exposed.

The thus obtained substrate was cut into a size of 50 mm x 50 mm to obtain a substrate for a semiconductor package. This substrate was curved in a convex shape toward the side where the semiconductor element 3 was mounted (creeping). The warping amount of the substrate (25 캜) was -53 탆.

In this substrate, the volume occupied ratio A of the fibrous substrate in the region from the center plane located at the center of the substrate in the thickness direction to the semiconductor element mounting surface is from the center plane of the substrate to the surface opposite to the semiconductor element mounting surface Of the fibrous base material in the region of " B " The volume occupancy of the fiber base layer in the region from the center in the thickness direction of the core layer (prepreg) to the surface of the core layer on the side of the substrate on which the semiconductor element is mounted is smaller than the volume occupancy Is higher than the volume occupied rate of the fibrous substrate layer in a region from the surface of the layer to the backside opposite to the surface.

(Fabrication of semiconductor device)

A semiconductor element (TEG chip, size 20 mm x 20 mm, thickness 200 m) was mounted on the substrate for the semiconductor package obtained above. A die attach film is attached to a semiconductor element, and a semiconductor element is mounted on the substrate via the die attach film. Thereafter, the semiconductor element and the substrate were electrically connected by a wire. In this wire bonding process, the substrate was heated to 150 占 폚.

After the wire bonding process, the substrate was cooled to 25 占 폚. At this time, the substrate (25 占 폚) had a convex shape warped (creeping) toward the side where the semiconductor element 3 was mounted.

Subsequently, the semiconductor element mounting surface was sealed by transfer molding at 175 DEG C for 90 seconds and at a pressure of 6.9 MPa using an encapsulating material (made of a thermosetting resin composition, manufactured by Sumitomo Bakelite Co., Ltd., silica filling amount: 85 wt% , And 175 [deg.] C for 5 hours. Thereafter, the temperature was cooled to 25 占 폚 to obtain a semiconductor device.

In the semiconductor device, the substrate was warped in a convex shape toward the opposite side to the semiconductor element, and so-called smile warpage was observed. The warpage of the substrate in the semiconductor device was +94 m.

The thickness of the sealing material was 350 mu m.

Table 1 shows the evaluation results.

Table 2 shows the coefficient of linear expansion and the modulus of elasticity of the substrate and the sealing material.

(Example 2)

In Example 2, the thickness of the sealing material was set to be different from that in Example 1 (450 μm). The other points are the same as those of the first embodiment.

Also in the second embodiment, the volume occupancy A of the fibrous substrate in the region from the center plane located at the center of the substrate in the thickness direction to the semiconductor element mounting surface in the substrate is smaller than the volume occupied rate A Is higher than the volume occupancy rate B of the fibrous substrate in the area to the opposite surface. The volume occupancy of the fibrous base layer in the region from the center in the thickness direction of the core layer (prepreg) to the surface of the core layer on the semiconductor element mounting surface side of the substrate is smaller than the volume occupancy Is higher than a volume occupied rate of the fibrous substrate layer in a region from the surface of the core layer to the backside opposite to the surface.

Also in the second embodiment, the substrate has a convex shape in a shape toward the side where the semiconductor element 3 is mounted. The warping amount of the substrate (25 캜) was -54 탆. Further, after the wire bonding process, the substrate (25 캜) after cooling the substrate to 25 캜 was formed into a convex shape toward the side where the semiconductor element 3 was mounted. Further, in the semiconductor device, the substrate was bent in a convex shape toward the opposite side of the semiconductor element, and so-called smile warping. The warp of the substrate in the semiconductor device was +97 mu m.

Table 1 shows the evaluation results.

(Example 3)

In Example 3, the thickness of the sealing material was 450 mu m and the thickness of the semiconductor device was 300 mu m. Other points are the same as those of the first embodiment.

The volume occupancy A of the fibrous substrate in the area from the center face located at the center in the thickness direction of the substrate to the semiconductor element mounting face in the substrate in Example 3 is smaller than the volume occupancy A of the fibrous substrate from the center face of the substrate Is higher than the volume occupancy rate B of the fibrous substrate in the area to the opposite surface. The volume occupancy of the fibrous base layer in the region from the center in the thickness direction of the core layer (prepreg) to the surface of the core layer on the semiconductor element mounting surface side of the substrate is smaller than the volume occupancy Is higher than a volume occupied rate of the fibrous substrate layer in a region from the surface of the core layer to the backside opposite to the surface.

Also in the third embodiment, the substrate has a convex shape in a shape toward the side where the semiconductor element 3 is mounted. The bending amount of the substrate (25 DEG C) was -49 mu m. Further, after the wire bonding process, the substrate (25 캜) after cooling the substrate to 25 캜 was formed into a convex shape toward the side where the semiconductor element 3 was mounted. Further, in the semiconductor device, the substrate was bent in a convex shape toward the opposite side of the semiconductor element, and so-called smile warping. The warp of the substrate in the semiconductor device was +62 mu m.

Table 1 shows the evaluation results.

(Comparative Example 1)

In Comparative Example 1, the distance from the surface of the fiber substrate layer to the surface of the resin layer (corresponding to the distance D1 in Fig. 1) was 7 mu m and the distance from the back surface of the fiber substrate layer to the back surface of the resin layer ) Was set at 7 mu m. The substrate of Comparative Example 1 is such that the volume occupied volume A of the fibrous substrate in the region from the center face located at the center in the thickness direction of the substrate to the semiconductor element mounting face is smaller than the volume occupied ratio A Is equal to the volume occupancy rate B of the fibrous substrate in the area up to < / RTI > Other points are the same as those of the first embodiment.

In the state of the substrate alone, the surface of the substrate opposite to the semiconductor element mounting surface protruded in a convex shape and was curved in a concave shape (smile warp). The bending amount of the substrate (25 DEG C) was +38 mu m. Further, after the wire bonding process, the substrate (25 캜) after cooling the substrate to 25 캜 still had a concave shape. Further, also in the semiconductor device, the substrate was in a state of smear warping bent in a concave shape, and the warping of the substrate in the semiconductor device was +142 占 퐉.

Table 1 shows the evaluation results.

(Comparative Example 2)

In Comparative Example 2, the distance from the surface of the fiber substrate layer to the surface of the resin layer (corresponding to the distance D1 in Fig. 1) was 7 mu m and the distance from the back surface of the fiber substrate layer to the back surface of the resin layer ) Was set at 7 mu m. The substrate of Comparative Example 2 had a volume occupied ratio A of the fibrous substrate in the region from the center face located at the center in the thickness direction of the substrate to the semiconductor element mounting face to the surface Is equal to the volume occupancy rate B of the above-mentioned fiber substrate layer in the region up to The other points are the same as those of the second embodiment.

In the state of the substrate alone, the surface of the substrate on the opposite side of the semiconductor element mounting surface protruded in a convex shape and was curved in a concave shape (smile warp). The bending amount of the substrate (25 캜) was +42 탆. After the wire bonding step, the substrate (25 DEG C) after cooling the substrate to 25 DEG C still had a concavely warped shape (smile warp). Also in the semiconductor device, the substrate was in a state of smoothing warp bent in a concave shape, and the warpage of the substrate in the semiconductor device was +144 탆.

Table 1 shows the evaluation results.

(Comparative Example 3)

In Comparative Example 3, the distance from the surface of the fiber substrate layer to the surface of the resin layer (corresponding to the distance D1 in Fig. 1) was 7 mu m and the distance from the back surface of the fiber substrate layer to the back surface of the resin layer ) Was set at 7 mu m. In the substrate of Comparative Example 3, the volume occupancy A of the fibrous substrate layer in the region from the center face located at the center in the thickness direction of the substrate to the semiconductor element mounting face is smaller than the volume occupancy A of the fibrous substrate layer from the center face of the substrate Is equal to the volume occupancy rate B of the fiber substrate layer in the area up to the surface. The other points are the same as those of the third embodiment.

In the state of the substrate alone, the surface of the substrate on the opposite side of the semiconductor element mounting surface protruded in a convex shape and was curved in a concave shape (smile warp). The bending amount of the substrate (25 DEG C) was +48 mu m. After the wire bonding step, the substrate (25 DEG C) after cooling the substrate to 25 DEG C still had a concavely warped shape (smile warp). Also in the semiconductor device, the substrate was in a state of smoothing warp bent in a concave shape, and the warp of the substrate in the semiconductor device was +113 탆.

Table 1 shows the evaluation results.

In Examples 1 to 3 and Comparative Examples 1 to 3, all of the substrates in the semiconductor device were smile warped, but in Examples 1 to 3, the warpage of the substrate in the semiconductor device was reduced as compared with Comparative Examples 1 to 3 . It has also been found that the reliability of the semiconductor device is thereby improved.

In Examples 1 to 3, the volume occupied ratio A of the fibrous substrate in the region from the center face of the substrate to the semiconductor element mounting face is smaller than the volume occupancy A of the fibrous substrate in the region from the center face of the substrate to the surface opposite to the semiconductor element mounting face. Is higher than the volume occupancy rate B of the fiber base layer. Thus, when the semiconductor element is mounted on the substrate, the element mounting surface side of the substrate is prevented from being softened, and the semiconductor element can be mounted at a desired position of the substrate.

On the other hand, in Comparative Examples 1 to 3, when the semiconductor element was mounted on the substrate, the element mounting surface side of the substrate tends to be softened, and it was difficult to mount the semiconductor element at a desired position of the substrate.

Figure pct00014

Figure pct00015

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-112134, filed May 16, 2012, the disclosure of which is incorporated herein by reference in its entirety.

Claims (12)

A substrate;
A semiconductor element mounted on the substrate,
And an encapsulating material which is provided on the substrate and is made of a thermosetting resin composition and encapsulates the semiconductor element,
Wherein the substrate comprises at least one fiber substrate layer and a resin layer impregnated in the fiber substrate layer,
The volume occupied rate A of the fibrous substrate layer in the region from the center of the substrate in the thickness direction to the semiconductor element mounting surface is preferably from the center in the thickness direction of the substrate to the surface opposite to the semiconductor element mounting surface The volume occupied rate B of the fibrous substrate layer in the region of < RTI ID = 0.0 >
The method according to claim 1,
Wherein the substrate has a core layer comprising the fiber substrate layer and the resin layer impregnated in the fiber substrate layer,
Wherein the core layer has a volume occupied rate of the fiber base layer in a region from a center in the thickness direction of the core layer to a surface of the core layer on the side of the semiconductor element mounting surface of the substrate,
Wherein a volume occupied rate of the fibrous substrate layer in a region from a center of the core layer in the thickness direction to a back surface opposite to the surface of the core layer is higher than a volume occupied rate of the fibrous substrate layer.
The method according to claim 1 or 2,
A / B is 1.2 or more.
The method according to any one of claims 1 to 3,
Wherein the average coefficient of linear expansion? Of the sealing material at 50 占 폚 to 70 占 폚 and? -??????????????????????????????????????????????????????????????????????????????????????????? wherein ?-? Lt; / RTI >
The method of claim 4,
The average coefficient of linear expansion? Of the substrate in the in-plane direction of the substrate at 50 ° C to 70 ° C is 1 ppm / ° C or more and 25 ppm /
Wherein the encapsulant has an average coefficient of linear expansion? At 50 占 폚 to 70 占 폚 of 8 ppm / 占 폚 or more and 25 ppm / 占 폚 or less.
The method according to any one of claims 1 to 5,
In a plan view, the substrate is larger than the semiconductor element,
A semiconductor device in which a semiconductor element and a substrate are wire-bonded.
A step of mounting a semiconductor element on a substrate,
Curing the sealing material made of the thermosetting resin composition and sealing the semiconductor element
/ RTI >
The substrate comprising at least one fiber substrate layer and a resin layer impregnated in the fiber substrate layer,
The volume occupancy A of the fibrous substrate layer in a region from the center of the substrate in the thickness direction to the semiconductor element mounting surface is set so that the volume occupancy A of the fiber substrate layer from the center in the thickness direction of the substrate to the surface opposite to the semiconductor element mounting surface The volume occupied rate B of the fibrous substrate layer in the region.
The method of claim 7,
A / B is 1.2 or more.
The method according to claim 7 or 8,
In the step of mounting the semiconductor element,
Preparing the substrate, which is warped in a convex shape toward the side where the semiconductor element is mounted, at 25 占 폚;
And a step of mounting the semiconductor element on the substrate.
The method of claim 9,
After the semiconductor element is mounted on the substrate, the step of sealing the semiconductor element with an encapsulating material,
Wherein the substrate is bent in a convex form toward the semiconductor element.
The method according to any one of claims 7 to 10,
In the semiconductor device after the step of sealing the semiconductor element,
Wherein the substrate is formed in a flat shape or in a convex shape toward the opposite side to the side on which the semiconductor element is mounted.
The method according to any one of claims 7 to 11,
After the step of sealing the semiconductor element,
Wherein the average coefficient of linear expansion? Of the sealing material at 50 占 폚 to 70 占 폚 and? -??????????????????????????????????????????????????????????????????????????????????????????? wherein ?-? Or less.
KR1020147034961A 2012-05-16 2013-05-13 Semiconductor device and semiconductor device manufacturing method KR20150008489A (en)

Applications Claiming Priority (3)

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JP2012112134A JP2013239610A (en) 2012-05-16 2012-05-16 Semiconductor device and manufacturing method of the same
PCT/JP2013/003029 WO2013172008A1 (en) 2012-05-16 2013-05-13 Semiconductor device and semiconductor device manufacturing method

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