KR20150007547A - Method of fabricating vertical GaN transister - Google Patents

Method of fabricating vertical GaN transister Download PDF

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KR20150007547A
KR20150007547A KR1020130081623A KR20130081623A KR20150007547A KR 20150007547 A KR20150007547 A KR 20150007547A KR 1020130081623 A KR1020130081623 A KR 1020130081623A KR 20130081623 A KR20130081623 A KR 20130081623A KR 20150007547 A KR20150007547 A KR 20150007547A
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South Korea
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layer
gan
gallium nitride
forming
pattern
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KR1020130081623A
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Korean (ko)
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모토노부 타케야
이관현
곽준식
정영도
이강녕
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서울반도체 주식회사
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Priority to KR1020130081623A priority Critical patent/KR20150007547A/en
Priority to EP14152839.8A priority patent/EP2765611A3/en
Priority to US14/177,825 priority patent/US9219137B2/en
Priority to JP2014024947A priority patent/JP2014154887A/en
Priority to CN201410049097.5A priority patent/CN103985742A/en
Publication of KR20150007547A publication Critical patent/KR20150007547A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method of fabricating a vertical GaN transistor includes: a step of forming a mask layer pattern on a first GaN layer, a step of forming a second GaN layer on the first GaN layer exposed by the mask layer pattern, a step of forming a third GaN layer on the second GaN layer, a step of forming a forth GaN layer on the third GaN layer, a step of forming a current blocking layer pattern on the forth GaN layer, a step of forming a fifth GaN layer on the exposed surface of the forth GaN layer and the current blocking layer pattern, and a step of forming a sixth GaN layer on the fifth GaN layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a vertical GaN transistor,

The present invention relates to a method of manufacturing a transistor, and more particularly, to a method of manufacturing a vertical type gallium nitride transistor.

BACKGROUND ART [0002] With the development of information and communication technologies, there is an increasing demand for high-voltage transistors operating in a high-speed switching environment or a high-voltage environment. Recently, the gallium nitride transistor appeared to be capable of high-speed switching operation as compared with the conventional silicon-based transistor, and thus it is not only suitable for ultra-high speed signal processing but also has advantages of being applicable to a high voltage environment through high- It is getting attention. Particularly, in the case of a high electron mobility transistor (HEMT) using gallium nitride, the mobility of electrons is improved by using a two-dimensional electron gas (2DEG) generated at the interface between dissimilar materials (mobility) can be increased, which is advantageous for high-speed signal transmission.

Such a gallium nitride transistor generally has a horizontal structure in which carriers move in the horizontal direction. However, in the case of a horizontal gallium nitride transistor, a phenomenon occurs in which a flow of a carrier moving through a channel is disturbed by an electric field formed on a surface, and an electric field is concentrated on a corner of a gate electrode at the time of device operation, There has been a problem in that the ruggedness of the resin is deteriorated.

Accordingly, a vertical type gallium nitride transistor in which a carrier moves vertically has been recently proposed. For example, a current aperture vertical electron transistor (CAVET) is disclosed in U.S. Patent Publication No. 2012-0319127 . According to this current-aperture vertical electron transistor (CAVET), the source electrode and the drain electrode are disposed so as to face each other in the vertical direction, and a p-type gallium nitride (p-GaN) layer is disposed therebetween as a current barrier layer. And the current flows vertically from the source electrode to the drain electrode through an aperture provided by a p-type gallium nitride (p-GaN) layer.

In order to manufacture such a vertical gallium nitride transistor, a process of epitaxially growing a gallium nitride (GaN) layer is required. For example, a gallium nitride (GaN) layer is formed on a large lattice (MOCVD) on a c-plane sapphire substrate in spite of the thermal stability and parameters and thermal coefficient mismatches. However, high density crystal defects such as threading dislocations (TD) are generated in the vertical direction in the growth direction due to the difference in lattice constant between the sapphire substrate and the sapphire substrate in the gallium nitride (GaN) layer formed in this process. These threading dislocations (DT) act as nonradiative recombination centers and act as charged scattering centers and are known to affect the mobility of carriers. Particularly, in the case of a gallium nitride transistor having a vertical channel, the threading dislocations DT are formed along the vertical direction in which the carriers are moved, thereby causing a significant reduction in the reliability of the device.

A problem to be solved by the present application is to provide a method of manufacturing a vertical gallium nitride transistor which can improve the reliability of a device by minimizing the density of the threading dislocations.

A method of fabricating a vertical gallium nitride (GaN) transistor according to an example includes forming a mask layer pattern on a first gallium nitride (GaN) layer, forming a first gallium nitride Forming a second gallium nitride (GaN) layer over the first gallium nitride (GaN) layer; forming a third gallium nitride (GaN) layer over the second gallium nitride (GaN) Forming a current blocking layer pattern on the fourth gallium nitride (GaN) layer; forming a current blocking layer pattern and a fourth gallium nitride (GaN) layer on the GaN layer; Forming a fifth gallium nitride (GaN) layer on the exposed surface of the first gallium nitride (GaN) layer, and forming a sixth gallium nitride (GaN) layer on the fifth gallium nitride (GaN) layer.

According to the present application, the growth of the fourth gallium nitride (GaN) layer in the drift region corresponding to the vertical movement direction of the carrier is mainly performed in the horizontal direction, so that the penetration potential in the vertical direction RTI ID = 0.0 > DT) < / RTI > In addition, since the etching process for the third gallium nitride (GaN) layer as the channel layer in contact with the gate insulating layer pattern in the manufacturing process is eliminated, the interface state between the gate insulating layer pattern and the third gallium nitride (GaN) The advantage is also provided.

FIGS. 1 to 14 are cross-sectional views illustrating a method of manufacturing a vertical type gallium nitride transistor according to an example embodiment.

Referring to FIG. 1, a first gallium nitride (GaN) layer 104 is formed as a sacrificial layer on a first substrate 102. The first substrate 102 is a growth substrate for growing a first gallium nitride (GaN) layer 104. In one example, the first substrate 102 is a sapphire substrate. The formation of the first gallium nitride (GaN) layer can be performed by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE) ). ≪ / RTI > In one example, the first gallium nitride (GaN) layer 104 has an n + type conductivity type. Next, a mask layer pattern 106 is formed on the first gallium nitride (GaN) layer 104. The mask layer pattern 106 is a mask for epitaxial lateral overgrowth (ELO), and is formed, for example, in a silicon oxide layer pattern. The mask layer pattern 106 has openings 107 that expose some surfaces of the first gallium nitride layer (GaN) layer 104.

Referring to FIG. 2, a second gallium nitride (GaN) layer 108 is grown over the exposed surface of a first gallium nitride (GaN) layer 104. In one example, the second gallium nitride (GaN) layer 108 is formed in an undoped state without dopant doping. The second gallium nitride (GaN) layer 108 begins to grow vertically from the exposed surface of the first gallium nitride (GaN) layer 104. After the second GaN layer 108 has grown to a height above the height of the upper surface of the mask layer pattern 106, the second GaN layer 108 begins to grow in the horizontal direction along the upper surface of the mask layer pattern 106. The growth of the second gallium nitride (GaN) layer 108 is performed until a portion of the upper surface of the mask layer pattern 106 is exposed. Thus, the second gallium nitride (GaN) layer 108 has an opening 109 that exposes a portion of the surface of the mask layer pattern 106.

Referring to FIG. 3, a third gallium nitride (GaN) layer 110 is grown over a second gallium nitride (GaN) layer 108. The third gallium nitride (GaN) layer 110 has a p-type conductivity type as a current barrier layer and a channel layer. As the dopant, boron (B), arsenic (As), phosphorus (P), magnesium (Mg) and the like can be used. The third gallium nitride (GaN) layer 110 is grown not only vertically from the upper surface of the second gallium nitride (GaN) layer 108 but also horizontally from the lateral side, A third gallium nitride (GaN) layer 110 is formed over the mask layer pattern 106. The growth of the third gallium nitride (GaN) layer 110 is such that the upper surface of the mask layer pattern 106 is partially exposed. Next, a fourth gallium nitride (GaN) layer 112 is grown on a third gallium nitride (GaN) layer 110. The fourth gallium nitride (GaN) layer 112 acts as a part of the drift layer. In one example, the fourth gallium nitride (GaN) layer 112 has an n-type conductivity. The fourth gallium nitride (GaN) layer 112 is grown not only vertically from the top surface of the third gallium nitride (GaN) layer 110 but also horizontally from the lateral surface, And covers the entire exposed surface of the mask layer pattern 106. In particular, the region indicated by "A" in the figure corresponds to the movement path of the carrier in the vertical direction in which the fourth gallium nitride (GaN) layer 112 grows mainly in the horizontal direction, The generation of the threading dislocations DT in the vertical direction in the region is suppressed.

Referring to FIG. 4, a current blocking layer pattern 114 is formed on a fourth gallium nitride (GaN) layer 112. In one example, the current blocking layer pattern 114 is formed of a silicon oxide layer. In another example, the current blocking layer pattern 114 may be formed as a p-type semiconductor layer pattern. The current blocking layer pattern 114 has openings 115 that expose some surfaces of the fourth gallium nitride (GaN) layer 112. The current blocking layer pattern 114 is formed along the direction perpendicular to the region where the source electrode layer is formed in the subsequent process, that is, the region where the second gallium nitride (GaN) layer 108 is disposed between the mask layer patterns 106 So that they are disposed at positions where they overlap each other.

Referring to FIG. 5, a fifth gallium nitride (GaN) layer 116 is formed on a fourth gallium nitride (GaN) layer 112. The fifth gallium nitride (GaN) layer 116 begins to grow vertically from the exposed surface of the fourth gallium nitride (GaN) layer 112. After the second gallium nitride (GaN) layer 108 has grown to a height above the height of the top surface of the current blocking layer pattern 114, it begins to grow in the horizontal direction along the top surface of the current blocking layer pattern 114, And covers the entire upper surface of the barrier layer pattern 114. In one example. The fifth gallium nitride (GaN) layer 116 has an n-type conductivity. The fifth gallium nitride (GaN) layer 116 acts as a drift layer with the fourth gallium nitride (GaN) layer 112. Next, a sixth gallium nitride (GaN) layer 118 is formed on the fifth gallium nitride (GaN) layer 116. The sixth gallium nitride (GaN) layer 118 has an n + type conductivity type.

Referring to FIG. 6, a drain electrode layer 120 is formed on a sixth gallium nitride (GaN) layer 118. The drain electrode layer 120 may be formed of a metal layer. Next, the second substrate 122 is attached onto the drain electrode layer 120. The second substrate 122 is a supporting substrate for supporting the device, and is made of silicon (Si) or metal in one example. After attaching the second substrate 122, the first substrate 102 is removed. In one example, removal of the first substrate 102 is performed using a laser lift-off (LLO) method. Specifically, laser is irradiated from the lower surface of the first substrate 102, as indicated by arrows in the drawing. The irradiated laser is irradiated to the lower surface of the first gallium nitride (GaN) layer 104 through the first substrate 102. The lower portion 104 'of the first gallium nitride (GaN) layer 104 is expanded and damaged by a laser shock wave by the laser irradiation, and the first gallium nitride (GaN) layer 104 The first substrate 102 is separated from the first gallium nitride (GaN) layer 104 in a lift-off manner by the damage 104 'of the first substrate 102'.

Referring to FIG. 7, the resultant structure described with reference to FIG. 6 is rotated 180 degrees so that the second substrate 122 is positioned at the bottom and the first gallium nitride (GaN) layer 104 is positioned at the top. Next, the first gallium nitride (GaN) layer 104 is removed. Removal of the first gallium nitride (GaN) layer 104 may be performed using an anisotropic etching process, for example, a reactive ion etching (RIE) method as indicated by the arrow in the figure. The surface of the mask layer pattern 106 is exposed as the first gallium nitride (GaN) layer 104 is removed and the second gallium nitride (GaN) layer 108 between the mask layer patterns 106 Is also exposed.

Referring to FIG. 8, the mask layer pattern 106 on which the surface is exposed is removed. When the mask layer pattern 106 is formed of a silicon oxide layer, the mask layer pattern 106 can be removed through a normal oxide film removing process. As the mask layer pattern 106 is removed, a recess 125 is created. A portion of the surface of the second gallium nitride (GaN) layer 108 and a portion of the surface of the third gallium nitride (GaN) layer 110 are exposed at the bottom of the recess 125, and a third gallium nitride ) Layer 110 is exposed on one surface of the fourth gallium nitride (GaN)

Referring to FIG. 9, a gate insulating layer 127 is formed on the front surface. Next, an etching mask layer pattern 130 for performing patterning with respect to the gate insulating layer 127 is formed on the gate insulating layer 127. In one example, the etch mask layer pattern 130 may be formed of a photoresist layer. The etching mask layer pattern 130 has openings 131 that expose a part of the surface of the gate insulating layer 127. The positions where the openings 131 are disposed overlap with the positions where the source electrodes are disposed in the subsequent process and overlap with the positions where the current blocking layer patterns 114 are disposed.

Referring to FIG. 10, etching using the etching mask layer pattern 130 is performed to remove exposed portions of the gate insulating layer 127 and exposed portions of the second gallium nitride (GaN) layer 108 to a certain depth . The gate insulating layer pattern 128 is formed by this etching. Optionally, the etch may be performed until a portion of the surface of the third gallium nitride (GaN) layer 110 is exposed. After the above etching is performed, the etching mask layer pattern 130 is removed. When the etching mask layer pattern 130 is formed of a photoresist layer, the etching mask layer pattern 130 can be removed through a conventional photoresist layer removing process, for example, an ashing process. After the etching mask layer pattern 130 is removed, an activation process is performed on the third gallium nitride (GaN) layer 110 used as a channel layer. In one example, the activation process is conducted at a temperature condition of approximately 600 < 0 > C in an N2 atmosphere for approximately 20 minutes. In another example, the activation process may be performed by laser irradiation of the third gallium nitride (GaN) layer 110.

Referring to FIG. 11, a lift-off mask layer pattern 132 is formed on the gate insulating layer pattern 128. In one example, the lift-off mask layer pattern 132 may be formed of a photoresist layer. The lift-off mask layer pattern 132 has a first opening 133-1 and a second opening 133-2. A part of the surface of the gate insulating layer pattern 128 is exposed by the first opening 133-1. A part of the surface of the second gallium nitride (GaN) layer 108 is exposed by the second opening 133-2. The first opening 133-1 and the second opening 133-2 are arranged alternately.

Referring to FIG. 12, a metal layer 135 is formed on the entire surface. The metal layer 135 is formed on the exposed surface of the second gallium nitride (GaN) layer 108, on the top surface of the lift-off mask layer pattern 132, and on the exposed surface of the gate insulating layer pattern 128 do. The metal layer 135 formed on the exposed surface of the second gallium nitride (GaN) layer 108 serves as the source electrode layer. The metal layer 137 formed on the exposed surface of the gate insulating layer pattern 128 acts as a gate electrode layer.

Referring to FIG. 13, the lift-off mask layer pattern 132 is removed. When the lift-off mask layer pattern 132 is formed of a photoresist layer, the lift-off mask layer pattern 132 can be removed through a conventional photoresist layer removing process, for example, an ashing process . As the lift-off mask layer pattern 132 is removed, the metal layer 135 thereon is also removed. The remaining metal layer on the second gallium nitride (GaN) layer 108 becomes the source electrode layer 138 and the remaining metal layer on the gate insulating layer pattern 128 becomes the gate electrode layer 136.

Referring to FIG. 14, a passivation layer 140 is formed on the entire surface so that the source electrode layer 138 and the gate electrode layer 136 are covered. In one example, the passivation layer 140 may be formed of an oxide layer or a nitride layer. Next, a via hole 143 is formed through the passivation layer 140 to expose a part of the surface of the source electrode layer 138. In this process, a via hole that exposes a part of the surface of the gate electrode layer 136 through the passivation layer 140 may be formed together, or may be formed through a separate process, although not shown in the figure. Next, a wiring layer 145 is formed by filling the via hole with a metal layer.

The first region B indicated by "B" in the drawing is a region acting as a carrier movement path between the drain electrode 120 and the source electrode 138, while a second region " C is a region in which carrier movement between the drain electrode 120 and the source electrode 138 is blocked by the current blocking layer pattern 114. [ The GaN-based transistor fabricated in accordance with this example has a structure in which a portion of the fourth gallium nitride (GaN) layer 112, which acts as a carrier movement path between the drain electrode 120 and the source electrode 138, 1 region B so that the formation of the threading dislocations DT in the vertical direction is suppressed in this process. Therefore, a phenomenon that an abnormal leakage current flows between the drain electrode 120 and the source electrode 138 due to the threading dislocation DT in the vertical direction is also prevented.

102 ... First substrate 104 ... First gallium nitride (GaN) layer
106 ... Mask layer pattern 108 ... Second gallium nitride (GaN) layer
110 ... a third gallium nitride (GaN) layer 112 ... a fourth gallium nitride (GaN) layer
114 ... current blocking layer pattern 116 ... fifth gallium nitride (GaN) layer
118 ... Sixth gallium nitride (GaN) layer 120 ... Drain electrode layer
122 ... second substrate 128 ... gate insulating layer pattern
130 ... Etch mask layer pattern 132 ... Lift-off mask layer pattern
135 ... metal layer 136 ... gate electrode layer
138 ... Source electrode layer 140 ... Passivation layer
143 ... via hole 145 ... wiring layer

Claims (20)

Forming a mask layer pattern on the first gallium nitride (GaN) layer;
Forming a second gallium nitride (GaN) layer on the first gallium nitride (GaN) layer exposed by the mask layer pattern;
Forming a third gallium nitride (GaN) layer over the second gallium nitride (GaN) layer;
Forming a fourth gallium nitride (GaN) layer on the third gallium nitride (GaN) layer;
Forming a current blocking layer pattern on the fourth gallium nitride (GaN) layer;
Forming a fifth gallium nitride (GaN) layer on the exposed surface of the current blocking layer pattern and the fourth gallium nitride (GaN) layer; And
And forming a sixth gallium nitride (GaN) layer on the fifth gallium nitride (GaN) layer. The method according to claim 1,
Wherein the mask layer pattern is formed of a silicon oxide layer. The method according to claim 1,
Wherein the second gallium nitride (GaN) layer is formed as an undoped layer, the third gallium nitride (GaN) layer is formed as a p-type conductivity, and the fourth gallium nitride (GaN) A method of manufacturing a vertical type gallium nitride (GaN) transistor formed in a conductive type. The method according to claim 1,
The formation of the second gallium nitride (GaN) layer and the formation of the third gallium nitride (GaN) layer may be performed using a vertical gallium nitride (GaN) < / RTI > 5. The method of claim 4,
Wherein the formation of the third gallium nitride (GaN) layer is performed such that a portion of the surface of the mask layer pattern is exposed. 6. The method of claim 5,
The formation of the fourth gallium nitride (GaN) layer may be performed using a vertical gallium nitride (GaN) layer, which is performed to grow in a horizontal direction on the exposed surface of the mask layer pattern exposed by the third gallium nitride GaN) < / RTI > The method according to claim 1,
Wherein the current blocking layer pattern is formed of a silicon oxide layer. The method according to claim 1,
The formation of the current blocking layer pattern may be performed by using a vertical gallium nitride (GaN) layer, which is performed so as to be disposed at a position overlapping with the region where the second gallium nitride (GaN) ) A method of manufacturing a transistor. The method according to claim 1,
Wherein the fifth gallium nitride (GaN) layer has an n-type conductivity and the sixth gallium nitride (GaN) layer has an n + -type conductivity type. The method according to claim 1,
Further comprising forming the first gallium nitride (GaN) layer on the first substrate. 11. The method of claim 10,
Wherein the first substrate is a sapphire substrate. 11. The method of claim 10,
Forming a drain electrode layer on the sixth gallium nitride (GaN) layer;
Forming a second substrate on the drain electrode layer;
Removing the first substrate;
Removing the first gallium nitride (GaN) layer;
Removing the exposed mask layer pattern by removal of the first gallium nitride (GaN) layer to form a recess;
Forming a gate insulating layer pattern in an area where the recess is located, wherein a part of the surface of the second gallium nitride (GaN) layer is exposed between the gate insulating layer patterns; And
And forming a gate electrode layer and a source electrode layer on the exposed surfaces of the gate insulating layer pattern and the second gallium nitride (GaN) layer, respectively. 13. The method of claim 12,
Wherein the removing of the first substrate is performed using a laser lift-off (LLO) method. 13. The method of claim 12,
Wherein the first gallium nitride (GaN) layer is removed using a reactive ion etching method. 13. The method of claim 12,
Wherein forming the gate insulating layer pattern comprises:
Forming a gate insulating layer on the entire surface of the recessed resultant;
Forming an etch mask layer pattern covering the recess region on the gate insulating layer;
Forming a gate insulating layer pattern by removing the gate insulating layer exposed by the etching mask layer pattern;
Removing a second gallium nitride (GaN) layer exposed by removal of the gate insulating layer to a certain depth; And
And removing the etch mask layer pattern. ≪ Desc / Clms Page number 20 > 16. The method of claim 15,
And performing an activation process for the third gallium nitride (GaN) layer after removing the etch mask layer pattern. ≪ Desc / Clms Page number 20 > 17. The method of claim 16,
Wherein the activation process for the third gallium nitride layer is performed by annealing in an N2 atmosphere. 17. The method of claim 16,
Wherein the activating process for the third gallium nitride layer is performed by irradiating a laser. 13. The method of claim 12,
Wherein forming the gate electrode layer and the source electrode layer comprises:
Forming a lift-off mask layer pattern on the gate insulating layer pattern;
Forming a metal layer on the gate insulating layer pattern between the lift-off mask layer patterns, on the exposed surface of the second gallium nitride (GaN) layer, and on the upper surface of the lift-off mask layer pattern; ; And
And removing the lift-off mask layer pattern to remove the metal layer on the lift-off mask layer pattern so that the metal layer remaining on the gate insulating layer pattern and the metal layer remaining on the second gallium nitride (GaN) layer Wherein the metal layer remaining on the exposed surface is used as a gate electrode layer and a source electrode layer, respectively. 13. The method of claim 12,
Forming a passivation layer covering the gate electrode layer and the source electrode layer;
Forming a via hole exposing the gate electrode layer and / or the source electrode layer through the passivation layer; And
And filling the via hole with a metal layer to form a wiring layer.
KR1020130081623A 2013-02-12 2013-07-11 Method of fabricating vertical GaN transister KR20150007547A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020130081623A KR20150007547A (en) 2013-07-11 2013-07-11 Method of fabricating vertical GaN transister
EP14152839.8A EP2765611A3 (en) 2013-02-12 2014-01-28 Vertical gallium nitride transistors and methods of fabricating the same
US14/177,825 US9219137B2 (en) 2013-02-12 2014-02-11 Vertical gallium nitride transistors and methods of fabricating the same
JP2014024947A JP2014154887A (en) 2013-02-12 2014-02-12 Vertical gallium nitride transistors and method for manufacturing the same
CN201410049097.5A CN103985742A (en) 2013-02-12 2014-02-12 Vertical gallium nitride transistors and methods of fabricating the same

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