KR20140141535A - 디펜던시 문제의 효율적인 병렬 계산 - Google Patents

디펜던시 문제의 효율적인 병렬 계산 Download PDF

Info

Publication number
KR20140141535A
KR20140141535A KR20140067227A KR20140067227A KR20140141535A KR 20140141535 A KR20140141535 A KR 20140141535A KR 20140067227 A KR20140067227 A KR 20140067227A KR 20140067227 A KR20140067227 A KR 20140067227A KR 20140141535 A KR20140141535 A KR 20140141535A
Authority
KR
South Korea
Prior art keywords
execution
sequence
logic
computing task
sid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR20140067227A
Other languages
English (en)
Korean (ko)
Inventor
세이 미즈라치
우리 탈
토머 벤데이비드
이샤이 겔러
이도 카세르
로넨 갈
Original Assignee
로케틱 테크놀로지즈 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/907,922 external-priority patent/US9032377B2/en
Application filed by 로케틱 테크놀로지즈 리미티드 filed Critical 로케틱 테크놀로지즈 리미티드
Publication of KR20140141535A publication Critical patent/KR20140141535A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/45Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/443Optimisation
    • G06F8/4441Reducing the execution time required by the program code
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/48Indexing scheme relating to G06F9/48
    • G06F2209/483Multiproc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)
KR20140067227A 2013-06-02 2014-06-02 디펜던시 문제의 효율적인 병렬 계산 Withdrawn KR20140141535A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/907,922 2013-06-02
US13/907,922 US9032377B2 (en) 2008-07-10 2013-06-02 Efficient parallel computation of dependency problems

Publications (1)

Publication Number Publication Date
KR20140141535A true KR20140141535A (ko) 2014-12-10

Family

ID=51418264

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20140067227A Withdrawn KR20140141535A (ko) 2013-06-02 2014-06-02 디펜던시 문제의 효율적인 병렬 계산

Country Status (4)

Country Link
KR (1) KR20140141535A (https=)
CN (1) CN104216685A (https=)
IL (1) IL232836A0 (https=)
IN (1) IN2014CH02634A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105988952B (zh) * 2015-02-28 2019-03-08 华为技术有限公司 为内存控制器分配硬件加速指令的方法和装置
CN112445587A (zh) * 2019-08-30 2021-03-05 上海华为技术有限公司 一种任务处理的方法以及任务处理装置
CN111738703B (zh) * 2020-05-29 2023-06-02 中国科学院计算技术研究所 一种加速安全散列算法的加速器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4783005B2 (ja) * 2004-11-25 2011-09-28 パナソニック株式会社 プログラム変換装置、プログラム変換実行装置およびプログラム変換方法、プログラム変換実行方法。
US7509244B1 (en) * 2004-12-22 2009-03-24 The Mathworks, Inc. Distributed model compilation
US7760743B2 (en) * 2006-03-06 2010-07-20 Oracle America, Inc. Effective high availability cluster management and effective state propagation for failure recovery in high availability clusters
JP4936517B2 (ja) * 2006-06-06 2012-05-23 学校法人早稲田大学 ヘテロジニアス・マルチプロセッサシステムの制御方法及びマルチグレイン並列化コンパイラ
GB2443277B (en) * 2006-10-24 2011-05-18 Advanced Risc Mach Ltd Performing diagnostics operations upon an asymmetric multiprocessor apparatus
US8286196B2 (en) * 2007-05-03 2012-10-09 Apple Inc. Parallel runtime execution on multiple processors
KR101607495B1 (ko) * 2008-07-10 2016-03-30 로케틱 테크놀로지즈 리미티드 디펜던시 문제의 효율적인 병렬 계산
CN103034534A (zh) * 2011-09-29 2013-04-10 阿尔斯通电网公司 基于网格计算的电力系统分析并行计算方法和系统

Also Published As

Publication number Publication date
IL232836A0 (en) 2014-08-31
CN104216685A (zh) 2014-12-17
IN2014CH02634A (https=) 2015-07-10

Similar Documents

Publication Publication Date Title
KR101607495B1 (ko) 디펜던시 문제의 효율적인 병렬 계산
US9684494B2 (en) Efficient parallel computation of dependency problems
US10509876B2 (en) Simulation using parallel processors
JP2011527788A5 (https=)
US20030188299A1 (en) Method and apparatus for simulation system compiler
US20040154002A1 (en) System & method of linking separately compiled simulations
US11023642B2 (en) Event-driven design simulation
US8473934B2 (en) Method for mapping applications on a multiprocessor platform/system
US12554916B2 (en) Method to avoid memory bank conflicts and pipeline conflicts in tensor memory layout
US9053272B2 (en) Method and apparatus of hardware acceleration of EDA tools for a programmable logic device
Tan et al. Multithreaded pipeline synthesis for data-parallel kernels
US10747930B2 (en) Event-driven design simulation
KR20140141535A (ko) 디펜던시 문제의 효율적인 병렬 계산
US10789405B2 (en) Event-driven design simulation
US10565335B2 (en) Event-driven design simulation
Rohde et al. Improving HLS generated accelerators through relaxed memory access scheduling
Neele GPU implementation of partial-order reduction
Sheikhha Task Scheduling Techniques to Accelerate RTL Simulation
Elsabbagh Accelerating RTL Simulation Through Fine-grained Task Dataflow and Selective Execution
Andersson et al. Automatic local memory architecture generation for data reuse in custom data paths
Turkington et al. Co-optimisation of datapath and memory in outer loop pipelining

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000