KR20140140291A - Display device and display method - Google Patents

Abstract

The present invention relates to a display device using an organic electroluminescent device as a light emitting device. The display device includes a plurality of pixel circuits (Px(i,j)) of n rows and m columns. Wherein, m and n are natural numbers. The pixel circuits are formed with a unit of a pair of pixel circuits composed of an odd row pixel circuit (Pxodd(i,j)) and an even row pixel circuit (Pxeven(i,j)) which are adjacent in a row direction and share a gate line (Lgi) to apply a row selection signal to each pixel circuit. A gradation signal (Vdata) of each column unit is applied to the odd row pixel circuit through an odd data line (Ldjodd). The gradation signal of each column unit is applied to the even row pixel circuit through an even data line (Ldjeven).

Description

DISPLAY DEVICE AND DISPLAY METHOD [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a display method, and more particularly to an organic light emitting display device and a display method using the organic electroluminescent device as a light emitting device.

An organic electroluminescent device (hereinafter referred to as " organic EL device ") has a structure in which an organic light emitting layer containing an organic compound is inserted between a pair of electrodes formed of a positive electrode and a negative electrode formed on a transparent substrate such as glass, Holes and electrons are injected into the organic light emitting layer from the pair of electrodes to recombine the excitons to emit excitons to emit light when the excitons lose their activity, Emitting device.

An organic electroluminescent display device using the organic electroluminescent device as a light emitting device (hereinafter sometimes simply referred to as " organic electroluminescent display device ") is lightweight and thin and has excellent brightness and viewing angle characteristics Has attracted attention as a next generation flat panel display device.

FIG. 1 is a diagram illustrating the configuration of a driving unit of a conventional organic light emitting display device.

1 (a), a conventional organic light emitting diode display device 1 includes a plurality of pixel circuits 11 (i, j) (i = 1 to n, j = 1 to m , a gate driver (row selection driver) 12, a data driver 14, a controller 15, and an anode driver (not shown).

1 (b), each pixel circuit 11 (i, j) corresponds to each pixel of the image, and each pixel circuit 11 (i, j) Two transistors T11 and T12, and a capacitor C1.

The gate driver 12 sequentially outputs the high level output signal OUT [k] to the gate lines Lg1, Lg2, ..., Lgn under the control of the controller 15, (N, 1) to 11 (n, m) are sequentially selected and the data driver 14 selects (1, 1) to 11 (1, m), 11 (2,1) to 11 (2, m) by applying the gradation signals based on the pixel data to the data lines Ld1 to Ldm, , 11 (n, 1) to 11 (n, m)).

When the writing is completed in this manner, the controller 15 controls the unillustrated anode driver so that the anode driver supplies the anode voltage signals VDD (1) to VDD (n) at the high level to the anode lines La ) To La (n), whereby the transistor T12 of the pixel circuit 11 (i, j) uses the voltage held by each capacitor C1 as the gate voltage, and outputs the gate voltage Vgs And supplies a corresponding current to the organic EL element 101 to emit light.

However, in the OLED display 1 of FIG. 1, one gate line per row unit and one data line per column unit are formed, and each pixel circuit is formed at a position where the gate line and the data line cross each other.

Therefore, for example, when the organic light emitting display device is a display device having a resolution of VGA (640 x 480), 640 gate lines are required. In the case of a display device having a resolution of HD (1280 x 720), 1280 Gate lines are required.

In FIG. 1, for convenience of description, each driver including a controller is not shown as being arranged at the right and left sides of a display unit composed of a plurality of pixel circuits, but in an actual display device, And the various drivers including the controller are respectively disposed in the lower part of the rectangular bezel in the form of IC or the like and the gate line and each anode line are drawn out from the IC And extend in the row direction through the left and right side bezels, and the data lines extend from the IC in the vertical direction of the display portion.

Therefore, the width of the display device bezel becomes wider as the number of various lines including the gate line increases, and the parasitic capacitance generated at the intersection of the gate line and the data line crosses the so-called RC delay and voltage drop The number of lines constituting the various lines including the gate line should be as small as possible. In order to reduce the number of lines connecting the IC and each pixel circuit, two or more pixels A method in which two rows of pixels share one gate line or a method in which two rows of pixels share one data line can be considered.

A display device described in Patent Document 1 is known as a method in which pixels of two columns share one data line.

2 is a circuit diagram showing a schematic configuration of a conventional organic light emitting diode display device described in Patent Document 1. In FIG.

2A, the organic light emitting diode display of Patent Document 1 includes a plurality of selection gate lines S1-Sn, a plurality of light emission gate lines Em11-Em1n, Em21-Em2n, and a plurality of data lines And a plurality of unit pixels 110. Each unit pixel 110 includes two sub pixels 111 and 112 arranged in a column direction.

2B, the two sub pixels 111 and 112 formed in one unit pixel share one pixel and the pixel driving part 115, and the pixel driving part 115 is connected to the driving transistor M1, a switching transistor M2 and a capacitor C1.

In addition, the scan driver 200 divides one field into two subfields, sequentially applies a selection signal to a plurality of selection gate lines (S1-Sn) in each subfield, and a plurality The emit signal is sequentially applied to the emit gate lines Em11-Em1n of the first subfield, and the emit signal is sequentially applied to the plurality of emit gate lines Em21-Em2n in the next subfield.

The data driver 300 applies a data signal to the data lines D1 to Dn and applies a data signal corresponding to the subpixel 111 in one subfield and corresponds to the subpixel 112 in the next subfield. The data signal is applied.

In Patent Documents 2 to 5, a plurality of selection gate lines (S1-Sn), a plurality of light emission gate lines (Em11-Em1n, Em21-Em2n), a plurality of data lines (D1-Dm) Each unit pixel 110 includes two sub-pixels 111 and 112 arranged in a column direction, and two sub-pixels formed in each unit pixel are divided into one select gate line and pixel A display device sharing the driver 115 is described.

Patent Document 1: JP-A-2005-0000759 Patent Document 2: Japanese Patent Application Laid-Open No. 2004-0037266 Patent Document 3: Japanese Patent Application Laid-Open No. 2004-0037288 Patent Document 4: Japanese Patent Application Laid-Open No. 2004-0038260 Patent Document 5: Japanese Patent Application Laid-Open No. 2004-0038261

Since the two subpixels formed in each unit pixel share one select gate line and the pixel driver, the description of the above Patent Documents 1 to 5 is based on the fact that one data line Dj, one select gate line Si, A pixel driver 115 including a transistor and a capacitor C1 shares two sub pixels 111 and 112 to thereby constitute a data line Dj and a selection gate line Si and a pixel driver 115 It is possible to reduce the number of transistors and capacitors.

However, since the display devices of Patent Documents 1 to 5 divide each unit pixel 110 into two sub-pixels 111 and 112 arranged in the column direction and drive them separately, Two transistors M3a (Em1-Em1n) connected to the two light-emitting gate lines (Em11-Em1n) and the light-emitting gate lines (Em21-Em2n) need a plurality of gate lines (Em11-Em1n) And M3b. As a result, the number of transistors per unit pixel is the same as the conventional one, and the number of gate lines (gate lines) is rather increased. Therefore, the number of signal lines for supplying signals to each pixel is .

The present invention has been made in view of the above problems, and it is an object of the present invention to reduce the number of gate lines of a display device, thereby reducing the width of a bezel required for an extended arrangement of gate lines, And further to improve the aperture ratio as the gate line decreases and increase the resolution of the panel.

According to an aspect of the present invention, there is provided a display device including a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively), wherein the plurality of pixel circuits are odd A gate line for applying a row selection signal to each of the pair of pixel circuits is shared by a pair of pixel circuits each composed of a row pixel circuit and an even row pixel circuit, And the even-numbered pixel circuits are supplied with the gray-scale signals in units of columns through the even-numbered data lines.

Further, the display device of the present invention is a display device including a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively), and is composed of an odd row pixel circuit and an even row pixel circuit adjacent to each other in the row direction A plurality of pairs of pixel circuits each having a pair of pixel circuits as a unit; a gate line for applying a row selection signal in units of the pair of pixel circuits; and an odd-numbered pixel circuit for applying a gray- Data lines and even-numbered data lines for applying gray-scale signals to the even-numbered row pixel circuits in units of columns.

Wherein each of the plurality of pixel circuits includes: a switching transistor which is driven by a row selection signal applied to the gate line to apply a gradation signal indicative of the gradation of the image data to one end of the capacitor; A first transistor for supplying a current based on a gray-scale signal applied to the first data line, the second data line, or the even-numbered data line to the organic EL element; a capacitor for charging a gray- And may include an organic EL element that emits light.

Wherein the switching transistor has a gate connected to the gate line and a source and a drain form a first current path between either one of the odd data line and the even data line and the gate terminal of the driving transistor and one end of the capacitor , The gate of the driving transistor is connected to one end of the first current path and one end of the capacitor, and the source and the drain form a second current path between the other end of the capacitor and the anode power supply terminal and the organic EL element good.

The display method of the present invention is a display method of a display device including a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively), and includes an odd row pixel circuit and an even row pixel circuit adjacent to each other in the row direction A row selection signal applying step of sequentially applying a row selection signal to a plurality of pairs of pixel circuits having a pair of pixel circuits as a unit; And a second gradation signal application step of applying a gradation signal in units of columns to the selected even-numbered row pixel circuit, wherein in the step of applying the row selection signal, the pair of pixel circuits are connected through one gate line And the row selection signal is applied.

The first gradation signal application step may be a first half pulse period of the entire pulse period of the row selection signal and the second gradation signal application step may be a second half pulse period of the entire pulse period of the row selection signal good.

According to the present invention, a plurality of pixel circuits constituting a display device are divided into a pair of an odd row pixel circuit and an even row pixel circuit adjacent to each other, and a pair of odd row pixel circuits and even row pixel circuits adjacent to each other The number of gate lines can be reduced to one-half (half) as compared with the prior art because one gate line for supplying a row selection signal sequentially applied from the gate driver is shared. Therefore, the width of the bezel of the display device can be greatly reduced by reducing the number of gate lines.

Also, since the number of the intersections at which the gate line intersects the line supplying the other signal in the display device due to the decrease in the number of gate lines is reduced, the parasitic capacitance generated at the intersection also decreases, Delay (RC Delay) and voltage drop (IR Drop) can also be greatly reduced.

In addition, as the gate line decreases, the aperture ratio of the display device increases, thereby increasing the resolution of the display device.

FIG. 1 is a diagram illustrating the configuration of a driving unit of a conventional organic light emitting display device.
2 is a diagram showing a schematic configuration of a conventional organic light emitting diode display.
3 is a diagram showing the configuration of a driving unit of a display device according to a preferred embodiment of the present invention.
4 is a circuit diagram showing a schematic configuration of the pixel circuit of the display device of Fig.
5 is a timing chart showing driving timings of a display apparatus according to a preferred embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a diagram showing the configuration of a driving section of a display apparatus according to a preferred embodiment of the present invention, and FIG. 4 is a circuit diagram showing a schematic configuration of some pixel circuits of the display apparatus of FIG.

3, the display device 10 of the present embodiment includes a plurality of pixel circuits Px (i, j) (i = 1 to n, n, (row selection driver) 12, a data driver 14, a controller 15, and an anode driver (not shown), each of which includes a gate driver (j = 1 to m, m and n are natural numbers).

The display device 10 of the present embodiment is a display device in which a plurality of pixel circuits of n rows and m columns constituting a display unit are constituted by a pair of pixel circuits each constituted by pixel circuits of two rows of odd rows and even rows adjacent to each other (For example, odd-numbered row pixel circuits (Pxodd (1,1 to 1, m)) and even-numbered row pixel circuits (Pxeven m share a gate line Lg1 for applying a row selection signal supplied from the gate driver 12 to each pixel circuit.

A pair of pixel circuits composed of the next pair of odd-numbered pixel circuits (Pxodd (3, 1 to 3, m)) and the even-numbered pixel circuits (Pxeven And the gate line Lg2 for applying the row selection signal to be supplied to each pixel circuit is shared.

A pair of pixel circuit diagrams consisting of the last pair of odd row pixel circuits (Pxodd (n-1,1 to n-1, m)) and the even row pixel circuits (Pxeven (n, 1 to n, m) (Lgn / 2, n is an even number) for applying a row selection signal supplied from the gate driver 12 to each pixel circuit.

 The odd-numbered row pixel circuits Pxodd (i, j) among the pixel circuits Px (i, j) in one column are connected to the data lines for supplying the data signals from the data driver 14 to the respective pixel circuits Px numbered row data line Ldjodd for supplying a data signal to the odd-numbered row pixel circuits Pxeven (i + 1, j), and an even-numbered row data line Ldjeven for supplying the data signal to the even-numbered row pixel circuits Pxeven (i + 1, j).

As described above, in the display device 10 of the present embodiment, one gate line is shared by the pixel circuits of two rows, and the data line has two data lines per pixel circuit of one column. As a result, The number of gate lines is reduced to half (1/2) as compared to the device 1, but the number of data lines is doubled.

The reason for this is that the gate lines extend in the row direction of the pixel circuit through the lower end of the display device 10 and the bezels on both sides and the data lines are arranged on the left and right sides of the display device 10 In order to reduce the bezel width of the display device 10, which is an object of the present invention, in a display device which is arranged so as not to pass through the bezel and extend directly in the column direction of the pixel circuit from the bezel at the lower end, In order to reduce it by half.

Here, the pixel circuit Px (i, j) corresponds to each pixel of the image.

Fig. 4 is a circuit diagram showing a schematic configuration of pixel circuits of some pixels among all the pixels of the display device of Fig. 3. In Fig. 4, for convenience of explanation, among the plurality of pixel circuits of row n, row m, (1, 1) to Pxodd (1,3) and Pxeven (2,1) to Pxeven (2,3), Pxodd (3,1) to Pxodd (3), which are pixel circuits Pxodd , 3) and Pxeven (4,1) to Pxeven (4,3). However, the other arrangement of the pixel circuits is the same.

In the following description, the pixel circuits Pxodd (1,1) to Pxodd (1,3) and Pxeven (2,1) to Pxeven (2,3), Pxodd Pxodd (3,3) and Pxeven (4,1) to Pxeven (4,3) are mainly described, but the other pixel circuits are also the pixel circuits Pxodd (1,1) to Pxodd ) And Pxeven (2,1) to Pxeven (2,3), Pxodd (3,1) to Pxodd (3,3), and Pxeven (4,1) to Pxeven (4,3).

As shown in Fig. 4, a plurality of pixel circuits Px (i, j) are arranged in two-row pixel circuits of odd-numbered rows and even-numbered rows adjacent to each other, that is, odd-numbered row pixel circuits (Pxodd ) And the even-numbered pixel circuits Pxeven (2,1, 2, and 3) share the gate line Lg1 for supplying the row selection signal applied from the gate driver 12, A pair of pixel circuits composed of the odd-numbered pixel circuits Pxodd (3, 1 to 3, 3) and the even-numbered pixel circuits Pxeven (4, 1 to 4, 3) And a gate line Lg2 for supplying a selection signal.

Although not shown in FIG. 4, the pixel circuits in the third and subsequent rows are also arranged in a pair consisting of an odd-numbered row pixel circuit (Pxodd (1,4 to 1, m)) and an even-numbered row pixel circuit (Pxeven (Pxodd (3,4 to 3, m)) and the even-numbered row pixel circuits (Pxeven (4 to 3, m)) which share the gate line Lg1 in units of the pixel circuits of the even- 4 to 4, m) naturally share the gate line Lg2.

On the other hand, in the conventional display device, one data line for supplying the data signal from the data driver 14 to each pixel circuit is provided for each pixel circuit in one column. However, in the display device 10 of the present embodiment, Numbered row pixel circuits Pxeven (i, j) are divided into odd-numbered data lines (odd-numbered data lines) and odd-numbered data lines (odd-numbered data lines) j supply data signals from the even data lines Ldjeven respectively.

4, odd-numbered row pixel circuits Pxodd (1, 1) and Pxodd (3, 1) are provided with odd-numbered row data lines Ld1odd, Data signals are supplied from the odd-numbered data lines Ld2odd to odd-numbered data lines Ld3odd to odd-numbered pixel circuits Pxodd (3,2) and odd-numbered row pixel circuits (Pxodd (1,3) and Pxodd3,3), respectively.

On the other hand, the even-numbered row pixel circuits Pxeven (2,1) and Pxeven (4,1) are provided with even-numbered row pixel circuits Pxeven (2,2) and Pxeven (4,2) Data lines are supplied from the even-numbered data lines Ld2even to the even-numbered pixel circuits Pxeven (2,3) and Pxeven (4,3) from the even-numbered data lines Ld3even.

4, the odd-numbered row pixel circuits Pxodd ((3,5, ..., n-1), 1) are supplied with data signals from the odd-numbered data lines Ld1odd, The even-numbered pixel circuits Pxeven ((4, 6... N), 1) are similarly supplied with data signals from the even-numbered data lines Ld1even.

(1, 1 to 1, m), (3, 1 to 3, m), (3, 1 to 3, ..., m) adjacent to each other among the plurality of pixel circuits, (n, 1 to n-1, m)) and the even-numbered pixel circuits Pxeven ((2,1 to 2, m), (4,1 to 4, m) , m)) share a gate line (Lg1, Lg2, ..., n / 2), and a plurality of odd-numbered row pixel circuits (Pxodd (3, 1 to 3, m), ... (n-1,1 to n-1, m)) share the odd data lines Ld1odd, Ld2odd, ..., Ldmodd, , The pixel circuits belonging to the same column among the plurality of even row pixel circuits Pxeven ((2,1 to 2, m), (4,1 to 4, m), Respectively, share the even data lines Ld1even, Ld2even, ..., Ldmeven.

The odd-numbered row pixel circuits Pxodd (1,1 to 1, m) include organic EL elements 101odd, two transistors T11odd and T12odd, and a capacitor Codd, Pxeven (2,1 to 2, m) includes an organic EL element 101even, two transistors T11even and T12even, and a capacitor Ceven.

Here, the organic EL element 101odd and the organic EL element 101even, the transistors T11odd and T12odd, the transistors T11even and T12even and the capacitors Codd and Ceven have organic EL elements, transistors and capacitors And the capacitors Codd and Ceven are capacitors connected between the gate and the drain of the transistors T12odd and T12even, respectively.

The organic EL elements 101odd and 101even are display elements having a structure in which a pixel electrode (anode electrode), an organic EL layer composed of a single or a plurality of carrier transporting layers, and a counter electrode are sequentially laminated, and a counter electrode The potential Vss is applied.

Each of the transistors T11odd, T11even, T12odd, and T12even is a TFT composed of an n-channel FET (Field Effect Transistor) and has drains, sources, and gates, and a semiconductor layer is provided between drains and sources. A channel is formed in the semiconductor layer when a bias voltage and a voltage larger than a threshold voltage are applied to the gate, and this channel becomes a current path between the drain and the source.

However, the transistors T11odd, T11even, T12odd and T12even are not limited to the n-channel FET, but may be a p-channel FET. When the transistors T11odd, T11even, T12odd, and T12even are p-channel FETs, the level of each signal applied from each driver described later may be reversed from that of the n-type FET. Therefore, detailed description is omitted.

The transistor T11odd of the odd-numbered pixel circuit Pxodd (i, j) is a switching transistor for applying a gradation signal Vdata representing the gradation of the image data Data to one end of the capacitor Codd, And the drain thereof is connected to the jth odd data line Ldjodd and the drain of each transistor T11odd of the odd-numbered row pixel circuit Pxodd (i, j) is connected to the gate of the transistor T12odd and the one end of the capacitor Codd. And the gate is connected to the gate line Lgi in the i-th row.

The transistor T11even of the even-numbered pixel circuit Pxeven (i, j) is also a switching transistor for applying a gradation signal Vdata indicating the gradation of the image data Data to one end of the capacitor Ceven, The gate of the odd-numbered row pixel circuit Pxodd (i, j) is connected to the gate of the transistor T12even and the one end of the capacitor Ceven, the drain thereof is connected to the jth even-numbered data line Ldjeven, T11even, the gate line Lgi of the i-th row.

That is, the odd-numbered row pixel circuits Pxodd (i, j) and the even-numbered row pixel circuits Pxeven (i, j) adjacent to each other share the gate line Lgi in the i- Numbered data line Ldjodd and the even-numbered data line Ldjeven, which are data lines, respectively.

When signals of a high level are sequentially output to the gate lines Lg1, ..., Lgn / 2, the odd-numbered row pixel circuits Pxodd (i, j) and the even-numbered row pixel circuits Pxeven (i, j) The transistors T11odd and T11even are turned on and the gray level signals Vdata inputted to the odd data lines Ldjodd and the even data lines Ldjeven are supplied to the gates of the transistors T12odd and T12even and to one ends of the capacitors Codd and Ceven Output.

The transistors T12odd and T12even control the amount of current of the current based on the gradation signal Vdata while the organic EL elements 101odd and Pxeven (i, j) of the odd-numbered row pixel circuit Pxodd (i, j) and the gate thereof is connected to the source of the transistors T11odd and T11even and to one end of the capacitors Codd and Ceven and the drain is connected to the power supply terminal Vdd and the source of the capacitors Codd and Ceven, And the other end of the capacitors Codd and Ceven, and the sources are connected to the anodes of the organic EL elements 101odd and 101even, respectively.

However, the positions of the capacitors Codd and Ceven are not limited to the above positions, and the capacitors Codd and Ceven may be connected between the gates and the sources of the transistors T12odd and T12even, respectively.

The gate driver 12 is a driver for selecting a pixel circuit on a row-by-row basis. As shown in Fig. 3, the gate driver 12 of the present embodiment is supplied with the output signal OUT ( 1) to (n / 2)) to each of the gate lines Lg1 to Lgn / 2.

The gate driver 12 of the present embodiment is characterized in that the pixel circuits of two rows adjacent to each other in an odd row and an even row, that is, a pair of adjacent odd row pixel circuits (Pxodd (i, j) (Pxeven (i, j)) share one gate line (Lgi), and one gate line (Lgi) simultaneously selects pixel circuits of two rows of an odd row and an even row.

The data driver 14 is a driver for writing the gradation signal Vdata of the display signal based on the pixel data Data supplied to the capacitors Codd and Ceven of each pixel circuit Px (i, j) The odd data lines Ld1odd to Ldmodd and the even data lines Ld1even to Ldmodd to the odd data lines Ld1odd to Ldmodd and the odd data lines Ld1even to Ldmodd, respectively, in accordance with the image data Data supplied from the controller 15, Ldmeven to the pixel circuits selected by the gate driver 12.

The controller 15 controls the gate driver 12 and the data driver 14 and includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory) The gate driver 12 starts the operation by supplying the start signal to the gate driver 12 while outputting the clock signal to the gate driver 12 and supplies the gate driver 12 with the end signal as the reset signal, .

The controller 15 supplies a start signal, image data (Data), a clock signal, and the like to the data driver 14.

Although not shown in Figs. 3 and 4, the display device 10 includes an anode driver, and the anode driver supplies driving transistors T12odd (i, j) through the anode lines And T12even to apply a voltage VDD of a high level or a low level to the driving transistors T12odd and T12even of the pixel circuit Px (i, j), and by a start signal from the controller 15 And operates in accordance with the clock signal supplied from the controller 15.

In the present embodiment, the cathode voltage Vss of the organic EL elements 101odd and 101even is set to 0 V, and the voltage VDD of High level supplied from the anode driver (not shown) Is set to, for example, +15 V and the voltage of the Low level is set to 0 V or less. The voltage of the organic EL element 101odd 101even of the pixel Px (i, j) However, the cathode voltage Vss and the anode voltage VDD of the organic EL elements 101odd and 101even are not limited to the above values and the cathode voltage Vss and the anode voltage Vdd may be changed according to the characteristics of the organic EL elements 101odd and 101even. (VDD) can be appropriately set.

Next, the operation of the display apparatus 10 of the present embodiment will be described. 5 is a timing chart showing the driving timings of the display device 10 according to the preferred embodiment of the present invention.

(1, 1 to 1, m), (3, 1 to 3, m), ..., (n-1), which are adjacent to each other among the plurality of pixel circuits, (N, 1 to n, m)) and the even-numbered pixel circuits Pxeven ((2,1 to 2, m), (4,1 to 4, m) 1, m), (3, ..., n / 2), and the odd-numbered row pixel circuits Pxodd 1 to 3, m), ... (n-1,1 to n-1, m)) share the odd data lines Ld1odd, Ld2odd, ..., Ldmodd, The pixel circuits of the same column among the pixel circuits Pxeven ((2,1 to 2, m), (4,1 to 4, m), , Ld2even, ..., and Ldmeven from the data driver 14 in the one pulse period of the row selection signal output from the gate driver 12 through the gate line Lgi through the data line Ldj The data signal, i.e., the gate driver 12 selects The gradation signal Vdata to be supplied to one row of the pixel circuits becomes a signal which is inverted by 1/2 pulse cycle of the row selection signal.

4 and 5, the gate driver 12 outputs a high level row selection signal ("first pulse" in FIG. 5) to the gate line Lg1 under the control of the controller 15 The transistors T11odd and T11even of the odd-numbered row pixel circuits Pxodd (1,1 to 1, m) and the even-numbered row pixel circuits Pxeven (2,1 to 2, m) sharing the gate line Lg1, Is turned on by the high level row selection signal.

During this period, the data driver 14 first supplies odd-numbered row pixel circuits Pxodd (1,1 to 1) through the odd-numbered data lines Ld1odd, Ld2odd, ..., Ldmodd in the first half- m) through the respective transistors T11odd to the respective capacitors Codd of the odd-numbered row pixel circuits Pxodd (1,1 to 1, m) by applying the gray-scale signals Vdata to the odd- Vdata) is written.

During the next half pulse period of the first pulse period, the data driver 14 drives the even-numbered pixel circuits Pxeven (2,1 to 2, m) through the even-numbered data lines Ld1even, Ld2even, ..., Ldmeven, (Vdata) to each capacitor Ceven of the even-numbered row pixel circuits Pxeven (2,1 to 2, m) through the transistor T11even .

When the gate driver 12 sequentially outputs a row selection signal of a high level to the gate lines Lg2, Lg3, ..., Lgn / 2 in the same manner, the next pair of odd-numbered row pixel circuits Pxodd (3, The odd-numbered row pixel circuits Pxodd (5, 1 to 5, m) and the even-numbered row pixel circuits Pxeven (4, 6,1 ~ 6, m)), ... (N, 1 to n-1, m) and the even-numbered row pixel circuits (Pxeven (n, 1 to n, m)) are sequentially selected.

During this period, the data driver 14 supplies the odd data lines Ld1odd, Ld2odd, ..., and Ldmodd, respectively, with the gray-scale signals Vdata based on the image data supplied during the first half- Odd-numbered pixel circuits (Pxodd (3, 1 to 3, m)), odd-numbered pixel circuits (Pxodd , The odd-numbered row pixel circuit (Pxodd (n-1,1 to n-1, m)), and then sequentially writes the gradation signal Vdata in the next 1 (Pxeven (4, 1 to 4, m)), even-numbered pixel circuits (Pxeven (6, 1 to 6, m)), and even- , And the gradation signals Vdata are written in the capacitors Ceven of the even-numbered pixel circuits Pxeven (n, 1 to n, m).

When the sequential write operation is completed in this way, the controller 15 controls the unillustrated anode driver to supply the high level voltage VDD to each pixel circuit Px (i, j) through the unillustrated anode line, The transistors T12odd and T12even of the respective pixel circuits Px (i, j) receive the voltage held by the capacitors Codd and Ceven as the gate voltage Vgs, By supplying a corresponding current to the organic EL elements 101odd and 101even, the organic EL elements 101odd and 101even emit light with a luminance corresponding to the current value of this current.

As described above, according to the present embodiment, in the display device comprising a plurality of pixel circuits of n rows and m columns, the plurality of pixel circuits are divided into a pair of odd-numbered row pixel circuits adjacent to each other and a unit of even- , The odd-numbered row pixel circuits and the even-numbered pixel circuits adjacent to each other share one gate line for supplying a row selection signal sequentially applied from the gate driver, so that the number of gate lines is reduced by half / 2).

Therefore, the width of the bezel of the display device can be greatly reduced by reducing the number of gate lines.

In addition, since the number of gate lines crosses the line supplying the other signals in the display device due to the decrease in the number of gate lines, the number of crossing points decreases, and the parasitic capacitance generated at the crossing points also decreases, RC Delay) and voltage drop (IR Drop) can be greatly reduced.

In addition, as the gate line decreases, the aperture ratio of the display device increases, thereby increasing the resolution of the display device.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. Various changes and modifications within the scope of the present invention are possible.

10 display device
12 gate driver
14 data driver
15 controller
The Px (i, j) pixel circuit
Pxodd (i, j) odd-numbered-row pixel circuit
The Pxeven (i, j)
Lg1, Lg2, ... , Lgn / 2 gate line
Ld1odd, Ld2odd, ... , Ldmodd odd data lines
Ld1even, Ld2even, ... , Ldmeven even data line
T11 switching transistor
T12 driving transistor
C capacitor
101 organic EL device

Claims (6)

a display device having a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively)
The plurality of pixel circuits each have a gate line for applying a row selection signal to each of the pair of pixel circuits in units of a pair of pixel circuits each including an odd row pixel circuit and an even row pixel circuit adjacent to each other in the row direction Share,
Numbered row pixel circuit is supplied with a gray-scale signal in units of columns through odd-numbered data lines, and the even-numbered row pixel circuit is supplied with gray-scale signals in units of columns through even-numbered data lines. a display device having a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively)
A plurality of pairs of pixel circuits each including a pair of pixel circuits each consisting of an odd row pixel circuit and an even row pixel circuit adjacent to each other in the row direction,
A gate line for applying a row selection signal in units of the pair of pixel circuits,
An odd-numbered data line for applying a gray-scale signal to the odd-numbered row pixel circuits in each column unit,
And an even-numbered data line for applying a gradation signal to the even-numbered row pixel circuits in each column unit. The method according to claim 1 or 2,
Each of the plurality of pixel circuits includes:
A switching transistor which is driven by a row selection signal applied to the gate line and applies a gradation signal indicative of the gradation of the image data to one end of the capacitor,
A driving transistor that is driven by the switching transistor to supply a current based on a gray-scale signal applied to the odd-numbered data line or the even-numbered data line to the organic EL element;
A capacitor for charging a gradation signal representing the gradation of the image data;
And an organic EL element which emits light at a luminance corresponding to an amount of current of the current. The method of claim 3,
Wherein the switching transistor has a gate connected to the gate line and a source and a drain form a first current path between one of the odd data line and the even data line and the gate of the driving transistor and one end of the capacitor,
Wherein the driving transistor has a gate connected to one end of the first current path and one end of the capacitor, and a source and a drain form a second current path between the other end of the capacitor and the anode power supply terminal and the organic EL element. A display method of a display device having a plurality of pixel circuits of n rows and m columns (m and n are natural numbers respectively)
A row selection signal applying step of sequentially applying a row selection signal to a plurality of pixel circuits each having a pair of pixel circuits each consisting of an odd row pixel circuit and an even row pixel circuit adjacent to each other in the row direction,
A first gradation signal applying step of applying a gradation signal in each column to the selected odd-numbered row pixel circuit;
And a second gradation signal applying step of applying a gradation signal in units of columns to the selected even-numbered row pixel circuit,
Wherein the row selection signal is applied to the pair of pixel circuits through one gate line in the row selection signal application step. The method of claim 5,
The first gradation signal application step is a first half pulse period of the entire pulse period of the row selection signal,
Wherein the second gradation signal application step is a half pulse period of the second half of the entire pulse period of the row selection signal.

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