KR20140119943A - Having electrostatic protecting semiconductor device and electrostatic protecting device - Google Patents

Having electrostatic protecting semiconductor device and electrostatic protecting device Download PDF

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Publication number
KR20140119943A
KR20140119943A KR1020130034605A KR20130034605A KR20140119943A KR 20140119943 A KR20140119943 A KR 20140119943A KR 1020130034605 A KR1020130034605 A KR 1020130034605A KR 20130034605 A KR20130034605 A KR 20130034605A KR 20140119943 A KR20140119943 A KR 20140119943A
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KR
South Korea
Prior art keywords
voltage
circuit
mos
trigger
signal line
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Application number
KR1020130034605A
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Korean (ko)
Inventor
박창근
손민오
서동환
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인텔렉추얼디스커버리 주식회사
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Priority to KR1020130034605A priority Critical patent/KR20140119943A/en
Publication of KR20140119943A publication Critical patent/KR20140119943A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

Disclosed is a semiconductor device including an electrostatic protection function. The semiconductor device includes a protection target circuit, multiple pads inputting and outputting an electric signal, and an electrostatic protection part connected to the protection target circuit and protecting the circuit when a voltage which is higher than a predetermined voltage is applied through the pads. The electrostatic protection part includes multiple MOS devices connected in parallel between the earth and a signal line connecting the pads with the protection target circuit and a trigger circuit connected to between the signal line and the earth and controlling an activation condition of the MOS devices according to a voltage applied to the signal line. A gate of each MOS device is connected to the earth and an output terminal of the trigger circuit is connected to a body of each MOS device.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device having an electrostatic protection function and an electrostatic discharge prevention device,

The present invention relates to a semiconductor element and an antistatic element having an electrostatic protection function.

As the process technology of the MOS device develops, there is a great advantage in terms of the operation speed of the circuit and the manufacturing cost. However, the static resistance of the integrated circuit using the MOS device becomes more and more vulnerable. Development is needed.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified illustration of an antistatic circuit on an integrated circuit according to the prior art.

A semiconductor device generally comprises a pad (PAD) for supplying a power supply voltage and ground from the outside, and an input / output pad for connecting an input / output signal to an external signal line. In some cases, the semiconductor device may include a plurality of power supply voltage pads and input / output pads. Static electricity can occur on any of the power supply voltage pads, ground pads, or input / output pads on an integrated circuit, and current flows to any other pad. Therefore, in the case of the anti-static device shown in FIG. 1, it is necessary to protect the circuit to be protected against all the combinations of the pad to which the static electricity is inputted and the pad to which the static electricity is discharged from the integrated circuit.

Referring to FIG. 1, when an electrostatic current is inputted, the electrostatic current passes through diodes 11 and 12 connected in series, passes through a power clamp 30, and is then output through diodes 13 and 14 connected in series. Here, the power clamp 30 is a circuit or element that provides a path through which static electricity can flow from a power supply voltage to ground when static electricity is generated. The internal circuit 20 is protected from the electrostatic current by the diodes 11, 12, 13, and 14 and the power clamp 30. Although the internal circuit 20 is protected from the electrostatic current by using the diodes 11, 12, 13 and 14 in FIG. 1, other types of antistatic devices such as ggNMOS and gcNMOS, in addition to the diodes 11, 12, May be used.

2 is a view for explaining an antistatic circuit of the ggNMOS structure according to the prior art.

In FIG. 2, ggNMOS 210 having a gate and a source connected to ground is connected to a plurality of connections 210, 220, 230, and 240 between a source line and a ground.

Referring to the ggNMOS 210, the ggNMOS 210 has a gate and a source connected to the ground, so that when a static operation is not generated in the circuit and a general operation is performed, the gate of the ggNMOS 210 is connected to the ground Therefore, the turn-off state is maintained. In this case, the signal line and the ground are kept disconnected from each other.

When a positive voltage is applied to the signal line and a high voltage is applied to the signal line, the channel is not formed in the ggNMOS 210, which is basically turned off, and a high voltage is applied to the drain. When a constant high voltage is applied to the drain, the parasitic junction transistor (BJT) is turned on and the static electricity flows.

However, if a voltage higher than the second beakdown voltage is applied, the ggNMOS 210 may be permanently destroyed. When the ggNMOS 210 of the plurality of ggNMOSs 210, 220, 230, and 240 is turned on and a static electricity current flows, the remaining ggNMOSs 220, 230, and 240 are turned off do. In this case, the ggNMOS 210 turned on is in danger of being destroyed, and the ggNMOS 210, 220, 230, 240 can not be turned on at the same time, so that the internal circuit can not be protected from static electricity.

3 is a view for explaining an antistatic circuit of a gcNMOS structure according to the prior art.

Referring to one gcNMOS 320 of the gcNMOS 320, 330, 340, and 350 of FIG. 3, the gcNMOS 320 prevents the risk of destruction of the ggNMOS 210 of FIG. 2, The gates of the gates are connected to the ground line connected to the ground, and the gates of the gates of the gates are connected to the gates of the gates of the gates of the gates. 330, 340, and 350 by adding the trigger circuit 310 formed by the gcNMOS 320, 330, 340, and 350, respectively.

In this connection, Korean Patent Publication No. 2011-0103814 (titled metal-oxide semiconductor field-effect transistor having an antistatic structure) discloses the structure of gcNMOS.

However, it is difficult to satisfy the condition that the gcNMOS 320, 330, 340, and 350 are simultaneously turned on, and there is a problem that an excessive voltage is applied to the gate.

It is an object of some embodiments of the present invention to provide a semiconductor device which protects a circuit to be protected by applying an electrostatic current to a MOS device body through a trigger circuit to activate the MOS device.

It is also an object of some embodiments of the present invention to provide an antistatic device for preventing static electricity by applying an electrostatic current to a MOS device body through a trigger circuit to activate the MOS device.

It is to be understood, however, that the technical scope of the present invention is not limited to the above-described technical problems, and other technical problems may exist.

According to a first aspect of the present invention, there is provided a semiconductor device having an electrostatic protection function, the device comprising: a protection circuit; a plurality of pads for inputting and outputting an electric signal; And a static eliminator for protecting the circuit to be protected when a voltage equal to or higher than a predetermined voltage is applied through the pad, wherein the static eliminator comprises: a parallel connection line between a signal line connecting the pad and the circuit to be protected, And a trigger circuit connected between the signal line and the ground and adjusting an activation condition of the MOS device according to a voltage applied to the signal line, wherein a gate of the MOS device is connected to the ground And the output terminal of the trigger circuit is connected to the body of the plurality of MOS elements, respectively .

According to a second aspect of the present invention, there is provided an antistatic device comprising: a plurality of MOS devices connected in parallel between a signal line and a ground; and a plurality of MOS devices connected between the signal line and the ground, Wherein a gate of the MOS device is connected to the ground, and an output terminal of the trigger circuit is connected to a body of the plurality of MOS devices, respectively.

The semiconductor device, which is one of the problem solving means of the present invention, activates and activates the electrostatic current through the body of the plurality of MOS devices through the trigger circuit, whereby each MOS device is simultaneously activated and only one MOS device is turned on It is possible to effectively protect the circuit to be protected from the electrostatic current.

1 is a view for explaining a conventional antistatic circuit using a diode.
2 is a view for explaining an antistatic circuit of the ggNMOS structure according to the prior art.
3 is a view for explaining an antistatic circuit of a gcNMOS structure according to the prior art.
4 is a view for explaining a semiconductor device having an electrostatic protection function according to an embodiment of the present invention.
5 is a view for explaining an anti-static unit and an anti-static unit according to an embodiment of the present invention.
6 is a diagram for explaining a change in the current voltage of the static electricity by the static electricity prevention part and the static electricity prevention device according to the embodiment of the present invention.
7 is a view for explaining an antistatic portion and an antistatic element according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. It should be understood, however, that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the same reference numbers are used throughout the specification to refer to the same or like parts.

Throughout this specification, when a part is referred to as being "connected" to another part, it is not limited to a case where it is "directly connected" but also includes the case where it is "electrically connected" do.

Throughout this specification, when an element is referred to as "including " an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise.

The semiconductor device according to an embodiment of the present invention prevents the circuit itself, the internal circuit or the circuit to be protected from damage due to the static electricity generated by the general circuit as shown in FIG.

4 is a view for explaining a semiconductor device having an electrostatic protection function according to an embodiment of the present invention.

Referring to FIG. 4, a semiconductor device having an electrostatic protection function includes a circuit to be protected (internal circuit) 1000 and a plurality of pads (not shown) through which an electric signal is input / output. In addition, the circuit includes an anti-static unit 401 or 402, which is connected to the circuit to be protected 1000 and protects the circuit to be protected when a voltage exceeding a predetermined voltage is applied through a plurality of pads (not shown). Although two static electricity prevention parts 401 and 402 are shown in the drawing, the number of the static electricity prevention parts 401 and 402 can be appropriately set to one or more numbers in consideration of the entire size of the semiconductor device, manufacturing cost, and the like. The antistatic parts 401 and 402 may be the same as the antistatic parts 401 and 402 and the antistatic part according to an embodiment of the present invention. Therefore, the antistatic portions 401 and 402 and the antistatic element can have the same configuration, and their functions can be the same. Hereinafter, the static electricity prevention parts 401 and 402 and the static electricity prevention element are described as being the same.

5 is a view for explaining an anti-static unit and an anti-static unit according to an embodiment of the present invention.

Referring to FIG. 5, the anti-static unit 400 includes a plurality of MOS devices 410, 420, 430, and 440 and a trigger circuit 450. Hereinafter, one MOS device 410 among the plurality of MOS devices 410, 420, 430, and 440 will be described.

A plurality of MOS devices 410 are connected in parallel between a signal line connecting the input / output pad (not shown) and the circuit to be protected 1000 and the ground. And the gate of the MOS device 410 is connected to the ground.

The trigger circuit 450 is connected between the signal line and the ground, and the activation condition of the MOS device 410 is adjusted according to the voltage applied to the signal line. The output terminal of the trigger circuit 450 is connected to the bodies of the plurality of MOS devices 410. [

Trigger circuit 450 may include a capacitor 451 and resistor 452 connected in series between the signal line and ground. The trigger circuit 450 accumulates a voltage in the capacitor 451 when a voltage equal to or higher than a preset voltage is applied through an input / output pad (not shown), and triggers the voltage accumulated in the capacitor 451 through the resistor 452 Voltage to be output to the output terminal.

Trigger circuit 450 may have an output stage disposed between capacitor 451 and resistor 452 to apply the converted trigger voltage to MOS device 410. [ For example, the output terminal of the trigger circuit 450 may be disposed at the center of the connection node of the capacitor 451 and the resistor 452.

The semiconductor device having an electrostatic protection function according to an embodiment of the present invention may include a plurality of MOS devices 410, 420, 430, and 440 of a static electricity prevention unit 400 and a trigger circuit 450 can protect the object circuit 1000 from static electricity. More specifically, the MOS devices 410, 420, 430, and 440 are activated by adjusting activation conditions of the MOS devices 410, 420, 430, and 440 through the trigger circuit 450, can do.

Here, the activation condition of the MOS device 410 is such that the body voltage of the MOS device 410 rises due to the trigger voltage applied to the body of the MOS device 410, and when the body voltage rises, Can be turned on and activated.

Illustratively, the threshold voltages of the plurality of MOS devices 410, 420, 430, and 440 may be slightly different depending on their device characteristics or states, and there may be differences in the activated states. This difference is caused by activating the plurality of MOS elements 410, 420, 430, and 440 under the same conditions by applying a voltage equal to or higher than a predetermined voltage through the capacitor 451 and the resistor 452 of the trigger circuit 450 as the trigger voltage . The relationship between the current and the voltage due to the activation of the MOS device 410 will be described with reference to FIG. 5 to be described later.

6 is a view for explaining current-voltage characteristics of static electricity by the static electricity prevention part and the static electricity prevention device according to the embodiment of the present invention.

Referring to FIG. 6, p1 is the electrostatic voltage and the current state at the time when the static electricity is generated, and p2 is the state where the static electricity is generated and the voltage is increased. At this time, a voltage is accumulated in the capacitor 451 of the trigger circuit 450 included in the static electricity prevention part 400. This causes the electrostatic voltage to decrease and the current to increase until P3, and the MOS device 410 is turned on and activated. Thereafter, until the p4, an electrostatic current is used to operate the MOS device 410 to protect the circuit 1000 to be protected. The p4 point is a secondary breakdown region having a voltage and a current at which the MOS device 410 is destroyed.

The MOS devices 410, 420, 430, and 440 of the anti-static unit 400 may be referred to as bcNMOS (body connected NMOS) according to their shapes. A plurality of MOS devices 410, 420, 430, and 440 of this type and a trigger circuit 450 are connected to the body of a plurality of MOS devices 410, 420, 430, and 440 through a trigger circuit 450, The MOS devices 410, 420, 430, and 440 are simultaneously activated so that only one of the MOS devices 410 is turned on while effectively protecting the circuit to be protected 1000 from the electrostatic current .

In addition to the bcNMOS mode, the anti-static unit 400 may be formed by combining the bcNMOS and the gcNMOS described in FIG. 3 to protect the object circuit 1000 from static electricity.

7 is a view for explaining an antistatic portion and an antistatic element according to another embodiment of the present invention.

Although the embodiment of the present invention has been described with reference to the NMOS, the PMOS can be used to form the electrostatic discharge prevention part and the ESD protection element.

7, a static eliminator and an antistatic device according to another embodiment of the present invention includes a plurality of PMOS devices 710, 720, 730, and 740, a trigger circuit 751 including a capacitor 751 and a resistor 752, (Not shown). The anti-static section and the anti-static element including the PMOS element 710 may have the same characteristics and effects as those of the anti-static section and the anti-static element using the NMOS described above with reference to FIG.

It will be understood by those of ordinary skill in the art that the foregoing description of the embodiments is for illustrative purposes and that those skilled in the art can easily modify the invention without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

400: Antistatic member, antistatic member
410, 420, 430, 440: bcNMOS
450: Trigger circuit
451: Capacitors
452: Resistance
1000: Internal circuit, protected circuit
2000: Power clamp

Claims (11)

1. A semiconductor device having an electrostatic protection function,
The protected circuit,
A plurality of pads for inputting and outputting electric signals and
And an antistatic unit connected to the circuit to be protected and protecting the circuit to be protected when a voltage higher than a predetermined voltage is applied through the pad,
The electrostatic-
A plurality of MOS devices connected in parallel between a signal line connecting the pad and the circuit to be protected and a ground,
And a trigger circuit connected between the signal line and the ground and adjusting an activation condition of the MOS device in accordance with a voltage applied to the signal line,
A gate of the MOS device is connected to the ground,
And an output terminal of the trigger circuit is connected to a body of the plurality of MOS elements, respectively.
The method according to claim 1,
Wherein the trigger circuit has a capacitor and a resistor connected in series between the signal line and the ground.
3. The method of claim 2,
The trigger circuit includes:
When a voltage higher than a predetermined voltage is applied through the pad,
Accumulating a voltage in the capacitor,
And converting the voltage stored in the capacitor through the resistor to a trigger voltage and outputting the trigger voltage to the output terminal.
The method of claim 3,
Wherein the trigger circuit has an output terminal between the capacitor and the resistor to apply the trigger voltage to the plurality of MOS elements.
The method of claim 3,
The activation condition of the MOS device is,
The body voltage of each of the MOS devices rises by the trigger voltage applied to the body of each MOS device,
Wherein a threshold voltage of the MOS device is lowered as the body voltage rises, so that each of the MOS devices is turned on.
In the antistatic element,
A plurality of MOS devices connected in parallel between the signal line and the ground and
And a trigger circuit connected between the signal line and the ground and adjusting an activation condition of the MOS device in accordance with a voltage applied to the signal line,
A gate of the MOS device is connected to the ground,
And the output terminal of the trigger circuit is connected to the body of the plurality of MOS elements, respectively.
The method according to claim 6,
Wherein the signal line connects a plurality of pads through which an electric signal is input / output and a circuit to be protected.
The method according to claim 6,
Wherein the trigger circuit comprises a capacitor and a resistor connected in series between the signal line and the ground.
9. The method of claim 8,
The trigger circuit includes:
When a voltage equal to or higher than a preset voltage is applied,
Accumulating a voltage in the capacitor,
And converting the voltage accumulated in the capacitor through the resistor to a trigger voltage to be output to the output terminal.
10. The method of claim 9,
Wherein the trigger circuit has the output stage disposed between the capacitor and the resistor to apply the trigger voltage to the plurality of MOS devices.
10. The method of claim 9,
The activation condition of the MOS device is,
The body voltage of each of the MOS devices rises by the trigger voltage applied to the body of each MOS device,
Wherein the threshold voltage of the MOS device is lowered as the body voltage rises, so that each of the MOS devices is turned on.
KR1020130034605A 2013-03-29 2013-03-29 Having electrostatic protecting semiconductor device and electrostatic protecting device KR20140119943A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170091828A (en) * 2016-02-01 2017-08-10 삼성디스플레이 주식회사 Electrostatic discharging circuit and display device including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170091828A (en) * 2016-02-01 2017-08-10 삼성디스플레이 주식회사 Electrostatic discharging circuit and display device including the same

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