KR20140111527A - Thin Film Transistor Substrate Having Metal Oxide Semiconductor and Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a thin film transistor substrate for a flat panel display device including a metal oxide semiconductor and a manufacturing method thereof. The thin film transistor substrate including an oxide semiconductor layer according to the present invention includes a substrate; a gate electrode formed on the substrate; a gate insulating film covering the gate electrode; an oxide semiconductor layer overlapping the gate electrode on the gate insulating film; semiconductor buffer layers formed on one upper surface of the oxide semiconductor layer and the other upper surface which is spaced a certain distance away from the one upper surface and faces the one upper surface; a source electrode in contact with the one upper surface of the oxide semiconductor layer across the semiconductor buffer layer; and a drain electrode in contact with the other upper surface of the oxide semiconductor layer across the semiconductor buffer layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate including a metal oxide semiconductor,

The present invention relates to a thin film transistor (TFT) for a flat panel display such as a liquid crystal display (LCD) and an organic light emitting diode display (OLED) And a method of manufacturing the same. More particularly, the present invention relates to a method of fabricating a thin film transistor substrate that can prevent damage to a channel layer formed of a metal oxide semiconductor material without having an etch stopper layer, and a thin film transistor substrate by the method.

The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

In the case of a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device which are actively driven, the thin film transistor substrate includes thin film transistors arranged in pixel regions arranged in a matrix manner. BACKGROUND ART Liquid crystal display devices (LCDs) display images by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device is divided into a vertical electric field type and a horizontal electric field type in accordance with the direction of the electric field driving the liquid crystal.

The vertical electric field type liquid crystal display device drives TN (Twisted Nematic) mode liquid crystal by a vertical electric field formed between a pixel electrode and a common electrode arranged opposite to upper and lower substrates. Such a vertical electric field type liquid crystal display device has a disadvantage that the aperture ratio is large, but the viewing angle is narrow to about 90 degrees.

A horizontal electric field type liquid crystal display device forms a horizontal electric field between a pixel electrode and a common electrode arranged in parallel to a lower substrate to drive a liquid crystal of an in-plane switch (IPS) mode. Such an IPS mode liquid crystal display device has a wide viewing angle of about 160 degrees, but has a disadvantage of low aperture ratio and low transmittance. Specifically, in the IPS mode liquid crystal display device, in order to form an in-plane field, the gap between the common electrode and the pixel electrode is formed wider than the gap (cell gap) between the upper substrate and the lower substrate, The common electrode and the pixel electrode are formed in a band shape having a constant width. An electric field substantially parallel to the substrate is formed between the pixel electrode and the common electrode in the IPS mode, but no electric field is formed in the liquid crystal above the pixel electrode and the common electrode having a constant width. That is, the liquid crystal molecules placed on the pixel electrode and the common electrode are not driven and maintain the initial alignment state. The liquid crystal that maintains the initial state can not transmit light, which causes a decrease in aperture ratio and transmittance.

A fringe field switching (FFS) type liquid crystal display device operated by a fringe field has been proposed to overcome the disadvantage of the IPS mode liquid crystal display device. The FFS type liquid crystal display device has a common electrode and a pixel electrode in each pixel region with an insulating film interposed therebetween. The common electrode and the pixel electrode overlap each other in the vertical direction, or even if they do not overlap, A fringe field of a parabolic shape is formed on the common electrode and the pixel electrode. The liquid crystal molecules interposed between the upper and lower substrates are operated by the fringe field, so that the aperture ratio and the transmittance can be improved.

In the fringe field type liquid crystal display device, since the common electrode and the pixel electrode overlap or are disposed at a considerably close position, an auxiliary capacitance is formed between the common electrode and the pixel electrode. Therefore, unlike the IPS mode, there is an advantage that the auxiliary capacitance need not be formed. However, when the large-screen display device is implemented by the fringe field method, the size of the pixel increases and thus the size of the storage capacitor increases.

In order to solve such a problem, a thin film transistor substrate having a metal oxide semiconductor layer having a high capacity driving characteristic without increasing the size of the thin film transistor has been applied. 1 is a plan view showing a thin film transistor substrate having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along a cutting line I-I '.

The thin film transistor substrate having the metal oxide semiconductor layer shown in FIGS. 1 and 2 includes a gate wiring GL and a data wiring DL intersecting each other with a gate insulating film GI interposed therebetween on a lower substrate SUB, And a thin film transistor (T) formed in each pixel region defined by the pixel region.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D opposed to the source electrode S, And a semiconductor layer A which forms a channel between the source electrode S and the drain electrode D when the gate electrode G is overlapped on the insulating film GI.

Particularly, when the semiconductor layer (A) is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a high charging capacity due to high charge mobility characteristics. However, it is preferable that the oxide semiconductor material further includes an etch stopper (ES) for protecting the upper surface from the etchant in order to secure the stability of the device. Specifically, it is preferable to form an etch stopper (ES) so as to protect the semiconductor layer (A) from the etchant flowing through the separated portion between the source electrode (S) and the drain electrode (D).

One end of the gate line GL includes a gate pad GP for receiving a gate signal from the outside. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 passing through the gate insulating film GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 passing through the first protective film PA1 and the second protective film PA2. Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the first protective film PA1 and the second protective film PA2.

And a pixel electrode PXL and a common electrode COM formed with a second protective film PA2 therebetween to form a fringe field in the pixel region. The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring GL. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL.

The position and shape of the common electrode COM and the pixel electrode PXL can be variously formed according to the design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that varies from time to time is applied to the pixel electrode PXL according to the video data to be implemented. Therefore, parasitic capacitance may occur between the data line DL and the pixel electrode PXL. It is preferable that the common electrode COM is formed first and the pixel electrode PXL is formed on the uppermost layer since this parasitic capacitance can cause image quality problems.

That is, a planarizing film PAC having a low dielectric constant organic material is formed on the first protective film PA1 covering the data line DL and the thin film transistor T, and then a common electrode COM is formed. After the second protective film PA2 covering the common electrode COM is formed, the pixel electrode PXL overlapping the common electrode COM is formed on the second protective film PA2. In this structure, the pixel electrode PXL is separated from the data line DL by the first protective film PA1, the planarization film PAC, and the second protective film PA2, so that the data line DL and the pixel electrode PXL, The parasitic capacitance can be reduced.

The common electrode COM is formed in a rectangular shape corresponding to the shape of the pixel region, and the pixel electrode PXL is formed in a plurality of line segments. In particular, the pixel electrode PXL has a structure in which the pixel electrode PXL is vertically overlapped with the common electrode COM via the second protective film PA2. A fringe field is formed between the pixel electrode PXL and the common electrode COM so that the liquid crystal molecules arranged in the horizontal direction between the TFT substrate and the color filter substrate are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

Hereinafter, a process for fabricating an FFS-type thin film transistor substrate including an oxide semiconductor according to the prior art will be described. FIGS. 3A to 3I are cross-sectional views taken along line I-I 'of FIG. 1, and show a process of manufacturing a thin film transistor substrate of a fringe field method according to the prior art.

A gate metal is deposited on the transparent lower substrate (SUB). The gate metal is patterned in a first mask process to form gate elements. The gate element includes a gate wiring GL, a gate electrode G branching from the gate wiring GL and a gate pad GP formed at one end of the gate wiring GL. (Fig. 3A)

The gate insulating film GI is entirely coated on the substrate SUB on which the gate elements are formed. The oxide semiconductor material is then deposited. In the second mask process, the semiconductor material is patterned to form the semiconductor layer (A). (Figure 3b)

An insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is applied over the entire surface of the substrate on which the semiconductor layer (A) is formed. An insulating material is patterned by a third mask process to form an etch stopper (ES). It is preferable that the etch stopper ES is formed so as to be located at the central portion of the semiconductor layer A to be formed on the gate electrode G. [ (Figure 3c)

The first gate pad contact hole GH1 exposing a part or the whole of the gate pad GP is formed by patterning the gate insulating film GI which is the uppermost portion of the substrate SUB completed with the etch stopper ES, . (Fig. 3d)

Source-drain metal is deposited on the substrate SUB on which the semiconductor layer A and the etch stopper ES are formed. In a fifth mask process, the source-drain metal is patterned to form source-drain elements. The source-drain element includes a data line DL that vertically crosses the gate line GL, a gate pad intermediate terminal IGT that is connected to the gate pad GP through the first gate pad contact hole GH1, A data pad DP formed at one end of the semiconductor layer A and a source electrode S branched at the data line DL and in contact with one side of the semiconductor layer A, And a drain electrode (D) facing the source electrode (S). In particular, the source electrode S and the drain electrode D are physically separated from each other, but have a structure connected through the semiconductor layer A.

The semiconductor layer A is etched by the etchant etching between the source electrode S and the drain electrode D in the process of patterning the source electrode S and the drain electrode D in the absence of the etch stopper ES A back etch phenomenon occurs. If the semiconductor layer (A) contains a silicon-based semiconductor material, the back-etch does not significantly affect the characteristics of the device. However, when the semiconductor layer (A) contains an oxidized semiconductor material, if the back etch occurs, the stability of the device may be deteriorated. Therefore, it is preferable to include an etch stopper (ES) when forming a channel layer with an oxidized semiconductor material. (Fig. 3E)

The first protective film PA1 is applied to the entire surface of the substrate SUB on which the thin film transistor T is completed. Then, the planarizing film (PAC) is coated with an organic material having a low dielectric constant. A planarizing film (PAC) is patterned by a sixth mask process to form the first drain contact hole DH1. The first drain contact hole DH1 does not expose the drain electrode D. The second drain contact hole DH2 is formed to expose the drain electrode to the second protective film PA2 formed later. Since the thickness of the planarization film PAC is relatively thick, the formation of the second drain contact hole DH2 And to secure the exposed area of the drain electrode D in advance. The planarization layer PAC is removed from the gate pad GP and the data pad DP to expose the first passivation layer PA1. (Figure 3f)

A transparent conductive material such as ITO (Indium Tin Oxide) is deposited on the entire surface of the substrate SUB on which the planarizing film PAC is formed. In the seventh mask process, the transparent conductive material is patterned to form the common electrode COM. The common electrode COM is preferably formed in a substantially rectangular shape corresponding to the shape of the pixel region. (Figure 3g)

The second protective film PA2 is coated on the entire surface of the substrate SUB on which the common electrode COM is formed. A second gate pad contact hole GH2 for patterning the first and second protective films PA1 and PA2 to expose the gate pad intermediate terminal IGT, data for exposing a part of the data pad DP, A pad contact hole DPH, and a second drain contact hole DH2 exposing the drain electrode D are formed. (Fig. 3H)

A transparent conductive material such as ITO is again deposited on the second protective film PA2. In the ninth mask process, the transparent conductive material is patterned to form the pixel electrode PXL, the gate pad terminal GPT, and the data pad terminal DPT. The pixel electrode PXL is formed so as to overlap the common electrode COM with the second protective film PA2 interposed therebetween. In particular, they are formed as bars arranged in parallel at regular intervals. The gate pad terminal GPT contacts the gate pad intermediate terminal IGT exposed through the second gate pad contact hole GH2. The data pad terminal (DPT) contacts the data pad (GP) exposed through the data pad contact hole (DPH). (Figure 3i)

Though not shown in the drawing, the thin film transistor substrate on which the pixel electrode PXL and the common electrode COM are formed is transferred to the alignment film processing chamber to apply the alignment film. Then, the liquid crystal layer is coated and adhered to the color filter substrate to complete the liquid crystal display panel.

As described above, nine mask processes are used to fabricate a thin film transistor substrate for an FFS type liquid crystal display including an oxide semiconductor. As the number of mask processes increases, the manufacturing process becomes complicated and the possibility of occurrence of defects increases. Therefore, it is an important problem to simplify the process of manufacturing the thin film transistor substrate which includes the largest number of components in the liquid crystal display device.

It is an object of the present invention to provide a method of manufacturing a thin film transistor substrate including an oxide semiconductor by a smaller number of mask processes and a thin film transistor substrate including the oxide semiconductor by the method have. Another object of the present invention is to provide a thin film transistor substrate and a method of manufacturing the same that can prevent damage to a channel region of an oxide semiconductor layer without using an etch stopper.

In order to accomplish the object of the present invention, a thin film transistor substrate including an oxide semiconductor layer according to the present invention includes a substrate; A gate electrode formed on the substrate; A gate insulating film covering the gate electrode; An oxide semiconductor layer overlying the gate electrode on the gate insulating layer; Semiconductor buffer layers formed on one upper surface of the oxide semiconductor layer and the other upper surface opposed to the one upper surface at a certain distance; A source electrode which is in contact with the upper surface of the one side of the oxide semiconductor layer with the semiconductor buffer layer interposed therebetween; And a drain electrode contacting the upper surface of the other side of the oxide semiconductor layer with the semiconductor buffer layer interposed therebetween.

Wherein the oxide semiconductor layer comprises an indium-gallium-zinc oxide; And the semiconductor buffer layer includes selenium.

And the semiconductor buffer layer has a thickness of 200 ANGSTROM or less.

A protective film formed on the substrate including the source electrode and the drain electrode; A contact hole penetrating a part of the protective film to expose a part of the drain electrode; And a pixel electrode formed on the passivation layer and contacting the drain electrode through the contact hole.

A method of fabricating a thin film transistor substrate including an oxide semiconductor layer according to the present invention includes: forming a gate electrode by applying a gate material on a substrate and patterning the substrate; Sequentially applying a gate insulating film, an oxide semiconductor material, and a semiconductor buffer material on the entire surface of the substrate including the gate electrode, and patterning the oxide semiconductor material and the semiconductor buffer material to form a semiconductor layer and a semiconductor buffer layer ; A source electrode which is in contact with one side of the semiconductor buffer layer by applying and patterning a source-drain material on the entire surface of the substrate including the semiconductor layer and the semiconductor buffer layer, and a drain electrode ; And vaporizing and removing a part of the semiconductor buffer layer exposed between the source electrode and the drain electrode.

Wherein the oxide semiconductor material comprises an indium-gallium-zinc oxide; Wherein the semiconductor buffer material comprises selenium.

And the semiconductor buffer material is coated to a thickness of 200 ANGSTROM or less.

The step of removing a part of the semiconductor buffer layer is characterized in that the heat treatment is performed at a temperature of 180 ° C or less under a vacuum of 10 ^-6 Torr or less.

Forming a contact hole exposing a part of the drain electrode by patterning a protective film on the substrate after vaporizing a part of the semiconductor buffer layer; And forming a pixel electrode in contact with the drain electrode through the contact hole by coating a transparent conductive material on the protective film and patterning the transparent electrode.

The thin film transistor substrate including the oxide semiconductor according to the present invention includes an oxide semiconductor material, and can completely protect the characteristics of the channel region without forming an etch stopper. Therefore, a thin film transistor substrate having excellent characteristics can be provided. In addition, since the channel region can be protected without forming an etch stopper, the number of mask processes in the manufacturing process can be reduced, and manufacturing time and manufacturing cost can be reduced.

1 is a plan view showing a thin film transistor substrate included in a conventional fringe field type liquid crystal display device.
FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the cutting line I-I '. FIG.
FIGS. 3A to 3I are cross-sectional views taken along line I-I 'of FIG. 1, illustrating a process for manufacturing a thin film transistor substrate of a fringe field type according to a related art.
4 is a plan view of a thin film transistor substrate included in a fringe field type liquid crystal display device according to an embodiment of the present invention.
5 is a cross-sectional view of the thin film transistor substrate shown in FIG. 4 taken along a perforated line II-II ';
FIGS. 6A to 6G are cross-sectional views illustrating a process of fabricating a thin film transistor substrate according to an embodiment of the present invention, which is cut into a perforated line III-III 'in FIG.
FIG. 7 is a plan view of a thin film transistor substrate included in an organic light emitting diode display according to another embodiment of the present invention. FIG.
8 is a cross-sectional view of the thin film transistor substrate shown in FIG. 7 taken along a perforated line IV-IV ';

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured.

Hereinafter, a thin film transistor substrate for a flat panel display according to an embodiment of the present invention will be described with reference to FIGS. 4 is a plan view of a thin film transistor substrate included in a fringe field type liquid crystal display according to an embodiment of the present invention. FIG. 5 is a cross-sectional view of the thin film transistor substrate shown in FIG. 4 taken along a perforated line II-II '. In one embodiment of the present invention, a thin film transistor substrate for a horizontal electric field type liquid crystal display of a fringe field method will be mainly described.

A thin film transistor substrate having a metal oxide semiconductor layer includes a gate wiring GL and a data wiring DL intersecting each other with a gate insulating film GI interposed therebetween on a lower substrate SUB, And a thin film transistor T formed thereon.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D opposed to the source electrode S, And a semiconductor layer A which forms a channel between the source electrode S and the drain electrode D when the gate electrode G is overlapped on the insulating film GI.

Particularly, when the semiconductor layer (A) is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a high charging capacity due to high charge mobility characteristics. In order to ensure the stability of the device, it is important that the oxide semiconductor material prevents the upper surface after deposition from being damaged from the gas substance and the chemical liquid in the manufacturing process. In order to protect the channel layer as described above, the present invention further includes a selenium buffer layer (Se) between the semiconductor layer (A) and the source-drain electrode (S-D).

Specifically, selenium (Si) is deposited between the semiconductor layer (A) and the source-drain electrode (SD) so as to protect the semiconductor layer (A) from the etchant flowing through the separated portion between the source electrode And further includes a buffer layer Se. The selenium buffer layer (Se) is one of semiconducting materials that can conduct electricity with light. Therefore, the selenium buffer layer Se does not exist on the surface of the channel region of the semiconductor layer A which is separated between the source electrode S and the drain electrode D. That is, the selenium buffer layer (Se) is continuously deposited on the semiconductor layer (A) to protect the surface of the semiconductor layer (A). The semiconductor layer A, particularly the channel region, can be protected even when patterning the source-drain (S-D) electrode thereafter. Thereafter, the selenium buffer layer (Se) remaining between the source and drain electrodes (S-D) is vaporized and removed in a high vacuum state to complete the channel region in the semiconductor layer (A).

A selenium buffer layer Se as a semiconductor material is interposed between the semiconductor layer A and the source electrode S and between the semiconductor layer A and the drain electrode D to form ohmic contact. On the other hand, the selenium buffer layer Se is removed on the surface of the semiconductor layer A positioned between the source electrode S and the drain electrode D, which is a channel region, so that an undamaged channel region is formed without an etch stopper .

One end of the gate line GL includes a gate pad GP for receiving a gate signal from the outside. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 passing through the gate insulating film GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 passing through the first protective film PA1 and the second protective film PA2. Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the first protective film PA1 and the second protective film PA2.

And a pixel electrode PXL and a common electrode COM formed with a second protective film PA2 therebetween to form a fringe field in the pixel region. The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring GL. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL.

The position and shape of the common electrode COM and the pixel electrode PXL can be variously formed according to the design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that varies from time to time is applied to the pixel electrode PXL according to the video data to be implemented. Therefore, parasitic capacitance may occur between the data line DL and the pixel electrode PXL. It is preferable that the common electrode COM is formed first and the pixel electrode PXL is formed on the uppermost layer since this parasitic capacitance can cause image quality problems.

That is, a planarizing film PAC having a low dielectric constant organic material is formed on the first protective film PA1 covering the data line DL and the thin film transistor T, and then a common electrode COM is formed. After the second protective film PA2 covering the common electrode COM is formed, the pixel electrode PXL overlapping the common electrode COM is formed on the second protective film PA2. In this structure, the pixel electrode PXL is separated from the data line DL by the first protective film PA1, the planarization film PAC, and the second protective film PA2, so that the data line DL and the pixel electrode PXL, The parasitic capacitance can be reduced.

The common electrode COM is formed in a rectangular shape corresponding to the shape of the pixel region, and the pixel electrode PXL is formed in a plurality of line segments. In particular, the pixel electrode PXL has a structure in which the pixel electrode PXL is vertically overlapped with the common electrode COM via the second protective film PA2. A fringe field is formed between the pixel electrode PXL and the common electrode COM so that the liquid crystal molecules arranged in the horizontal direction between the TFT substrate and the color filter substrate are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

Hereinafter, a process of fabricating a thin film transistor substrate included in a fringe field type liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. 6A to 6G. 6A to 6G are cross-sectional views illustrating a process of fabricating a thin film transistor substrate according to an embodiment of the present invention, which is cut into a perforated line III-III 'in FIG. Since the manufacturing process is characterized by the thin film transistor portion of the present invention, only the thin film transistor will be mainly described. Reference is made to Figs. 4 and 5 for the components formed in the region other than the region representing the thin film transistor portion. Further, if necessary, reference can be had to Figs. 3A to 3I, which are descriptions of the prior art.

A gate metal is deposited on the transparent lower substrate (SUB). The gate metal is patterned in a first mask process to form gate elements. The gate element includes a gate wiring GL, a gate electrode G branching from the gate wiring GL and a gate pad GP formed at one end of the gate wiring GL. (Fig. 6A)

The gate insulating film GI is entirely coated on the substrate SUB on which the gate elements are formed. Subsequently, the oxidized semiconductor material and the buffer material are continuously deposited. Here, the buffer material includes selenium, and it is most preferable to coat the buffer material to a thickness of 200 ANGSTROM or less. In the second mask process, the semiconductor semiconductor material and the buffer material are patterned to form the semiconductor layer (A) and the selenium buffer layer (Se). Since the semiconductor material layer and the buffer material are simultaneously patterned, the selenium buffer layer Se covers the surface of the channel region in the semiconductor layer (A), particularly in the central portion thereof. Therefore, the semiconductor layer A is not exposed to the photoresist, etchant, . (Fig. 6B)

A gate insulating layer GI which is the uppermost layer of the substrate SUB on which the semiconductor layer A and the selenium buffer layer Se are completed may be patterned to expose a part or all of the gate pad GP The first gate pad contact hole GH1 can be formed. In this case, a mask process can be further added. Here, this masking step is not essential and will be omitted.

Source-drain metal is deposited on a substrate SUB on which a semiconductor layer A and a selenium buffer layer Se are formed. In a third masking process, the source-drain metal is patterned to form source-drain elements. The source-drain element is connected to the data line DL perpendicularly intersecting the gate line GL, the data pad DP formed at one end of the data line DL and the data line DL, And a drain electrode D which is in contact with the other side of the semiconductor layer A and opposes the source electrode S, Although not shown in the drawing, the first gate pad contact hole GH1 may further include a gate pad intermediate terminal IGT connected to the gate pad GP through the first gate pad contact hole GH1 It is possible.

In the process of patterning the source electrode S and the drain electrode D, a selenium buffer layer (not shown) is formed on the upper surface of the channel layer, which is the semiconductor layer A occupying the spacing space between the source electrode S and the drain electrode D Se) exists, the channel region is not attacked by the etching solution and the strip solution. After the source electrode (S) and the drain electrode (D) are completed, the remaining selenium buffer layer (Se) on the upper surface of the channel region must be removed. If the selenium buffer layer (Se) remains in the channel region, it can not function as a channel region because the metal connection state is maintained.

Thus, after completing the source-drain electrode SD, the exposed selenium buffer layer Se is vaporized and removed by performing a heat treatment under a vacuum of 10 ^-6 Torr or less and a temperature of 180 ° C or lower. Thus, although the source electrode S and the drain electrode D are physically separated from each other, they are connected to each other through the semiconductor layer A. The temperatures at which selenium can be vaporized in a vacuum state are shown in Table 1 below. Therefore, it is preferable to vaporize and remove the selenium buffer layer Se exposed between the source electrode S and the drain electrode D by using the vacuum degree and the vaporization temperature value most suitable for the conditions of the manufacturing process to be applied.

Vacuum degree (Torr) 10 ^-8 10 ^-7 10 ^-6 10 ^-5 10 ^-4 10 ^-3 10 ^-2 10 ^-1 One Temperature (℃) 63 83 107 133 164 199 243 297 363

An oxide semiconductor layer (A) according to an embodiment of the present invention uses indium-gallium-zinc-oxide (IGZO). In this case, the selenium buffer layer (Se) does not react with the oxide semiconductor layer (A) because the binding energy of the indium (In), gallium (Ga), and zinc It can be confirmed through Raman and XPS experiments that the metal bond with (A) completely disappears and is vaporized. Further, it can be confirmed by XPS experiment that the chemical structure of the oxide layer which is the underlying semiconductor layer (A) is not changed.

The thin film transistor according to the present invention does not include an etch stopper. A back etch in which the semiconductor layer A is etched by an etchant etching between the source electrode S and the drain electrode D in the process of patterning the source electrode S and the drain electrode D, The phenomenon does not occur. The selenium buffer layer (Se) functions to protect the surface of the oxide semiconductor layer (A). The thickness of the selenium buffer layer (Se) is preferably determined in consideration of both the process time for removing the selenium buffer layer (Se), the stability of the manufacturing process, and the channel region protection capability of the selenium buffer layer (Se). As a result of conducting several experiments in this embodiment, it was preferable that the thickness did not exceed 200 Å. (Fig. 6C)

The first protective film PA1 is applied to the entire surface of the substrate SUB on which the thin film transistor T is completed. Then, the planarizing film (PAC) is coated with an organic material having a low dielectric constant. A planarizing film (PAC) is patterned by a fourth mask process to form the first drain contact hole DH1. The first drain contact hole DH1 does not expose the drain electrode D. The second drain contact hole DH2 is formed to expose the drain electrode to the second protective film PA2 formed later. Since the thickness of the planarization film PAC is relatively thick, the formation of the second drain contact hole DH2 And to secure the exposed area of the drain electrode D in advance. In addition, the planarization layer (PAC) may be removed from the gate pad GP and the data pad DP to expose the first passivation layer PA1. (Fig. 6D)

A transparent conductive material such as ITO (Indium Tin Oxide) is deposited on the entire surface of the substrate SUB on which the planarizing film PAC is formed. In the fifth mask process, the transparent conductive material is patterned to form the common electrode COM. The common electrode COM is preferably formed in a substantially rectangular shape corresponding to the shape of the pixel region. (Fig. 6E)

The second protective film PA2 is coated on the entire surface of the substrate SUB on which the common electrode COM is formed. In the sixth mask process, the first and second protective films PA1 and PA2 are patterned to form a data pad contact hole DPH exposing a part of the data pad DP, and a second drain contact Thereby forming a hole DH2. Although not shown in the figure, when the gate pad intermediate terminal IGT is further included, a second gate pad contact hole GH2 may be further formed to expose the gate pad intermediate terminal IGT. (Figure 6f)

A transparent conductive material such as ITO is again deposited on the second protective film PA2. In the seventh mask process, the transparent conductive material is patterned to form the pixel electrode PXL, the gate pad terminal GPT, and the data pad terminal DPT. The pixel electrode PXL is formed so as to overlap the common electrode COM with the second protective film PA2 interposed therebetween. In particular, they are formed as bars arranged in parallel at regular intervals. The gate pad terminal GPT contacts the gate pad intermediate terminal IGT exposed through the second gate pad contact hole GH2. The data pad terminal (DPT) contacts the data pad (GP) exposed through the data pad contact hole (DPH). (Fig. 6G)

As described above, the thin film transistor substrate for a liquid crystal display of the fringe field type horizontal electric field type according to an embodiment of the present invention includes an oxide semiconductor material, and can completely protect the characteristics of a channel region without forming an etch stopper . Therefore, a thin film transistor substrate having excellent characteristics can be provided. In addition, the number of mask processes in the manufacturing process can be reduced, thereby reducing manufacturing time and cost.

In the above description, the present invention is applied to a flat panel display device such as a liquid crystal display device. The present invention is equally applied to a liquid crystal display device as well as an organic light emitting diode display device, so that a display device having excellent characteristics can be manufactured with a short manufacturing time and at a low cost.

7 and 8, a structure of a thin film transistor for an organic light emitting diode display device in which an oxide semiconductor material is protected by a selenium buffer layer will be described as another embodiment of the present invention. 7 is a plan view showing a thin film transistor substrate included in an organic light emitting diode display according to another embodiment of the present invention. FIG. 8 is a cross-sectional view of the thin film transistor substrate shown in FIG. 7 taken along a perforated line IV-IV '.

7 and 8, an active matrix organic light emitting diode display device according to another embodiment of the present invention includes a switching thin film transistor ST, a driving TFT DT connected to the switching TFT, And an organic light emitting diode (OLED).

The switching TFT ST is formed at a portion where the scan line SL and the data line DL intersect each other. The switching TFT ST functions to select a pixel. The switching TFT ST includes a gate electrode SG, a semiconductor layer SA, a source electrode SS, and a drain electrode SD which branch off from the scan line SL. The driving TFT DT serves to drive the organic light emitting diode OLED of the pixel selected by the switching TFT ST. The driving TFT DT includes a gate electrode DG connected to the drain electrode SD of the switching TFT ST and a source electrode DS connected to the semiconductor layer DA and the driving current wiring VDD, DD). The drain electrode DD of the driving TFT DT is connected to the anode electrode ANO of the organic light emitting diode OLED. An organic light emitting layer (OLE) is interposed between the anode electrode ANO and the cathode electrode CAT. The cathode electrode CAT is connected to the base voltage VSS.

More specifically, the gate electrodes SG and DG of the switching TFT ST and the driving TFT DT are formed on the substrate SUB of the active matrix organic light emitting diode display device. A gate insulating film GI covers the gate electrodes SG and DG. The semiconductor layers SA and DA are formed in a part of the gate insulating film GI which overlaps with the gate electrodes SG and DG. The source electrodes SS and DS and the drain electrodes SD and DD are formed facing each other on the semiconductor layers SA and DA at regular intervals. The drain electrode SD of the switching TFT ST contacts the gate electrode DG of the driving TFT DT through the drain contact hole DH formed in the gate insulating film GI. A protective film PAS covering the switching TFT ST and the driving TFT DT having such a structure is applied to the entire surface.

A color filter CF is formed at a portion corresponding to the region of the anode electrode ANO to be formed later. It is preferable that the color filter CF is formed so as to occupy a wide area as much as possible. For example, it is preferable to overlap with many regions of the data line DL, the drive current line VDD and the scan line SL at the previous stage. As described above, the substrate on which the color filter CF is formed is formed with various components, the surface is not flat, and many steps are formed. Therefore, the overcoat layer OC is applied over the entire surface of the substrate in order to flatten the surface of the substrate.

An anode electrode ANO of the organic light emitting diode OLED is formed on the overcoat layer OC. The anode electrode ANO is connected to the drain electrode DD of the driving TFT DT through the pixel contact hole PH formed in the overcoat layer OC and the protective film PAS.

A bank pattern BANK is formed on a region where a switching TFT ST, a driving TFT DT and various wirings DL, SL and VDD are formed on a substrate on which an anode electrode ANO is formed to define a pixel region .

And the anode electrode ANO exposed by the bank pattern BANK becomes a light emitting region. The organic light emitting layer OLE and the cathode electrode layer CAT are sequentially stacked on the anode electrode ANO exposed by the bank pattern BANK. When the organic light emitting layer (OLE) is made of an organic material emitting white light, the organic coloring layer (OLE) exhibits a color assigned to each pixel by a color filter (CF) located below. The organic light emitting diode display device having the structure as shown in FIG. 8 is a bottom emission display device emitting light in a downward direction.

By providing a thin film transistor in such a flat panel display device, a high-quality active type display device can be realized. In particular, in order to have more excellent driving characteristics, the channel layer of the thin film transistor is preferably formed of a metal oxide semiconductor material.

Particularly, when the semiconductor layers SA and DA are formed of an oxide semiconductor material, they are advantageous for a large-area thin film transistor substrate having a high charging capacity due to high charge mobility characteristics. In order to ensure the stability of the device, it is important that the oxide semiconductor material prevents the upper surface after deposition from being damaged from the gas substance and the chemical liquid in the manufacturing process. In order to protect the channel layer, a selenium buffer layer Se is further provided between the semiconductor layers SA and DA and the source-drain electrodes SS-SD and DS-DD.

More specifically, the semiconductor layers SA, DA and the source-drain regions SA, DA are formed so as to protect the semiconductor layers SA, DA from the etchant flowing through the separated portions between the source electrodes SS, DS and the drain electrodes SD, And a selenium buffer layer Se between the drain electrodes SS-SD and DS-DD. The selenium buffer layer (Se) is one of semiconducting materials that can conduct electricity with light. The selenium buffer layer Se does not exist on the channel region surface of the separated semiconductor layers SA and DA between the source electrodes SS and DS and the drain electrodes SD and DD. That is, the selenium buffer layer Se is continuously deposited on the semiconductor layers SA and DA to protect the surfaces of the semiconductor layers SA and DA. It is possible to protect the semiconductor layers SA and DA, particularly the channel region, even when patterning the source-drain (SS-SD, DS-DD) electrode thereafter. Thereafter, the selenium buffer layer Se remaining between the source and drain electrodes SS-SD and DS-DD is vaporized and removed in a high vacuum state to complete the channel region in the semiconductor layers SA and DA.

A selenium buffer layer Se as a semiconductor material is interposed between the semiconductor layers SA and DA and the source electrodes SS and DS and between the semiconductor layers SA and DA and the drain electrodes SD and DD to form an ohmic contact . On the other hand, the selenium buffer layer Se is removed on the surfaces of the semiconductor layers SA, DA located between the source electrodes SS, DS and the drain electrodes SD, DD, which are channel regions, An undamaged channel region is formed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

T: Thin film transistor SUB: Substrate
GL: gate wiring CL: common wiring
DL: Data wiring PXL: Pixel electrode
COM: Common electrode GP: Gate pad
DP: Data pad GPT: Gate pad terminal
DPT: Data pad terminal IGT: Gate pad middle terminal
GPH: gate pad contact hole GH1: first gate pad contact hole
GH2: second gate pad contact hole DPH: data pad contact hole
G: gate electrode S: source electrode
D: drain electrode A: semiconductor channel layer
GI: gate insulating film PAS: protective film
PA1: first protective film PA2: second protective film
PAC: planarization film DH: drain contact hole
ES: Etch stopper Se: Selenium buffer layer
SL: scan wiring
SP: Scan Pads SPI: Scan Pads Intermediate Terminals
SPH: Scan pad contact hole SPT: Scan pad terminal
VDD: drive current wiring ST: switching TFT
DT: Driving TFT OLED: Organic Light Emitting Diode
SG, DG: gate electrode SS, DS: source electrode
SD, DD: drain electrode SE, DE: etch stopper
CAT: cathode electrode (layer) ANO: anode electrode (layer)
BANK: Bank CF: Color filter
OLE: (white) organic layer OC: overcoat layer
PL: planarization film PH: pixel contact hole

Claims (9)

Board;
A gate electrode formed on the substrate;
A gate insulating film covering the gate electrode;
An oxide semiconductor layer overlying the gate electrode on the gate insulating layer;
Semiconductor buffer layers formed on one upper surface of the oxide semiconductor layer and the other upper surface opposed to the one upper surface at a certain distance;
A source electrode which is in contact with the upper surface of the one side of the oxide semiconductor layer with the semiconductor buffer layer interposed therebetween; And
And a drain electrode which contacts the upper surface of the other side of the oxide semiconductor layer with the semiconductor buffer layer interposed therebetween.
The method according to claim 1,
Wherein the oxide semiconductor layer comprises an indium-gallium-zinc oxide;
Wherein the semiconductor buffer layer comprises selenium. ≪ RTI ID = 0.0 > 11. < / RTI >
The method according to claim 1,
Wherein the semiconductor buffer layer has a thickness of 200 ANGSTROM or less.
The method according to claim 1,
A protective film formed on the substrate including the source electrode and the drain electrode;
A contact hole penetrating a part of the protective film to expose a part of the drain electrode; And
And a pixel electrode formed on the passivation layer and contacting the drain electrode through the contact hole.
Applying a gate material over the substrate and patterning to form a gate electrode;
Sequentially applying a gate insulating film, an oxide semiconductor material, and a semiconductor buffer material on the entire surface of the substrate including the gate electrode, and patterning the oxide semiconductor material and the semiconductor buffer material to form a semiconductor layer and a semiconductor buffer layer ;
A source electrode which is in contact with one side of the semiconductor buffer layer by applying and patterning a source-drain material on the entire surface of the substrate including the semiconductor layer and the semiconductor buffer layer, and a drain electrode ; And
And vaporizing and removing a part of the semiconductor buffer layer exposed between the source electrode and the drain electrode.
6. The method of claim 5,
Wherein the oxide semiconductor material comprises an indium-gallium-zinc oxide;
Wherein the semiconductor buffer material comprises selenium. ≪ RTI ID = 0.0 > 21. < / RTI >
6. The method of claim 5,
Wherein the semiconductor buffer material is applied to a thickness of 200 ANGSTROM or less.
6. The method of claim 5,
Wherein removing the portion of the semiconductor buffer layer comprises:
Wherein the heat treatment is performed at a temperature of 180 DEG C or less in a vacuum state of 10 ^-6 Torr or less.
6. The method of claim 5,
After vaporizing a part of the semiconductor buffer layer,
Forming a contact hole exposing a part of the drain electrode by applying a protective film on the substrate and patterning the substrate; And
Applying a transparent conductive material on the passivation layer and patterning the passivation layer to form a pixel electrode in contact with the drain electrode through the contact hole.

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