KR20140109209A

KR20140109209A - Memory device and the method of operating the same

Info

Publication number: KR20140109209A
Application number: KR1020130047548A
Authority: KR
Inventors: 심용; 송인달; 최영
Original assignee: 삼성전자주식회사
Priority date: 2013-03-05
Filing date: 2013-04-29
Publication date: 2014-09-15

Abstract

A memory device is provided. The memory device comprises n-1 frequency demultipliers which create a second demultiply clock or n (n is a natural number satisfying a following equation, n>=2) clocks by demultiplying a first clock; a first delay unit which creates a first demultiply clock which delays the first lock for the same time applied to the second demultiply clock or the n multiply clock for delaying; an MUX unit which receives the first demultiply clock or the n multiply clock and chooses one of the clocks; a flip-flop unit which is connected to the MUX unit, receives and synchronizes the selected demultiply clock and a first signal; and a command decoder unit which decodes the synchronized signal provided from the flip-flop unit and creates internal command signal.

Description

[0001] The present invention relates to a memory device and a method of operating the same,

The present invention relates to a memory device and a method for driving the memory device.

2. Description of the Related Art In general, semiconductor memory devices such as dynamic random access memory (DRAM) have been continuously improved in order to improve the operation speed thereof with an increase in integration degree. In order to improve the operation speed of a DRAM, an SDRAM (Synchronous Dynamic Random Access Memory) that can operate in synchronization with an external clock signal input from the outside has appeared.

However, SDRAM is also insufficient to satisfy the speed of a system requiring high-speed operation. Accordingly, a double data rate (DDR) scheme, which is a method of processing two data in one clock cycle, has been proposed. Since the double data rate RAM (DDR RAM) inputs and outputs two data continuously in synchronization with the rising edge and the falling edge of the external clock signal input from the outside, the high-speed operation becomes possible .

Meanwhile, double data rate RAM (DDR RAM) has evolved into 'DDR2 RAM', 'DDR3 RAM' and 'DDR4 RAM' over the generations.

However, as the memory device gradually operates at high speed, it becomes difficult to secure a timing margin in the memory device. To overcome this, a gear-down mode is used to lower the frequency of the clock.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device that minimizes the number of circuits used without causing a skew in timing even when the gear-down mode is used.

It is another object of the present invention to provide a method of driving a memory device that minimizes the number of circuits used without occurrence of a timing skew even when the gear-down mode is used.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a memory device comprising: a memory device for dividing a first clock and generating n-1 (n-1) A first delay unit for generating a first divided clock in which the first clock is delayed by the same time as the second divided clock to the n th divided clock, and a second delay unit for receiving the first divided clock to the n th divided clock, A flip-flop unit coupled to the mux unit for receiving and synchronizing the selected clock with the first signal, and a flip-flop unit for decoding the synchronized signal provided from the flip- And a command decoder for generating a command signal.

The MUX receives a Mode Register Set (MRS) signal and can select one of the first to n-th frequency dividing clocks.

The mux portion may include n mux portions, and each of the n mux portions may be connected to the first delay portion and the n-1 frequency dividers one-to-one.

The n muxes may select one of the first to n-th frequency bands by receiving n MRS signals.

And a second delay unit delaying the first signal by the selected divided clock.

The decoder may further include a third delay unit that is further provided with a command and delays the command by the synchronized signal.

Wherein the duty ratio of the second divided clock to the n th divided clock is smaller than 1/2 and the duty is sequentially decreased from the first divided clock to the n th divided clock, the clock levels of the n frequency-dividing clocks include a first level and a second level, and the times at which the clock level is the first level within one period of the first to n-th frequency dividing clocks may be equal to each other, And the clock level may be different from the second level within one cycle of the first to n-th divided clocks.

The first signal may include at least one of chip select (CS), chip enable (CE), clock enable (CKE) and on-die termination (ODT), an address signal ADDR and an external command signal CMD have.

According to another aspect of the present invention, there is provided a memory device including: a command control logic for generating an internal command signal; a memory cell array including a plurality of memory cells; Wherein the command control logic comprises: n-1 pieces of clocks for dividing a first clock and generating second to n-th divided clocks (where n is a natural number 2); and a sense amplifier / A first delay unit for generating a first divided clock in which the first clock is delayed by the same time as the second divided clock to an n th divided clock and a second delayed unit for receiving the first divided clock to an n th divided clock A flip-flop section connected to the mux section and adapted to receive and synchronize with the selected divided clock signal, And a command decoder unit for decoding the synchronized signal provided from the flip-flop unit to generate the internal command signal.

The first signal includes a chip select (CS) signal, and the sense amplifier / write driver may select one of the plurality of memory cells using the internal command signal generated by the first signal.

The first signal further includes a chip enable (CE) signal, and the sense amplifier / write driver may enable the selected memory cell using the internal command signal generated by the first signal.

The sense amplifier / write driver includes an on-die termination (ODT) device, the first signal including an on-die termination (ODT) signal, the internal command signal generated by the first signal So that the ODT circuit can be enabled.

The duty ratios of the first to n < th > divided clocks may be sequentially decreased from the first divided clock to the n < th > divided clock.

The details of other embodiments are included in the detailed description and drawings.

1 is a block diagram of a memory device in accordance with an embodiment of the invention.
FIGS. 2 and 3 are timing diagrams showing divided clocks output in the frequency divider.
4 is a block diagram of a memory device for explaining the effect of the present invention.
5 is a block diagram of a memory device in accordance with another embodiment of the present invention.
6 is a block diagram of a memory device in accordance with another embodiment of the present invention.
Figure 7 is a block diagram illustrating an electronic system including a memory device in accordance with some embodiments of the present invention.
8 and 9 are flowcharts for explaining a method of driving a memory device according to an embodiment of the present invention.
10 is a flowchart illustrating a method of driving a memory device according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of the components shown in the figures may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout the specification and "and / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

The term 'sub' or 'module' as used in the present embodiment means a hardware component such as software or FPGA or ASIC, and 'sub' or 'module' performs certain roles. However, " part " or " module " is not meant to be limited to software or hardware. The term " part " or " module " may be configured to reside on an addressable storage medium and configured to play one or more processors. Thus, by way of example, 'a' or 'module' is intended to be broadly interpreted as encompassing any type of process, including features such as software components, object-oriented software components, class components and task components, Microcode, circuitry, data, databases, data structures, tables, arrays, and variables, as used herein, Or " modules " or " modules " or " modules " or " modules " Can be further separated.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms " comprises "and / or" comprising "used in the specification do not exclude the presence or addition of one or more other elements in addition to the stated element.

Although the first, second, etc. are used to describe various elements or components, it is needless to say that these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, it is needless to say that the first element or the constituent element mentioned below may be the second element or constituent element within the technical spirit of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

A memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a block diagram of a memory device according to one embodiment of the present invention, and FIGS. 2 and 3 are timing diagrams showing divided clocks output in a divider.

Hereinafter, for convenience of explanation, it is assumed that the memory device of the present invention is a DDR4 RAM operating at high speed. However, the present invention is not limited thereto.

Referring to FIG. 1, a memory device 100 according to an embodiment of the present invention includes a signal buffer 101_1, a clock buffer 101_2, n-1 frequency dividers 105_2, ..., and 105_n, Second delay units 103_1 and 103_2, n MUX units 107, a flip-flop unit 109 and a command decoder unit 111. [ Here, n is a natural number of n? 2.

The first clock CLK is provided to the first delay unit 105_1 and n-1 frequency dividers 105_2, ..., 105_n through the clock buffer 101_2. The clock buffer 101_2 serves to amplify the first clock CLK. And may provide the first clock bar (CLKB) to the clock buffer 101_2 in order to amplify the first clock (CLK). The first clock bar (CLKB) is the same size as the first clock and has a phase difference of 180 degrees. The clock buffer 101_2 amplifies the magnitude of the first clock CLK and does not change the period of the first clock CLK. Referring to FIG. 2, the clock buffer 101_2 amplifies the first clock CLK to generate an amplified first clock CLK_O having a larger amplitude than the first clock CLK.

The first clock CLK_O amplified by the clock buffer 101_2 is provided to the first delay unit 105_1 and n-1 frequency dividers 105_2, ..., and 105_n.

The n-1 frequency dividers 105_2, ..., and 105_n may be connected in parallel with the clock buffer 101_2 and may divide the amplified first clock CLK_O. Specifically, referring to FIG. 1 and FIG. 2, the 1/2 frequency divider 105_2 can generate a second divided clock CLK_D2 having a frequency 1/2 times the amplified first clock CLK_O have. That is, the second divided clock CLK_D2 may have a cycle twice as much as the amplified first clock CLK_O. Likewise, the 1/3 cycle 105_3 can generate a third divided clock CLK_D3 having a frequency that is 1/3 times the amplified first clock CLK_O. That is, each of the (n-1) frequency dividers 105_2, 105_3, ..., and 105_n is divided into 1/2, 1/3, , And second to n-th frequency dividing clocks CLK_D2, CLK_D3, ..., CLK_Dn having a frequency of 1 / n times.

The first delay unit 105_1 outputs the amplified first clock CLK_O without changing the frequency. Since it outputs without changing the frequency, it can be seen in 1/1 frequency. However, the first delay unit 105_1 generates the first divided clock CLK_D1 by delaying the amplified first clock CLK_O by a predetermined time.

The first delay unit 105_1 is necessary for matching the timing skew with the 1/2 to 1 / n divider 105_2, 105_3, ..., 105_n. More specifically, referring to FIG. 2, n-1 frequency dividers 105_2,..., 105_n generate second to N'th frequency bands CLK_D2 to CLK_Dn. However, the amplified first clock CLK_O may be delayed by a predetermined time, that is, d while being divided by the second divided clocks CLK_D2 through n_number dividing clocks CLK_Dn. Accordingly, the first divided clock CLK_D1 is delayed by d like the second through n-th divided clocks CLK_D2, ..., CLK_Dn so that skew is not generated. The first delay unit 105_1 is arranged to delay the first And generates a first divided clock CLK_D1 by delaying the received clock CLK_O by d.

On the other hand, the 1/2 to 1 / n divider 105_2, ..., 105_n can divide the amplified first clock CLK_O into different forms. Referring to FIG. 3, the 1/2 to 1 / n divider 105_2, ..., 105_n generates the second divided clock signal CLK_D2 to the n-th divided clock signal CLK_Dn, And the first clock is generated by delaying the amplified first clock CLK_O by d. In FIG. 2, all of the first through n-th divided clock signals CLK_D1 through CLK_Dn have a duty ratio of 1/2, whereas the first divided clock signals CLK_D1 through CLK_Dn ) Can have a duty less than 1/2. The duty can be expressed as a ratio of ON time to one cycle of the clock.

The clock may have two clock levels, i.e., a first level and a second level. Here, the first level means a clock level operating in the ON state, and the second level means a clock level operating in the OFF state. Therefore, the duty is a ratio of the high level time during one period of the clock when the clock operates at the high level, and is a ratio of the low level during one period when the clock operates at the low level. It is the ratio of level time.

2 and 3 illustrate the case where the high level operates in the ON state, a person skilled in the art will be able to deduce a case where the operation is performed from the low level to the ON state by referring to FIG. 2 and FIG.

Referring to FIG. 3, the duty ratio of the first divided clock signal CLK_D1 is 1/2. However, the duty of the second divided clock CLK_D2 is 1/4, not 1/2. And the duty of the third divided clock CLK_D3 is 1/6. Therefore, the duty of the n-th frequency divider clock CLK_Dn is 1 / (2n). That is, in FIG. 3, the duty from the first divided clock CLK_D1 to the nth divided clock CLK_Dn can be sequentially decreased, and the second to the n-th divided clock CLK_Dn are smaller than 1/2.

The reason why the duty ratios of the first to nth divided clocks CLK_D1, ..., CLK_Dn are sequentially lowered occurs because there is a difference in the method of generating the divided clock. In Fig. 3, unnecessary pulse signals are removed from the provided amplified first clock signal CLK_O to generate first to n-th divided clock signals CLK_D1, ..., CLK_Dn. Specifically, the second divided clock CLK_D2 sets two periods of the amplified first clock CLK_O as one period, and leaves only the first pulse, that is, the 0th pulse in one period, do. The third frequency dividing clock signal CLK_D3 sets three periods of the amplified first clock signal CLK_O as one cycle, and leaves only the first pulse, i.e., the 0th pulse, in one period, and removes all other remaining pulses. Likewise, the n-th frequency dividing clock CLK_Dn sets n periods of the amplified first clock CLK_O as one period and all the other pulses are removed while leaving only the first pulse, i.e., the 0th pulse, in one period . The first divided clock CLK_D1 is delayed only by d compared to the amplified first clock CLK_O, and has the same period as the amplified first clock CLK_O.

Since the first pulse of the amplified first clock CLK_O is left as it is, the high level, that is, the first level, per one cycle of the first to n-th divided clocks CLK_D1, ..., CLK_Dn is All can be the same. The low level, i.e., the second level, of one cycle of the first to n < th > divided clocks CLK_D1, ..., CLK_Dn may be different from each other.

The signal applied to the memory device is generally synchronized with the rising edge of the clock. Thus, only the first pulse, i. E. The zeroth pulse, is needed to synchronize with the signal applied to the memory device and no other pulse within one period is needed. Therefore, even if the amplified first clock CLK_O is divided as shown in FIG. 3, the memory device 100 can operate normally. When dividing the amplified first clock CLK_O as shown in FIG. 3, the dividing clock can be formed only by removing a part of the pulses of the first clock CLK_O, so that the frequency dividers 105_2, ..., It can be configured simply and simply.

2 and 3, the first delay unit 105_1 and the 1/2 to 1 / n divider 105_2, ..., and 105_n additionally amplify the first clock CLK_O, if necessary, Amplification. Therefore, the amplitudes of the first through n-th frequency dividing clocks may be larger than the amplified first clock CLK_O.

1, n divided clocks CLK_D1, ..., CLK_Dn generated through the first delay unit 105_1 and the n-1 frequency dividers 105_2, ..., 105_n are supplied to n mux portions 107_1, ..., 107_n, respectively. That is, each of the n mux portions 107_1, ..., 107_n is connected to the first delay portion 105_1 and the n-1 frequency dividers 105_2, ..., 105_n one-to-one to form first through n-th divided clocks CLK_D1 , ..., CLK_Dn).

The n mux portions 107_1, ..., 107_n select one of the n divided clocks CLK_D1, ..., CLK_Dn. The selected frequency dividing clock S_CLKD is used to generate an internal command signal Internal_command in synchronization with the first signal C_S.

The n muxes 107_1, ..., 107_n are provided with n MRS (Mode Register Set) signals for selecting one frequency-divided clock. The first MRS signal MRS1 is supplied to the first delay unit 105_1 and the second through the n-th MRS signals MRS2, ..., MRSn are supplied to the first to Nth frequency dividers 105_2, ..., . Only one mux portion 107 is enabled according to the first to n-th MRS signals MRS1, ..., MRSn to output the selected divided clock S_CLKD. That is, one of the n muxes 107_1, ..., 107_n may be selected to select one of the first through n-th divided clocks CLK_D1, ..., CLK_Dn.

The n mux portions 107_1, ..., 107_n are connected to one flip-flop portion 109. [ The selected divided clock S_CLKD is provided to the flip-flop unit 109. [ The flip-flop unit 109 receives the selected divided clock S_CLKD and the first signal C_S and can synchronize them to generate a synchronized signal SMP_CS.

The first signal C_S is required to generate an internal command signal INT_CMD indicating operation within the memory device 100. Accordingly, the first signal C_S may include at least one of a chip select (CS), a chip enable (CE) signal, a clock enable (CKE) signal, and an on-die termination (ODT) signal. However, the present invention is not limited thereto. For example, the first signal C_S may be the address signal ADDR or the external command signal CMD. That is, the signal related to the operation of the memory device 100 may be the first signal C_S.

The first signal C_S input to the memory device 100 may be provided to the flip-flop unit 109 through the signal buffer 101_1. The signal buffer 101_1 may serve to amplify the first signal C_S in the same manner as the clock buffer 101_2.

On the other hand, the first signal C_S may be provided to the second delay unit 103_1 before being provided to the flip-flop unit 109. [ The second delay unit 103_1 delays the first signal C_S by a predetermined time. The first clock CLK applied to the memory device 100 may be delayed through the first delay unit 105_1 and the n-1 frequency dividers 105_2, ..., and 105_n. 2 and 3, the first clock CLK may be delayed by d through the first delay unit 105_1 and n-1 frequency dividers 105_2,..., 105_n. Accordingly, the selected divided clock S_CLKD provided to the flip-flop unit 109 may also be a clock delayed by a predetermined time as compared with the first clock CLK. The second delay unit 103_1 may delay the first signal C_S for a predetermined time to match the skew between the first signal C_S and the selected divided clock S_CLKD. Therefore, the second delay unit 103_1 can prevent the error of the flip-flop unit 109 due to the timing skew between the first signal C_S and the selected divided clock S_CLKD.

The synchronized signal SMP_CS in the flip-flop unit 109 may be provided to the command decoder unit 111. [ The command decoder unit 111 may additionally provide the synchronized signal SMP_CS and the synchronized command SMP_CMD to generate the internal command signal INT_CMD. The synchronized command SMP_CMD may be a command CMD that synchronizes the command CMD provided by the memory device with the selected divided clock S_CLKD. The command decoder unit 111 can generate the internal command signal INT_CMD by decoding the synchronized signal SMP_CS using the provided synchronized command SMP_CMD. Since the synchronized signal SMP_CS is provided to the command decoder unit 111 through a plurality of units, the third delay unit 103_2 may delay the synchronized command SMP_SMD by a predetermined time, Skew can be reduced.

Various devices in the memory device 100 can operate by the internal command signal INT_CMD generated by the command decoder unit 111. [

The effects of the present invention will be described with reference to Figs. 1 and 4. Fig. 4 is a block diagram of a memory device for explaining the effect of the present invention.

Referring to FIG. 4, a frequency divider 205 and a flip-flop unit 209 are additionally required to use the gear-down mode. Specifically, in order to make the frequency of the first clock CLK 1/2 times, the first clock CLK is provided to the half divider 205_2 through the clock buffer 201_2. The 1/2 frequency divider 205_2 generates a second divided clock CLK_D22 whose frequency is 1/2 of the first clock CLK. The generated second divided clock CLK_D22 is transferred from the first mux portion 203_2 to the second flip flop portion 209_2 when the first mux portion 203_2 is provided with the first MRS signal MRS2 in an enabled state / RTI > The second flip-flop unit 209_2 synchronizes the second clock CLK_D22 and the first signal C_S and provides the synchronized signal SMP_CS to the final mux 210. Then, the final mux 210 selects a necessary signal and provides it to the command decoder 111. [

If a plurality of gear-down modes are required and a plurality of frequency dividers are provided, the frequency divider 205, the mux portion 203, and the flip-flop portion 209 are required as much as the number of gear-down modes. For example, if five gear-down modes are required, five divider 205, mux 203, and flip-flop 209 are required. Since the first clock CLK is delayed by a predetermined time while passing through the divider 205 and the multiplexer 203, the flip-flop unit 209 outputs the divided clock CLK_D2 and the first signal C_S In order to synchronize, the first signal C_S passing through the signal buffer 201_1 must be delayed through the signal delay unit 213_1. In addition, since the first signal C_S is delayed, the first clock CLK applied to the first flip-flop unit 209_1 must also be delayed, and accordingly, the clock delay unit 201_2 is also required.

Further, in order to select one synchronized signal SMP_CS to be provided to the command decoder unit 211, a final mux unit 210 connected to the n flip-flop units 209 is additionally required.

As described above, when a plurality of gear-down modes are required, if the frequency divider 205 is added to the number of gear dots, the flip-flop section 209 and the mux section 203 and a final mux portion 210 for selecting the synchronized signal SMP_CS. As a result, as the number of gear-down modes increases, required parts and circuits increase, and timing skew tends to occur as the number of circuits increases.

However, like the memory device 100 according to an embodiment of the present invention, the first delay unit 105_1 and the (n-1) frequency dividers 105_2, ..., 105_n are connected to n mux portions 107 When the n mux portions 107 are connected to one flip-flop portion 109, the size of the memory device can be reduced and the timing skew can be eliminated.

Referring to FIG. 5, a memory device according to another embodiment of the present invention will be described. The description overlapping with the above description will be omitted, and differences will be mainly described. 5 is a block diagram of a memory device in accordance with another embodiment of the present invention.

Referring to FIG. 5, in contrast to the memory device 100 according to an embodiment of the present invention, the memory device 110 according to another embodiment of the present invention uses only one mux portion 107. The first delay unit 105_1 and the n-1 frequency dividers 105_2 to 105_n are all connected to one mux 107 and include a first delay unit 105_1 and n-1 frequency dividers 105_2 , ..., and 105_n are provided to the mux portion 107. The first to nth divided clocks CLK_D1, The mux portion 107 selects one of the first through n-th divided clocks CLK_D1 through CLK_Dn through the provided MRS signal MRS.

The mux portion 107 is connected to one flip-flop portion 109 and provides the selected divided clock S_CLKD to the flip-flop portion 109. [

Another memory device 110 in accordance with another embodiment of the present invention may reduce the size of the memory device 110 by using one mux portion 107.

6 is a block diagram illustrating a memory device according to another embodiment of the present invention.

6, the memory device 1000 includes a command control logic 1100, an address register unit 1200, a row address control unit 1300, a column address control unit 1400, A memory cell array 1500, a sense amp / write driver 1600, and a data I / O unit 1700. The memory I /

The command control logic 1100 is configured to generate an internal command signal INT_CMD. The command control logic 1100 may be configured to include a command register unit 1100 (COMMAND REGS) and a command decoder unit 111 (COMMAND DECODER). The command register unit 1100 receives the command signal CMD, the first signal C_S and the first clock CLK and can synchronize the signals with the selected divided clock S_CLKD. The command decoder unit 111 receives the synchronized command signal SMP_CMD and the synchronized signal SMP_CS from the command register unit 1110 and generates the internal command signal INT_CMD using the signals.

The command control logic 1100 may include a clock generator 1111. The clock generator 1111 outputs an internal clock signal (CLK_D1 in Fig. 1) having a first period time in the first gear-down mode and an internal clock signal CLK_D2. The clock generator 1111 may be provided substantially the same as the memory devices 100 and 110 except for the command decoder unit 111 in Figs. 1 and 5.

The address register unit 1200 receives the address signal ADDR and the bank address signal BA and is configured to synchronize the signals with the internal clock signal.

6, the clock generator 1111 except for the command decoder unit 111 is included as a component of the command register unit 1110. However, the memory device 1111 may be provided separately from the command register unit 1110 And may be included as some components of the command control logic 1100. [

The row address controller 1300 is configured to receive the address / bank address signal SMP_ADDR / BA synchronized with the internal command signal INT_CMD and to transmit the row address signal RAi to the memory cell array 1500.

The column address control unit 1400 is configured to receive the address / bank address signal SMP_ADDR / BA synchronized with the internal command signal INT_CMD and to transmit the column address signal CAi to the sense amplifier / write driver 1600 .

The memory cell array 1500 is configured to include a plurality of memory cells for storing data.

The sense amplifier / write driver 1600 is configured to read data from the selected memory cell in correspondence with the row address signal RAi and the column address signal CAi. The sense amplifier / write driver 1600 may write data to the selected memory cell.

The data input / output unit 1700 transmits and receives the data signal DQ to the external system and transmits the internal data signal DATAi for writing to the memory cell array 1500 to the sense amplifier / write driver 1600 And is configured to receive the internal data signal DATAi read from the memory cell array 1500 from the sense amplifier / write driver 1600.

The first signal C_S is needed to generate an internal command signal INT_CMD that indicates operation within the memory device 1000. Accordingly, the first signal C_S may include at least one of a chip select (CS), a chip enable (CE) signal, a clock enable (CKE) signal, and an on-die termination (ODT) signal. However, the present invention is not limited thereto.

When the first signal C_S is the CS signal and / or the CE signal, the memory device 1000 operates as follows. When the CS signal and / or the CE signal is applied, the internal command signal INT_CMD is generated using the CS signal and / or the CE signal. The internal command signal INT_CMD is supplied to the row address control unit 1300 and the column address control unit 1400. The row address control unit 1300 and the column address control unit 1400 are provided with an address / bank synchronized with the internal command signal INT_CMD, The row address signal RAi and the column address signal CAi are generated using the address signal SMP_ADDR / BA and provided to the sense amplifier / write driver 1600. The sense amplifier / write driver 1600 selects a memory cell corresponding to the row address signal RAi and the column address signal CAi from among the plurality of memory cells when the first signal C_S is a CS signal, If the signal C_S is the CE signal, the selected memory cell is enabled. After selecting and enabling one of the memory cells of the memory cell array 1500, data is written to the selected cell through the data input / output unit 1700 or the selected cell is read out through the data input / output unit 1700 can do.

When the first signal C_S is a CKE signal, the memory device 1000 operates as follows. When the CKE signal is applied, the internal command signal INT_CMD is generated using the CKE signal. The internal command signal INT_CMD is supplied to the row address control unit 1300 and the column address control unit 1400. The row address control unit 1300 and the column address control unit 1400 supply the internal command signal INT_CMD to the sense amplifier / (1600). The sense amplifier / write driver 1600 receives the internal command signal INT_CMD and enables a clock used for reading or writing data. Output the data to the memory cell array 1500 through the data input / output unit 1700 or read the selected cell and output the data through the data input / output unit 1700 after enabling the clock.

When the first signal C_S is the ODT signal, the memory device 1000 operates as follows. When the ODT signal is applied, the internal command signal INT_CMD is generated using the ODT signal. The internal command signal INT_CMD is supplied to the row address control unit 1300 and the column address control unit 1400. The row address control unit 1300 and the column address control unit 1400 supply the internal command signal INT_CMD to the sense amplifier / (1600). The sense amplifier / write driver 1600 receives the internal command signal INT_CMD and activates the ODT circuit outside the impedance matching. After activating the ODT circuit, the data can be written to the memory cell array 1500 through the data input / output unit 1700 or read out the selected cells and output the data through the data input / output unit 1700. Speed data I / O can be achieved through the ODT circuit.

Meanwhile, the ODT circuit is included in the sense amplifier / write driver 1600, but the present invention is not limited thereto. For example, the ODT circuit may be included in the data input / output unit 1700.

The first signal C_S is a CS signal, a CE signal, a CKE signal, and an ODT signal. However, the present invention is not limited thereto, It is easy to guess how the memory device 1000 operates in the case where the signal is a signal indicating an operation inside another memory device 1000. [

7 is a block diagram illustrating an electronic system including a memory device in accordance with some embodiments of the present invention.

7, the electronic system 2000 includes a controller 2100, an interface 2200, an input / output device 2300, a memory 2400, a power supply 2500 (POWER SUPPLY), and a bus 2600 (BUS).

The control device 2100, the interface 2200, the input / output device 2300, the storage device 2400, and the power supply device 2500 can be coupled to each other via the bus 2600. The bus 2600 corresponds to a path through which data is moved.

The control device 2100 can process data including at least one of a microprocessor, a microcontroller, and logic elements capable of performing similar functions.

The interface 2200 may perform functions to transmit data to or receive data from the communication network. The interface 2200 may be in wired or wireless form. Illustratively, the interface 2200 may include an antenna or a wired or wireless transceiver.

The input / output device 2300 can input and output data including a keypad and a display device.

The storage device 2400 may store data and / or instructions and the like. The memory devices 100, 110, and 1000 described with reference to FIGS. 1, 5, and 6 may be provided as some components of the storage device 2400.

The power supply device 2500 can convert the power input from the outside and provide it to each of the components 2100 to 2400.

In addition, memory devices 100, 110, and 1000 in accordance with some embodiments of the present invention may be implemented as a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA) Such as a computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, Among the electronic devices One of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or various components of an electronic device such as one of various components constituting a computing system &Lt; / RTI >

8 and 9, a method of driving a memory device according to an embodiment of the present invention will be described. 8 and 9 are flowcharts for explaining a method of driving a memory device according to an embodiment of the present invention.

First, referring to FIG. 8, the memory device is provided with a first clock (SlOO). Then, the first clock is supplied to n frequency dividers, and the first clock is divided to generate n frequency-divided clocks (S200). Here, n is a natural number. The 1/1 cycle of the n divider may be the first delay unit 105_1 of FIG. The first divided clock has the same frequency as the first clock, the second divided clock has a frequency that is one-half the frequency of the first clock, and the n-th divided clock, Lt; RTI ID = 0.0 > 1 / n < / RTI > times the frequency of the first clock. Each of the n divider units generates first to n < th > dividing clocks.

all the n frequency-divided clocks can have a duty less than 1/2, and the duty can be sequentially reduced from the first frequency-divided clock to the nth frequency-divided clock. Also, the first through n-th frequency dividing clocks may all have the same high level time. The duty has been described in detail, and further explanation will be omitted.

Next, one of the n number of frequency dividing clocks is selected (S300). The MRS signal is received and one of the n number of frequency dividing clocks can be selected. More specifically, referring to FIG. 9, n divided clocks are provided to the mux 107 (S310). Then, it provides the MRS signal to the mux 107. The mux section 107 selects one of the n number of frequency dividing clocks according to the provided MRS signal and outputs it (S320). The outputted selective dividing clock is provided to the flip-flop unit 109 connected to the mux unit 107 in one pass.

Next, referring again to FIG. 8, the selected divided clock is synchronized with the first signal (S400).

Synchronization can be performed in the flip-flop unit 109.

Subsequently, an internal command signal is generated using the synchronized signal (S500). The command decoder unit 111 provided with the synchronized signal can generate the internal command signal INT_CMD.

Referring to FIG. 10, a method of driving a memory device according to another embodiment of the present invention will be described. The description overlapping with the above description will be omitted, and differences will be mainly described.

10 is a flowchart illustrating a method of driving a memory device according to another embodiment of the present invention.

A method of driving a memory device according to another embodiment of the present invention differs from the method of driving a memory device according to an embodiment of the present invention in a method of selecting one of divided clocks. Specifically, referring to FIG. 10, n frequency dividers correspond one-to-one with n muxes. Accordingly, the first through n-th frequency dividing clocks generated by the n frequency dividers are provided to n mux portions 107 one by one (S311). The memory device is provided with n MRS signals, and each of the n muxes 107 receives one MRS signal. Only the mux portion 107 enabled via the MRS signal outputs the divided clock and provides it to the flip-flop portion 109. That is, one of n muxes 107 is selected by receiving n MRS signals, and one of n divided clocks is selected (S321).

The steps of a method or algorithm described in connection with the embodiments of the invention may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable recording medium It is possible. An exemplary recording medium is coupled to a processor, which is capable of reading information from, and writing information to, the recording medium. Alternatively, the recording medium may be integral with the processor. The processor and the storage medium may reside within an application specific integrated circuit (ASIC). The ASIC may reside within the user terminal. Alternatively, the processor and the storage medium may reside as discrete components in a user terminal.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100, 110: memory device 107:
1000: memory system 2000: electronic system

Claims

N-1 frequency dividers for dividing the first clock to generate the second to N-th frequency dividing clocks (here, n? 2);
A first delay unit for generating a first divided clock in which the first clock is delayed by the same time as the second divided clock to the n th divided clock;
A mux unit for receiving the first to n-th divided clocks and selecting one of the first to n-th divided clocks;
A flip-flop connected to the multiplexer for receiving and synchronizing the selected divided clock with the first signal; And
And a command decoder unit for decoding the synchronized signal provided from the flip-flop unit to generate an internal command signal.

The method according to claim 1,
Wherein the mux selects one of the first to n < th > divided clocks according to an MRS (Mode Register Set) signal.

The method according to claim 1,
Said mux portion comprising n mux portions,
Wherein each of the n muxes is connected to the first delay unit and the n-1 frequency dividers one-to-one.

The method according to claim 1,
And the duty ratio of the second divided clock to the n th divided clock is less than 1/2.

5. The method of claim 4,
Wherein the duty is sequentially reduced from the first divided clock to the n th divided clock.

6. The method of claim 5,
Wherein the clock levels of the first to n < th > divided clocks include a first level and a second level,
And the clock level is the first level within one period of the first to n < th > divided clocks.

Command control logic for generating an internal command signal;
A memory cell array including a plurality of memory cells;
And a sense amplifier / write driver for receiving the internal command signal to operate the memory cell array,
The command control logic,
N-1 frequency dividers for dividing the first clock to generate the second to N-th frequency dividing clocks,
A first delay unit for generating a first divided clock in which the first clock is delayed by the same time as the second divided clock to the n th divided clock,
A mux unit for receiving the first to n-th divided clocks and selecting one of the first to n-th divided clocks,
A flip-flop unit connected to the mux and receiving and synchronizing the selected divided clock with the first signal,
And a command decoder for decoding the synchronized signal provided from the flip-flop to generate the internal command signal.

8. The method of claim 7,
Wherein the first signal comprises a chip select (CS) signal,
And the sense amplifier / write driver selects one of the plurality of memory cells using the internal command signal generated by the first signal.

9. The method of claim 8,
Wherein the first signal further comprises a chip enable (CE) signal,
Wherein the sense amplifier / write driver enables the selected memory cell using the internal command signal generated by the first signal.

8. The method of claim 7,
The sense amplifier / write driver includes an on-die termination (ODT) device,
Wherein the first signal comprises an on-die termination (ODT) signal,
And the ODT circuit is enabled using the internal command signal generated by the first signal.