KR20140108951A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device comprises: a semiconductor substrate; an interlayer insulating film disposed on the semiconductor substrate; a DC plug passing through the interlayer insulating film; a first bit line structure disposed on the DC plug; a second bit line structure disposed on the interlayer insulating film and spaced apart from the first bit line structure; and a bit line lower protective film disposed between the interlayer insulating film and the second bit line structure and covering a lower surface of the second bit line structure.

Description

TECHNICAL FIELD The present invention relates to a semiconductor device and a fabrication method thereof.

The present invention relates to a semiconductor device including a storage contact plug and a method of manufacturing the same.

As the semiconductor device is highly integrated, the area of the storage contact hole is reduced. Various studies have been conducted to improve the reliability of the electrical connection between the storage contact plug located in the storage contact hole and the active region of the semiconductor substrate in the semiconductor device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which a lower portion of a storage contact hole located close to an upper surface of a semiconductor substrate is sufficiently widened and a manufacturing method thereof.

Another object of the present invention is to provide a semiconductor device in which a contact area between a storage contact plug and a conductive landing pad located under the storage contact plug is increased, and a method of manufacturing the same.

The problems to be solved by the present invention are not limited to the above-mentioned problems. Other tasks not mentioned herein will be apparent to those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; An interlayer insulating film located on the semiconductor substrate; A DC plug penetrating the interlayer insulating film; A first bit line structure located on the DC plug; A second bit line structure located on the interlayer dielectric film and spaced apart from the first bit line structure; And a bit line lower protective film located between the interlayer insulating film and the second bit line structure and covering the lower surface of the second bit line structure.

The horizontal distance of the bit line lower protective film may be larger than the horizontal distance of the interlayer insulating film.

The semiconductor device may further include a bit line spacer positioned on a side of the second bit line structure. The bit line lower protective film may include the same material as the bit line spacers.

The bit line lower protective film may be harder than the interlayer insulating film.

The level of the lower surface of the bit line spacer may be the same as the level of the lower surface of the bit line lower protective film.

The semiconductor device comprising: a DC spacer positioned on a side of the DC plug; an insulating fence positioned between the semiconductor substrate and the interlayer dielectric; a conductive landing pad positioned between the DC spacer and the insulating fence; And a storage contact plug located in the storage device. The storage contact plug may directly contact the upper surface of the conductive landing pad and the lower surface of the bit line lower protective layer.

The top surface of the conductive landing pad may include a pad recess region. The horizontal distance of the contact surface between the conductive landing pad and the storage contact plug may be wider than the horizontal distance of the pad recess region.

The storage contact plug may be in direct contact with the entire top surface of the conductive landing pad.

The horizontal distance of the insulating fins may be larger than the horizontal distance of the interlayer insulating film.

The storage contact plug may be in direct contact with the upper surface of the insulating fence.

According to the technical idea of the present invention, the lower surface of the bit line structure located on the interlayer insulating film can be covered with the bit line lower protective film. Accordingly, in the semiconductor device and the manufacturing method thereof according to the technical idea of the present invention, the interlayer insulating film covering the upper surface of the conductive landing pad located under the storage contact plug can be removed without damaging the bit line structure. That is, in the semiconductor device and the manufacturing method thereof according to the technical idea of the present invention, the upper surface of the conductive landing pad vertically overlapping with the bit line structure by the storage contact hole can be exposed. Therefore, the reliability of the semiconductor device and the manufacturing method thereof according to the technical idea of the present invention can be improved.

1 is a layout view showing a semiconductor device according to an embodiment of the present invention.
2A is a cross-sectional view taken along the line I-I 'in FIG.
2B is a cross-sectional view taken along line II-II 'of FIG.
3A and 3B are cross-sectional views showing a semiconductor device according to another embodiment of the present invention.
4 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
5A to 18A and 5B to 18B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
19 is a block diagram showing a memory module including a semiconductor device according to the technical idea of the present invention.
20 is a configuration diagram showing a semiconductor module including a semiconductor device according to the technical idea of the present invention.
21 is a block diagram showing a mobile system including a semiconductor device according to the technical idea of the present invention.
22 is a configuration diagram showing a mobile device including a semiconductor device according to the technical idea of the present invention.
23 is a configuration diagram showing an electronic system including a semiconductor device according to the technical idea of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the drawings, the same reference numerals denote the same components throughout the specification. In the drawings, the lengths and the thicknesses of layers or regions may be exaggerated for convenience. In addition, when the first component is described as being on the second component, it is preferable that the first component is located on the upper side in direct contact with the second component, And the third component is located between the second components.

Here, the terms first, second, etc. are used for describing various components and are used for the purpose of distinguishing one component from another component. However, the first component and the second component may be arbitrarily named according to the convenience of the person skilled in the art without departing from the technical idea of the present invention.

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. For example, an element represented in singular form includes a plurality of elements unless the context clearly dictates a singular number. Also, in the specification of the present invention, the terms such as " comprises "or" having ", and the like, designate the presence of stated features, integers, steps, operations, elements, But do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

In addition, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the related art and, unless expressly defined in the specification of the present invention, are intended to mean either an ideal or an overly formal meaning It is not interpreted.

(Example)

1 is a layout view showing a semiconductor device according to an embodiment of the present invention. 2A is a cross-sectional view taken along the line I-I 'in FIG. 2B is a cross-sectional view taken along line II-II 'of FIG.

1, 2A and 2B, a semiconductor device according to an embodiment of the present invention includes a semiconductor substrate 100, gate patterns 110, conductive landing pads 121, insulating fins 122, 130, a bit line lower protective layer 140, DC plugs 150p, bit line structures 160f, and storage contact plugs 180. Referring to FIG. The gate patterns 110 may extend in a first direction X. The bit line structures 160f may extend in a second direction Y. [ The second direction (Y) may be perpendicular to the first direction (X). The plane formed by the first direction X and the second direction Y may be parallel to the upper surface of the semiconductor substrate 100.

The semiconductor substrate 100 may include a silicon wafer or an SOI (Silicon On Insulator) substrate. The semiconductor substrate 100 may include an active region ACT and a field region FLD.

The active region ACT may intersect the gate patterns 110 and the bit line structures 160f. The active region ACT may not be parallel to the gate patterns 110 or the bit line structures 160f. For example, the active area ACT may be in the form of a bar extending diagonally. The active region (ACT) may include a conductive dopant. For example, the active region ACT may comprise phosphorus (P) or boron (B).

The field region FLD may define the active region ACT. The field region FLD may include a field trench 101t and a field insulator 101. [

The field trench 101t may surround the active area ACT. The field trench 101t may extend in the third direction Z. [ The third direction Z may be perpendicular to the upper surface of the semiconductor substrate 100. The field trench 101t may extend vertically from the upper surface of the semiconductor substrate 100 to the lower surface of the semiconductor substrate 100. [

The field insulator 101 may be located in the field trench 101t. The field trench 101t may be completely filled with the field insulator 101. The level of the top surface of the field insulator 101 may be the same as the level of the top surface of the semiconductor substrate 100. The active area (ACT) may be defined by the field insulator (101). The field insulator 101 may include an insulating material. For example, the field insulator 101 may include silicon oxide.

The gate patterns 110 may cross the active area ACT and the field area FLD. Each of the gate patterns 110 may be spaced apart in the second direction (Y). Each of the gate patterns 110 may be parallel to each other. Each of the gate patterns 110 may function as a word line.

The semiconductor device according to an embodiment of the present invention may further include gate trenches 110t. The gate trenches 110t may be located within the semiconductor substrate 100. [ The gate trenches 110t may extend in the first direction X. [ The gate trenches 110t may pass through the active region ACT in the first direction X. [ The gate trenches 110t may be completely filled with the gate patterns 110. [ The gate patterns 110 may be located in the semiconductor substrate 100.

The level of the upper surface of the gate patterns 110 may be the same as the level of the upper surface of the semiconductor substrate 100. The lowest level of the gate patterns 110 may be higher than the lowest level of the field trench 101t. The lowest level of the field trench 101t may be lower than the lowest level of the gate trenches 110t.

Each of the gate patterns 110 may include a gate insulating layer 111, a gate barrier layer 113, a gate electrode 115, and a gate capping layer 117.

The gate insulating layer 111 may be located along the surface of the corresponding gate trench 110t. The thickness of the gate insulating film 111 may be constant. The gate insulating layer 111 may include an oxide. For example, the gate insulating layer 111 may include oxidized silicon.

The gate barrier film 111 may be partially located on the upper surface of the gate insulating film 111. [ The gate barrier film 111 may be located near the bottom of the gate trench 110t. The gate barrier film 111 may include a refractory metal. For example, the gate barrier film 111 may include Ti, TiN, Ta, TaN or WN.

The gate electrode 115 may be located on the upper surface of the gate barrier film 113. The gate barrier film 113 may be located between the gate insulating film 111 and the gate electrode 115. The gate electrode 115 may partially fill the gate trench 110t. For example, the gate electrode 115 may fill the bottom of the gate trench 110t. The gate electrode 115 may include a conductive material. For example, the gate electrode 115 may comprise a metal, a metal silicide, or a doped polycrystalline silicon.

The gate capping layer 117 may be located on the gate electrode 115. The gate capping layer 117 may be located on the upper surface of the gate electrode 115. The gate capping layer 117 may completely fill the gate trench 110t. The level of the upper surface of the gate capping layer 117 may be the same as the level of the upper surface of the semiconductor substrate 100. The gate capping layer 117 may include an insulating material. For example, the gate capping layer 117 may comprise silicon nitride.

The conductive landing pads 121 may be located on the active area ACT and the field area FLD. Each of the conductive landing pads 121 may be electrically connected to the active region ACT. The lower surface of each conductive landing pad 121 may be in direct contact with the upper surface of the active area ACT. The upper surface of each of the conductive landing pads 121 may include a pad recess region 121r.

The conductive landing pads 121 may include a conductive material. The conductive landing pads 121 may include the same material as the semiconductor substrate 100. For example, the conductive landing pads 121 may comprise monocrystalline silicon formed by Selective Epitaxial Growth (SEG).

The insulating fins 122 may be located on the semiconductor substrate 100. The insulating fins 122 may be located between the conductive landing pads 121. Each conductive landing pad 121 may be surrounded by the insulating fence 122. Each of the conductive landing pads 121 may be electrically insulated from adjacent conductive landing pads 121 by the insulating fins 122.

The level of the upper surface of the insulating fins 122 may be the same as the level of the upper surface of the conductive landing pads 121. The insulative fins 122 may extend into the field insulator 101 in the field region FLD. The horizontal distance of the insulating fins 122 in the first direction X at the lower portion of the bit line structures 160f may be smaller than the horizontal distance of the field insulating material 101 in the first direction X. [ The lowest level of the insulating fins 122 under the bit line structures 160f may be lower than the level of the upper surface of the semiconductor substrate 100. [

The insulating fins 122 may include an insulating material. The insulating fins 122 may have an etch rate different from that of the field insulator 101. The insulating fins 122 may have an etch selectivity with the field insulator 101. For example, the insulating fins 122 may comprise silicon nitride.

The semiconductor device according to the embodiment of the present invention may further include the fuse through holes 122h. The fins through holes 122h may pass through the insulating fins 122. [ The fence through holes 122h may be located between the conductive landing pads 121. [ The fuse through holes 122h may be located below the bit line structure 160f. The fuse through holes 122h may expose the active area ACT located below the bit line structure 160f.

The horizontal distance of the fins through holes 122h in the first direction X may be greater than the horizontal distance of the bit line structure 160f in the first direction X. [ The horizontal distance in the first direction X of the fence through holes 122h is greater than the horizontal distance in the first direction X of the active area ACT exposed by the fuse through holes 122h . The horizontal distance of the fence through holes 122h in the second direction Y may be larger than the horizontal distance of the first direction X of the fuse through holes 122h. Each fuse through hole 122h may expose the active area ACT located below the bit line structure 160f and the field area FLD surrounding the active area ACT.

The semiconductor device according to an embodiment of the present invention may further include substrate recess regions 100r. The substrate recess regions 100r may be located on the upper surface of the semiconductor substrate 100. The lowest level of the substrate recess regions 100r may be lower than the level of the upper surface of the semiconductor substrate 100. [ The lowest level of the substrate recess regions 100r may be higher than the level of the upper surface of the gate electrode 115. [

The substrate recess regions 100r may be located below the fuse through holes 122h. Each of the fuse through holes 122h may expose the bottom surface of the substrate recess region 100r. The horizontal distance of each substrate recess region 100r in the first direction X may be the same as the horizontal distance of the corresponding fins through hole 122h in the first direction X. [ The horizontal distance of each substrate recess region 100r in the second direction Y may be the same as the horizontal distance of the corresponding fins through hole 122h in the second direction Y. [ The area of each substrate recess region 100r may be the same as the area of the corresponding fuse through hole 122h.

The interlayer insulating layer 130 may be located on the insulating fins 122. The interlayer insulating layer 130 may expose the conductive landing pads 121. The horizontal distance of the interlayer insulating layer 130 in the first direction X under the bit line structures 160f may be smaller than the horizontal distance of the insulating fins 122 in the first direction X. [ The interlayer insulating layer 130 may expose the entire upper surface of the conductive landing pads 121.

The interlayer insulating layer 130 may include an insulating material 130. The interlayer insulating layer 130 may have an etch rate different from that of the insulating fins 122. The interlayer insulating layer 130 may have an etch selectivity with the insulating fins 122. For example, the interlayer insulating layer 130 may include silicon oxide. The insulating fins 122 may be more dense than the interlayer insulating layer 130. The insulating fins 122 may be harder than the interlayer insulating layer 130.

The interlayer insulating layer 130 may include lower through holes 130h. The lower through holes 130h may be located on the upper portion of the fuse through holes 122h. The lower through holes 130h may expose the bottom surface of the substrate recess regions 100r. The horizontal distance of each of the lower through holes 130h in the second direction Y may be the same as the horizontal distance of the corresponding fins through hole 122h in the second direction Y. [

The bit line lower protective layer 140 may be located on the interlayer insulating layer 130. The bit line lower protective layer 140 may be located on the lower surface of the bit line structure 160f. The bit line lower protective layer 140 may cover the lower surface of the bit line structure 160f.

The bit line lower protective layer 140 may have an etch rate different from that of the interlayer insulating layer 130. The bit line lower protective layer 140 may have an etch selectivity with the interlayer insulating layer 130. The bit line lower protective layer 140 may include the same material as the insulating fins 122. For example, the bit line lower protective film 140 may include silicon nitride. The bit line lower protective layer 140 may be more dense than the interlayer insulating layer 130. The bit line lower protective layer 140 may be harder than the interlayer insulating layer 130.

The horizontal distance of the bit line lower protective layer 140 in the first direction X may be larger than the horizontal distance of the interlayer insulating layer 130 in the first direction X at the lower portion of the bit line structure 160f . The horizontal distance of the bit line lower protective layer 140 in the first direction X may be greater than the horizontal distance of the insulating fins 122 in the first direction X at the lower portion of the bit line structure 160f .

The bit line lower protective layer 140 may include upper contact holes 140h. The upper contact holes 140h may be positioned on the upper portion of the lower through holes 130h. The upper contact holes 140h may expose the bottom surface of the substrate recess regions 100r. The horizontal distance in the second direction Y of each upper contact hole 140h may be the same as the horizontal distance in the second direction Y of the corresponding lower through hole 130h.

The substrate recess regions 100r, the fuse through holes 122h, the lower through holes 130h and the upper through holes 140h may constitute the DC contact holes 150h. Each of the DC contact holes 150h may be formed in the substrate recess region 100r, the puddle through hole 122h, the lower through hole 130h, and the upper through hole 140h. Each side wall of each of the DC contact holes 150h is connected to a side wall of the substrate recess region 100r aligned in the third direction Z, a side wall of the corresponding fuse through hole 122h, a corresponding lower through hole 130h, And a sidewall of the upper through-hole 140h. The bottom surface of each of the DC contact holes 150h may be the bottom surface of the corresponding substrate recess region 100r. The DC contact holes 150h may expose the active area ACT that is vertically overlapped with the bit line structures 160f.

The DC plugs 150p may be positioned within the DC contact holes 150h. Each of the DC contact holes 150h may be filled with a corresponding DC plug 150p. The DC plugs 150p may pass through the interlayer insulating layer 130. [ The horizontal distance of each DC plug 150p in the first direction X may be equal to the horizontal distance of the first direction X of the corresponding substrate recess region 100r. The horizontal distance of each DC plug 150p in the second direction Y may be equal to the horizontal distance of the substrate recess region 100r in the second direction Y. [

The level of the upper surface of the DC plugs 150p may be the same as the level of the upper surface of the bit line lower protective layer 140. [ The lowest level of the DC plugs 150p may be equal to the lowest level of the DC contact holes 150h. The lowest level of the DC plugs 150p may be the same as the level of the bottom surface of the substrate recess regions 100r. The lowest level of the DC plugs 150p may be lower than the level of the upper surface of the semiconductor substrate 100.

Each of the DC plugs 150p may be electrically connected to the active region ACT located in the corresponding substrate recess region 100r. Each DC plug 150p may be in direct contact with the top surface of the active area ACT located in the substrate recess region 100r. The DC plugs 150p may include a conductive material. For example, the DC plugs 150p may comprise a metal, a metal silicide, or doped silicon.

The semiconductor device according to the embodiment of the present invention may further include DC spacers 150s. The DC spacers 150s may be located on the side of the DC plugs 150p. The DC spacers 150s may electrically insulate the DC plugs 150p from the conductive landing pads 121. [ Each of the DC spacers 150s may be positioned between a sidewall of the corresponding DC contact hole 150h and a corresponding DC plug 150p. Each of the DC spacers 150s may directly contact a sidewall of the corresponding DC contact hole 150h. The conductive landing pads 121 may be located between the insulating fins 122 and the DC spacers 150s.

The DC spacers 150s may partly cover the sidewalls of the DC contact holes 150h. The highest level of the DC spacers 150s may be lower than the highest level of the sidewalls of the DC contact holes 150h. The highest level of the DC spacers 150s may be higher than the level of the upper surface of the conductive landing pads 121. [

The DC spacers 150s may include an insulating material. The DC spacers 150s may have an etch rate different from that of the interlayer insulating layer 130. The DC spacers 150s may have an etch selectivity with the interlayer dielectric 130. The DC spacers 150s may include the same material as that of the bit line lower protective layer 140. For example, the DC spacers 150s may comprise silicon nitride.

The bit line structures 160f may be located on the upper surface of the bit line lower protective layer 140 and the DC plug 150p. Each of the bit line structures 160f may be spaced apart in the first direction X. [ Each bit line structure 160f may be parallel to each other. Each of the bit line structures 160f may function as a bit line.

The bit line structures 160f may traverse the top of the DC plugs 150p. Each of the bit line structures 160f may include first structure regions 160a and second structure regions 160b.

The first structure regions 160a may refer to the bit line structure 160f located on top of the DC plugs 150p. The first structure region 160a may be electrically connected to the DC plugs 150p. The first structure region 160a may be in direct contact with the upper surface of the DC plugs 150p.

The level of the lower surface of the first structure regions 160a may be the same as the level of the upper surface of the DC plugs 150p. The upper surface of the DC plugs 150p may be in a dishing shape. The lowest level of the first structure regions 160a may be lower than the level of the upper surface of the bit line lower protective film 140. [

And the second structure regions 160b may refer to the bit line structure 160f located on the bit line lower protective layer 140. [ The second structure regions 160b may be in direct contact with the upper surface of the bit line lower protective layer 140. The level of the lower surface of the second structure regions 160b may be the same as the level of the upper surface of the bit line lower protective layer 140. The level of the lower surface of the second structure regions 160b may be higher than the lowest level of the first structure regions 160a.

The second structure regions 160b may be located between the first structure regions 160a. Each of the second structure regions 160b may connect between the first structure regions 160a. The bit line structures 160f may be formed by repeating the first structure regions 160a and the second structure regions 160b. The first structure regions 160a of the bit line structure 160f may be positioned in parallel with the second structure regions 160b of the adjacent bit line structure 160f in the second direction Y. [

Each of the bit line structures 160f may include a lower bit line barrier pattern 161p, an upper bit line barrier pattern 162p, a bit line electrode pattern 163p, and a bit line capping pattern 164p.

The lower bit line barrier pattern 161p may directly contact the upper surface of the bit line lower protective layer 140 and the upper surface of the DC plugs 150p. The horizontal distance of the lower bit line barrier pattern 161p in the first direction X may be smaller than the horizontal distance of the first direction X of the DC contact holes 150h. The horizontal distance of the lower bit line barrier pattern 161p in the first direction X may be equal to the horizontal distance of the bit line lower protective layer 140 in the first direction X. [ The lower bit line barrier pattern 161p may include a metal silicide. For example, the lower bit line barrier pattern 161p may comprise tungsten silicide.

The upper bit line barrier pattern 162p may be located on the upper surface of the lower bit line barrier pattern 161p. The horizontal distance of the upper bit line barrier pattern 162p in the first direction X may be the same as the horizontal distance of the lower bit line barrier pattern 161p in the first direction X. [ The upper bit line barrier pattern 162p may include a metal or a metal compound. For example, the upper bit line barrier pattern 162p may include Ti, TiN, Ta, TaN or WN.

The bit line electrode pattern 163p may be positioned on the upper surface of the upper bit line pattern 162p. The horizontal distance of the bit line electrode pattern 163p in the first direction X may be equal to the horizontal distance of the upper bit line barrier pattern 162p in the first direction X. [ The bit line electrode pattern 163p may include a conductive material. The bit line electrode pattern 163p may include the same material as the upper bit line barrier pattern 162p. For example, the bit line electrode pattern 163p may include tungsten.

The bit line capping pattern 164p may be located on the upper surface of the bit line electrode pattern 163p. The horizontal distance of the bit line capping pattern 164p in the first direction X may be equal to the horizontal distance of the bit line electrode pattern 163p in the first direction X. [ The bit line capping pattern 164p may comprise an insulating material. For example, the bit line capping pattern 164p may comprise silicon nitride.

The semiconductor device according to an embodiment of the present invention may further include bit line spacers 170s. The bit line spacers 170s may be located on the sides of the bit line structures 160f. The bit line spacers 170s may include first spacer regions 171s and second spacer regions 172s.

The first spacer regions 171s may refer to the bit line spacers 170s located on the sides of the first structure regions 160a. The first spacer regions 171s may extend in the third direction Z along the sides of the DC plugs 150p. The level of the lower surface of the first spacer regions 171s may be lower than the level of the upper surface of the DC plugs 150p. The level of the lower surface of the first spacer regions 171s may be lower than the level of the lower surface of the bit line lower protective film 140. The first spacer regions 171s may directly contact the DC spacers 150s. For example, a side upper portion of the DC plugs 150p may be covered by the first spacer regions 171s.

The semiconductor device according to the embodiment of the present invention may further include a plug surface insulating film 150f. The plug surface insulating layer 150f may be positioned between the DC plugs 150p and the first spacer regions 171s. The plug surface insulating film 150f may include an oxide. For example, the plug surface insulating film 150f may include silicon oxide.

The second spacer regions 172s may refer to the bit line spacers 170s located on the sides of the second structure regions 160b. The second spacer regions 172s may extend along the side surfaces of the bit line lower protective film 140. [ The second spacer regions 172s may cover the side surfaces of the bit line lower protective layer 140. [ The level of the lower surface of the second spacer regions 172s may be equal to the level of the lower surface of the bit line lower protective film 140. [ The level of the lower surface of the second spacer regions 172s may be higher than the level of the lower surface of the first spacer regions 171s.

The storage contact plugs 180 may be located between the bit line structures 160f. The storage contact plugs 180 may be located between the bit line spacers 170s. The storage contact plugs 180 may be in direct contact with the bit line spacers 170s.

The storage contact plugs 180 may be in direct contact with the top surface of the conductive landing pad 121. The storage contact plugs 180 may be located within the pad recess region 121r of the conductive landing pad 121. [ The lowest level of the storage contact plugs 180 may be the same as the level of the bottom surface of the pad recess region 121r.

The storage contact plugs 180 may extend between the second spacer regions 172s and the interlayer insulating layer 130. The horizontal distance of the contact surface between the conductive landing pads 121 and the storage contact plugs 180 in the first direction X is determined by the horizontal distance X in the first direction X of the pad recess region 121r, Can be bigger. The storage contact plugs 180 may be in direct contact with the entire top surface of the conductive landing pads 121. The storage contact plugs 180 may be in direct contact with the lower surface of the second spacer regions 172s. The storage contact plugs 180 may be in direct contact with the lower surface of the bit line lower protective layer 140. The storage contact plugs 180 may be in direct contact with the upper surface of the insulating fins 122.

In the semiconductor device according to the embodiment of the present invention, the interlayer insulating film may expose the entire upper surface of the conductive landing pads 121. Accordingly, the semiconductor device according to the embodiment of the present invention can directly contact the entire upper surface of the conductive landing pads 121 with the storage contact plugs 180. Therefore, in the semiconductor device according to the embodiment of the present invention, the reliability of the electrical connection between the storage contact plugs 180 and the conductive landing pads 121 can be improved.

3A and 3B are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention.

3A and 3B, a semiconductor device according to an embodiment of the present invention includes a semiconductor substrate 100, gate patterns 110, conductive landing pads 121, an insulating fins 122, an interlayer insulating layer 130, The bit line lower protective layer 140, the DC contact hole 150h, the DC plugs 150p, the DC spacers 150s, the bit line structures 160f, the bit line spacers 170s, (180).

The semiconductor substrate 100 may include an active region ACT and a field region FLD. The field region FLD may include a field trench 101t and a field insulator 101. [ The bit line structures 160f may include first structure regions 160a and second structure regions 160b. The bit line spacers 170s may include first spacer regions 171s and second spacer regions 172s.

The horizontal distance of the interlayer insulating layer 130 in the first direction X at the lower portion of the second structure regions 160b may be greater than the horizontal distance of the insulating fins 122 in the first direction X . The storage contact plugs 180 may be spaced apart from the insulating fins 122. The horizontal distance of the interlayer insulating layer 130 in the first direction X at the lower portion of the second structure regions 160b is smaller than the horizontal distance of the bit line lower protective layer 140 in the first direction X . The storage contact plugs 180 may be in direct contact with the lower surface of the bit line lower protective layer 140.

4 is a flow chart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 5A to 18A and 5B to 18B are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to Figs. 1, 2A, 2B, 4, 5A to 18A, and 5B to 18B. 4, 5A and 5B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming gate patterns 110 (110) in a semiconductor substrate 100 including an active area (ACT) and a field area (S110). ≪ / RTI >

A step S110 of forming the gate patterns 110 in the semiconductor substrate 100 includes a step of preparing the semiconductor substrate 100 and a step of forming the active region ACT and the field region 100 in the semiconductor substrate 100, Forming the gate insulating film 111 in the gate trenches 110t; forming the gate insulating film 111 in the gate trenches 110t; A step of forming a gate electrode film 115 on the gate barrier film 113 and a step of forming a gate capping layer 117 on the upper surface of the gate electrode pattern 115 ) May be formed.

Wherein the step of forming the active region ACT and the field region FLD in the semiconductor substrate 100 includes the steps of forming a field trench 101t in the semiconductor substrate 100 and forming the field trench 101t in the field trench 101t, And forming the insulator 101. [

4A, 6A and 6B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming conductive landing pads 121 and insulating fins 122 on a semiconductor substrate 100 ).

The step of forming the conductive landing pads 121 and the insulating fins 122 on the semiconductor substrate 100 may include the steps of forming the insulating fins 122 on the semiconductor substrate 100, And forming the conductive landing pads 121 between the insulating fins 122.

Referring to FIGS. 4, 7A and 7B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes forming an interlayer insulating layer 130 and a bit line lower protective layer 130 on the conductive landing pads 121 and the insulating fins 122, (S130) of forming the second electrode layer 140.

The step S130 of forming the interlayer insulating layer 130 and the bit line lower protective layer 140 may be performed on the upper surface of the conductive landing pads 121 and the upper surface of the insulating fins 122 130 and a step of forming the bit line lower protective layer 140 on the upper surface of the interlayer insulating layer 130.

The process of forming the bit line lower protective film 140 on the upper surface of the interlayer insulating film 130 may include forming the bit line lower protective film 140 with a material having an etch rate different from that of the interlayer insulating film 130 . ≪ / RTI >

4, 8A and 8B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include a step S140 of forming DC through holes 150h on the semiconductor substrate 100 .

The step S140 of forming the DC through holes 150h on the semiconductor substrate 100 may include a process of forming the upper through holes 140h, a process of forming the lower through holes 130h, Forming the holes 122h, and forming the substrate recess regions 100r.

The process of forming the upper through holes 140h may include a process of etching the bit line lower protective layer 140. [ The process of forming the lower through holes 130h may include a process of etching the interlayer insulating layer 130. [ The process of forming the fuse through holes 122h may include a process of etching the conductive landing pads 121. The step of forming the substrate recessed regions 100r may include a step of recessing the semiconductor substrate 100. [

Referring to FIGS. 4, 9A and 9B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming a DC spacer layer 151 on the semiconductor substrate 100 (S150).

The step (S150) of forming the DC spacer layer 151 may include a step of covering the sidewalls and the bottom surface of the DC contact holes 150h with the DC spacer layer 151.

4, 10A and 10B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include a step S160 of forming DC spacers 150s in the DC contact holes 150h .

The step (S160) of forming the DC spacers 150s in the DC contact holes 150h may include anisotropically etching the DC spacer layer 151.

4, 11A and 11B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include a step of forming a DC plug layer 150 on the semiconductor substrate 100 (S170).

The step of forming the DC plug layer 150 on the semiconductor substrate 100 may include a step of filling the DC contact hole 150h with the DC plug layer 150. [

4, 12A and 12B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include a step S180 of forming a DC plug 150p in the DC contact hole 150h.

The step of forming the DC plug 150p in the DC contact hole 150h includes a step of planarizing the DC plug layer 150 such that the upper surface of the bit line lower protective layer 140 is exposed . The step of planarizing the DC plug layer 150 may include a chemical mechanical polishing (CMP) process.

4, 13A and 13B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include a step (S190) of forming a bit line structure layer 160 on the semiconductor substrate 100 .

The step of forming the bit line structure layer 160 on the semiconductor substrate 100 may include forming a bit line structure layer 160 on the upper surface of the bit line lower protective layer 140 and the upper surface of the DC plug 150p, Forming an upper bit line barrier layer (162) on the upper surface of the lower bit line barrier layer (161), forming a lower bit line barrier layer (162) on the upper surface of the upper bit line barrier layer Forming a bit line electrode layer 163 on the bit line electrode layer 163 and forming a bit line capping layer 164 on the bit line electrode layer 163.

4, 14A and 14B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include a step S200 of forming bit line structures 160f on the semiconductor substrate 100 .

A step S200 of forming the bit line structures 160f on the semiconductor substrate 100 includes a step of etching the bit line capping layer 164 to form a bit line capping pattern 164p, Forming a bit line electrode pattern 163p by etching the electrode layer 163; etching the upper bit line barrier layer 162 to form an upper bit line barrier pattern 162p; And forming a lower bit line barrier pattern 161p by etching the lower bit line barrier pattern 161.

The process of forming the lower bit line barrier pattern 161p may include a process of partially recessing the upper portion of the DC plugs 150p. The process of partially recessing the top of the DC plugs 150p may include exposing the top of the DC spacers 150s.

Each of the bit line structures 160f includes first structure regions 160a located on top of the DC plugs 150p and second structure regions 160b located on the bit line lower protective layer 140 160b.

4, 15A and 15B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include a step S210 of forming a plug surface insulating film 150f on the surface of the DC plugs 150p have.

The step of forming the plug surface insulating film 150f (S210) may include a step of oxidizing the surface of the exposed DC plugs 150p.

4, 16A and 16B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include a step S220 of forming a bit line spacer layer 170 on the semiconductor substrate 100 .

The step S220 of forming the bit line spacer layer 170 may include a step of covering the upper surface of the plug surface insulating layer 150f with the bit line spacer layer 170. [

4, 17A and 17B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes the steps of forming bit line spacers 170s and a storage contact hole 180h on the semiconductor substrate 100 S230).

The step of forming the bit line spacers 170s and the storage contact holes 180h includes a step of forming bit line spacers 170s on the side surfaces of the bit line structures 160f, And forming the storage contact hole 180h through the insulating film 130. [

The step S230 of forming the bit line spacers 170s may include a step of etch-backing the bit line spacer layer 170. [ Each of the bit line spacers 170s includes first spacer regions 171s positioned on the sides of the first structure regions 160a and first spacer regions 171s located on the sides of the second structure regions 160b. 2 spacer regions 172s.

The process of forming the storage contact hole 180h may include a process of etching the interlayer insulating layer 130 on the upper surface of the conductive landing pads 121 and a process of forming the pad recess region 121r. have.

The step of forming the pad recess region 121r may include a step of forming the pad recess region 121r on the upper surface of the conductive landing pads 121. [ The step of forming the pad recess region 121r may be performed simultaneously with the step of etching the interlayer insulating layer 130.

Referring to FIGS. 4, 18A and 18B, a method of fabricating a semiconductor device according to an embodiment of the present invention may include a step S240 of recessing the side surface of the interlayer insulating layer 130.

The step S240 of recessing the side surface of the interlayer insulating layer 130 may include a step of increasing the area of the lower region of the storage contact hole 180h. The step S240 of recessing the side surface of the interlayer insulating layer 130 may include a step of removing the interlayer insulating layer 130 covering the upper surface of the conductive landing pads 121. [ The step S240 of recessing the side surface of the interlayer insulating layer 130 may include a step of partially removing the interlayer insulating layer 130 covering the lower surface of the bit line lower protective layer 130. [ The step S240 of recessing the side surface of the interlayer insulating layer 130 may include a step of partially removing the interlayer insulating layer 130 filling the gap between the bit line structure 160f and the insulating fins 122 have.

The step S240 of recessing the side surface of the interlayer insulating layer 130 may include an isotropic etching process. For example, the step S240 of recessing the side surface of the interlayer insulating layer 130 may include a wet etching process.

1, 2A, 2B and 4, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes a step S250 of forming the storage contact plug 180 on the semiconductor substrate 100 .

The step of forming the storage contact plug 180 may include a step of covering the upper surface of the conductive landing pads 121 with the storage contact plug 180. The process S250 of forming the storage contact plug 180 may be performed by using the lower surface of the bit line lower protective film 130 exposed by the interlayer insulating film 130 and the lower surface of the insulating fins 122 ) On the upper surface of the substrate.

19 is a block diagram showing a memory module including a semiconductor device according to the technical idea of the present invention.

Referring to FIG. 19, the memory module 1000 may include a module substrate 1100, semiconductor packages 1200, and module contact terminals 1300. The module substrate 1100 may be a system board. The semiconductor packages 1200 may be disposed side by side on the module substrate 1100. The semiconductor packages 1200 may be coated on both sides of the module substrate 1100. The module contact terminals 1300 may be formed alongside one edge of the module substrate 1100. The module contact terminals 1300 may be electrically connected to the semiconductor packages 1200.

The semiconductor packages 1200 may include semiconductor devices according to various embodiments of the present invention. Therefore, in the memory module 1000, the reliability of the semiconductor packages 1200 can be improved.

20 is a configuration diagram showing a semiconductor module including a semiconductor device according to the technical idea of the present invention.

Referring to FIG. 20, the semiconductor module 2000 may include a module substrate 2100, memories 2200, a microprocessor 2300, and input / output terminals 2400. The memories 2200, the microprocessor 2300 and the input / output terminals 2400 may be mounted on the module substrate 2100. The semiconductor module 2000 may include a memory card or a card package.

The memories 2200 and the microprocessor 2300 may include semiconductor devices according to various embodiments of the inventive concepts. Therefore, in the semiconductor module 2000 according to the embodiment of the present invention, the reliability of the memories 2200 and the microprocessor 2300 can be improved.

21 is a block diagram showing a mobile system including a semiconductor device according to the technical idea of the present invention.

Referring to FIG. 21, the mobile system 3000 may include a display unit 3100, a body unit 3200, and an external apparatus 3300. The body unit 3200 may include a microprocessor 3210, a power supply 3220, a functional part 3230, and a display controller 3240.

The display unit 3100 may be electrically connected to the body unit 3200. The display unit 3100 may be electrically connected to the display controller 3240 of the body unit 3200. The display unit 3100 may implement an image processed by the display controller 3240 of the body unit 3200.

The body unit 3200 may be a system board including a printed circuit board (PCB) or a mother board. The microprocessor 3210, the power supply unit 3220, the functional unit 3230 and the display controller 3240 may be mounted or mounted on the body unit 3200.

The microprocessor 3210 can receive the voltage from the power supply unit 3230 and control the function unit 3230 and the display controller 3240. The power supply unit 3220 may receive a predetermined voltage from an external power supply or the like and may divide it into various voltage levels and supply the voltage to the microprocessor 3210, the function unit 3230, and the display controller 3240.

The power supply unit 3220 may include a power management IC (PMIC). The power management IC can efficiently supply voltage to the microprocessor 3210, the function unit 3230, and the display controller 3240.

The functional unit 3230 may perform various functions of the mobile system 3000. [ For example, the function unit 3230 may include various components capable of performing wireless communication functions such as video output to the display unit 3100, audio output to a speaker, and the like through dialing or communication with the external device 3300 ≪ / RTI > For example, the function unit 3230 may function as an image processor of a camera.

The function unit 3230 may function as a memory card controller when the mobile system 3000 is connected to a memory card or the like for capacity expansion. The function unit 3230 may function as an interface controller when the mobile system 3000 further includes a universal serial bus (USB) for expanding functions.

The microprocessor 3210, the power supply unit 3220 and the function unit 3230 may include a semiconductor device according to various embodiments of the technical concept of the present invention. Therefore, reliability can be improved in the mobile system 3000 according to the embodiment of the present invention.

22 is a configuration diagram showing a mobile device including a semiconductor device according to the technical idea of the present invention.

22, the mobile device 4000 may be a mobile wireless phone. The mobile device 4000 may be understood as a tablet PC. The mobile device 4000 may comprise a semiconductor device according to various embodiments of the inventive concepts. Accordingly, the reliability of the mobile device 4000 according to the embodiment of the present invention can be improved.

23 is a configuration diagram showing an electronic system including a semiconductor device according to the technical idea of the present invention.

23, the electronic system 5000 may include a memory 5100, a microprocessor 5200, a power supply 5300, and a user interface 5400 . The electronic system 5000 may be a system such as an LED lighting device, a refrigerator, an air conditioner, an industrial cutter, a welding machine, an automobile, a ship, an aircraft,

The memory 5100 may store code for booting the microprocessor 5200, data processed by the microprocessor 5200, or external input data. The memory system 5100 may include a controller and a memory.

The microprocessor 5200 may program and control the electronic system 5000. The microprocessor 5200 may include a RAM used as an operation memory.

The power supply unit 530 may supply a predetermined voltage to the memory 5100, the microprocessor 5200, and the user interface 5400 by receiving a predetermined voltage from an external power supply or the like. The power supply unit 5300 may include a power management IC (PMIC).

The user interface 5400 may perform data communication using the bus 5500. [ The user interface 5400 may be used to input data to or output data from the electronic system 5000.

The memory 5100 and the microprocessor 5200 may include semiconductor devices according to various embodiments of the inventive concepts. Therefore, in the electronic system 5000 according to the embodiment of the present invention, the reliability of the memory 5100 and the microprocessor 5200 can be improved.

100: semiconductor substrate 110: gate pattern
121: conductive landing pad 122: insulating fence
130: interlayer insulating film 140: bit line lower protective film
150p: DC plug 160f: Bit line structure

Claims (10)

A semiconductor substrate;
An interlayer insulating film located on the semiconductor substrate;
A DC plug penetrating the interlayer insulating film;
A first bit line structure located on the DC plug;
A second bit line structure located on the interlayer dielectric film and spaced apart from the first bit line structure; And
And a bit line lower protective film located between the interlayer insulating film and the second bit line structure and covering the lower surface of the second bit line structure. The method according to claim 1,
And the horizontal distance of the bit line lower protective film is larger than the horizontal distance of the interlayer insulating film. The method according to claim 1,
Further comprising a bit line spacer located on a side of the second bit line structure, wherein the bit line lower protective film comprises the same material as the bit line spacers. The method of claim 3,
Wherein the bit line lower protective film is harder than the interlayer insulating film. The method of claim 3,
And the level of the lower surface of the bit line spacer is equal to the level of the lower surface of the bit line lower protective film. The method according to claim 1,
A DC spacer positioned on a side surface of the DC plug; an insulating fence positioned between the semiconductor substrate and the interlayer insulating film; a conductive landing pad positioned between the DC spacer and the insulating fence; Further comprising a contact plug, wherein the storage contact plug is in direct contact with an upper surface of the conductive landing pad and a lower surface of the bit line lower protective layer. The method according to claim 6,
Wherein a top surface of the conductive landing pad includes a pad recess region wherein a horizontal distance of a contact surface between the conductive landing pad and the storage contact plug is greater than a horizontal distance of the pad recess region. The method according to claim 6,
Wherein the storage contact plug is in direct contact with the entire top surface of the conductive landing pad. The method according to claim 6,
Wherein a horizontal distance of the insulating fins is larger than a horizontal distance of the interlayer insulating film. 10. The method of claim 9,
Wherein the storage contact plug is in direct contact with an upper surface of the insulating fence.

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