KR20140083528A - Semiconductor Device Having Vertical Cells and Method of Fabricating the Same - Google Patents

Abstract

Suggested is a semiconductor device which includes a substrate, multiple insulating layers and word line electrodes which are alternately stacked on the substrate, a channel structure which vertically penetrates the insulating layers and the word line electrodes and touches the substrate, and a cutting structure which vertically and partly cuts the upper parts of the word line electrodes and the upper part of the insulating layers. The cutting structure includes a cutting trench which vertically and partly cuts the upper part of the world line electrodes and the insulating layers, a cutting protection pattern which is conformal on both sidewalls of the cutting trench, and a cutting trap pattern which is conformal on the cutting protection pattern.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device having vertical cells and a fabrication method thereof. [0002]

The present invention relates to a semiconductor device having vertical cells and a manufacturing method thereof.

A method of vertically stacking cells to improve the degree of integration of semiconductor devices has been proposed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having vertical cells.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device having a vertical cell.

The various problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

A semiconductor device according to an embodiment of the present invention includes a substrate, a plurality of insulating layers alternately and repeatedly stacked on the substrate, and word line electrodes vertically penetrating the insulating layers and the word line electrodes A channel structure in contact with the substrate, and a cut structure vertically cutting an upper portion of the insulating layers and an upper portion of the word line electrodes, wherein the cut structure includes at least one of the interlayer dielectric layers and the word A cut trench that vertically cuts each of the upper portions of the line electrodes, a cut protection pattern that is conformally formed on both sidewalls of the cut trench, and a cut trap pattern that is conformally formed on the cut protection pattern. have.

The cut protection pattern may comprise silicon oxide.

The cut trap pattern may comprise a silicon nitride layer and a silicon oxide layer.

The cut channel pattern may comprise polycrystalline silicon.

The cut protection pattern may be conformally formed to be continuous materially on both sidewalls and bottom surface of the cutting trench.

The cut trap pattern may be formed conformally so as to be materially continuous on the side surfaces and the bottom surface of the cut protection pattern.

The cutting structure may further include a cut channel pattern conformally formed on the cut trap pattern.

The cut channel pattern may be materially continuous on the cut cut trap pattern.

Wherein the channel structure includes a channel hole vertically penetrating the interlayer insulating layers and the word line electrodes to expose a surface of the substrate, a channel protective pattern conformally formed on an inner wall of the channel hole, A channel trap pattern formed conformally on the channel trap pattern and a channel pattern electrically connected to the surface of the substrate, and a channel core pattern formed to fill the channel hole on the channel pattern. have.

The cut protection pattern and the channel protection pattern may comprise the same material.

The cut trap pattern and the channel trap pattern may comprise the same material.

A semiconductor device according to an embodiment of the present invention includes insulating trenches arranged in parallel to each other on a substrate, channel holes disposed between the insulating trenches, and channel holes formed in a center of the dummy channel Holes formed in the dummy channel holes and real channel holes arranged in two or more rows between the dummy channel holes and one of the respective insulating trenches and including cutting trenches intersecting the dummy channel holes, Dummy active patterns, and truncated active patterns formed in the truncated trenches, wherein the dummy active patterns and the truncated active patterns can be materially continuous.

The semiconductor device may further include spacers formed on sidewalls of the isolation trenches and a trench isolation filling the isolation trenches.

The details of other embodiments are included in the detailed description and drawings.

The semiconductor device according to the technical idea of the technical idea of the present invention may include channel structures and cutting structures including the same materials. Therefore, the process of manufacturing the semiconductor device can be simplified.

1 is a layout of a semiconductor device according to an embodiment of the present invention.
2A and 2B are longitudinal sectional views of a semiconductor device according to an embodiment of the present invention.
3A and 3B to 19A and 19B are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
20A is a conceptual view of a semiconductor module including a semiconductor element according to one embodiment of the technical concept of the present invention.
20B is a block diagram conceptually showing an electronic system including a semiconductor element according to an embodiment of the technical idea of the present invention.
20C is a block diagram schematically illustrating another electronic system including a semiconductor device according to an embodiment to which the technical idea of the present invention is applied.
20D is a view schematically showing a mobile device including a semiconductor device according to an embodiment of the technical concept of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

It is to be understood that one element is referred to as being 'connected to' or 'coupled to' another element when it is directly coupled or coupled to another element, One case. On the other hand, the fact that one device is referred to as being 'directly connected to' or 'directly coupled to' another device indicates that no other device is interposed in between. Like reference numerals refer to like elements throughout the specification. &Quot; and / or " include each and every one or more combinations of the mentioned items.

Spatially relative terms such as 'below', 'beneath', 'lower', 'above' and 'upper' May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figure, an element described as 'below' or 'beneath' of another element may be placed 'above' another element. Thus, the exemplary term " below " may include both the downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Like reference numerals refer to like elements throughout the specification. Accordingly, although the same reference numerals or similar reference numerals are not mentioned or described in the drawings, they may be described with reference to other drawings. Further, even if the reference numerals are not shown, they can be described with reference to other drawings.

1 is a layout of a semiconductor device 100 according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor device 100 according to an embodiment of the present invention may include channel holes Hd and Hr, a cutting trench Tc, and insulating trenches Ti. The channel trenches Hd and Hr may be arranged between the insulating trenches Ti in five rows. The channel holes Hd and Hr may include dummy channel holes Hd arranged in the center and real channel holes Hr arranged on both sides. Adjacent channel holes Hd and Hr may be arranged in a staggered manner. A straight cutting trench Tc may be arranged to intersect the dummy channel holes Hd.

2A and 2B are longitudinal sectional views of a semiconductor device 100 according to an embodiment of the present invention. FIG. 2A is a longitudinal sectional view taken along line I-I 'of FIG. 1, and FIG. 2A is a longitudinal sectional view taken along a line II-II' and III-III 'of FIG. 2A and 2B, a semiconductor device 100 according to an embodiment of the present invention includes interlayer insulating layers 120 and 120t stacked on a substrate 110, word line electrodes 130, (210d, 210r), and a cut structure (310).

The interlayer insulating layers 120 and 120t and the word line electrodes 130 may be alternately and repeatedly stacked. The interlayer insulating layers 120 and 120t may include silicon oxide. The word line electrodes 130 may comprise a metal-like conductor. The word line electrodes 130 may be surrounded by a blocking pattern 135, respectively. The blocking pattern 135 may include an insulator having a relatively high work function. For example, the blocking pattern 135 may comprise a metal oxide, such as aluminum oxide.

The channel structures 210d and 210r may include a dummy channel structure 210d at the center and real channel structures 210r at both sides of the dummy channel structure 210d. The channel structures 210d and 210r may vertically penetrate the interlayer insulating layers 120 and 120t and the word line electrodes 130 to contact the substrate 110. [ The channel structure 210 and the word line electrodes 130 may be spaced apart with a blocking pattern 135 therebetween.

The channel structures 210d and 210r may include channel activation patterns 220d and 220r and channel pad patterns 230d and 230r, respectively. The channel activation patterns 220d and 220r may include a dummy channel activation pattern 220d and a real channel activation pattern 220r. The dummy channel active pattern 220d includes a dummy channel protection pattern 221d, a dummy channel trap pattern 223d, a dummy channel pattern 225d, and a dummy channel core pattern 225d formed conformally on the inner wall of the dummy channel hole Hd. Lt; RTI ID = 0.0 > 227d. ≪ / RTI > The real channel activation patterns 220r include real channel protection patterns 221r, real channel trap patterns 223r, real channel patterns 225r, and the like, which are conformally formed on the inner walls of the real channel holes Hr, And real channel core patterns 227r.

The channel protection patterns 221d and 221r may be in direct contact with the blocking pattern 135. [ The channel protection patterns 221d and 221r may include silicon oxide. The channel trap patterns 223d and 223r may comprise double or triple layers of insulating layers. For example, the channel trap patterns 223d and 223r may comprise a double layer of silicon nitride and silicon oxide, or a triple layer of insulating layers of silicon oxide, silicon nitride, and silicon oxide. The channel patterns 223d and 223r may include silicon. For example, the channel patterns 225d and 225r may comprise intrinsic silicon, doped monocrystalline or polycrystalline silicon. The channel core patterns 225d and 225r may include silicon oxide.

The channel pad patterns 230d and 230r may be arranged to be vertically aligned on the channel activation patterns 220d and 220r. The channel pad patterns 230d and 230r may include conductors. For example, the channel pad patterns 230d and 230r may comprise doped polycrystalline silicon or metal silicide. The channel pad patterns 230d and 230r may be surrounded by the uppermost interlayer insulating layer 120t.

The cut structure 310 may partially penetrate the interlayer insulating layers 120, 120t and the word line electrodes 130 vertically. For example, the cut structure 310 may vertically cut several upper layers of the interlayer dielectric layers 120, 120t and several upper layers of the word line electrodes 130. The cut structure 310 may include a cut active pattern 320 and a cut pad pattern 330. The cut active pattern 320 may include a cut protection pattern 321 and a cut trap pattern 323 formed conformally on the inner walls and bottom surface of the cutting trench Tc, respectively. The cut active pattern may include a cut channel pattern 325 conformally formed on the cut trap pattern 323, and / or a cut core pattern 327. The cut protection pattern 321 and the blocking pattern 323 can directly contact each other. The cut protection pattern 321, the cut trap pattern 323, and / or the cut channel pattern 325 may be conformally formed so as to be materially continuous on both sidewalls and the bottom surface of the cut trench Tc. The channel protection pattern 221 and the cut protection pattern 321 may comprise the same material. The channel trap pattern 223 and the cut trap pattern 323 may comprise the same material. The channel pattern 225 and the cut channel pattern 325 may comprise the same material. The channel core pattern 227 and the cut core pattern 327 may comprise the same material. The cut pad pattern 330 may be arranged to be vertically aligned on the cut active pattern 320. [ The channel pad pattern 230 and the cutting pad pattern 330 may comprise the same material. The cutting pad pattern 230 may also be surrounded by the uppermost interlayer insulating layer 120t. In another embodiment, the cut channel pattern 325 and the cut core pattern 327 may be omitted.

2B, the dummy channel protection pattern 221d and the cut protection pattern 321, the dummy channel trap pattern 223d, and the cut trap pattern Tc in the region where the dummy channel hole Hd and the cutting trench Tc intersect each other, The dummy channel pattern 225d and the cut channel pattern 325 and the dummy channel core pattern 227d and the cut core pattern 327 may be continuous.

The bit line plug 410 and the bit line 420 may be formed on the channel structures 210d and 210r and the cut structure 310. [ A bit line plug 420 may be formed on the channel pad pattern 230. For example, the bit line plug 410 may be in direct contact with the channel pad pattern 230 to be electrically connected. The bit line plug 410 may or may not be connected to the cutting pad pattern 330. The bit line plug 410 may comprise a metal compound or a metal suicide. The side of the bit line plug 410 may be surrounded by an insulating capping layer 150. The bit line 420 may be formed to be connected to the bit line plug 410 on the capping layer 150. The bit line 420 may comprise a metal or a metal compound.

The semiconductor device 100 according to an embodiment of the present invention includes channel structures 210d and 210r vertically penetrating the insulating layers 120 and the word line electrodes 130 and word line electrodes 130 in a cutting trench Tc that cuts portions of the trench Tc. The channel structures 210d and 210r and the truncated structures 310 may include channel activity patterns 220d and 220r and a truncated active pattern 320 that include the same material. Thus, the channel activation patterns 220d and 220r and the cleavage active pattern 320 can be formed at the same time, and thus can be manufactured by a simplified process.

3A and 3B to 19A and 19B are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 3A to 19A are longitudinal cross-sectional views in the direction of I-I 'in FIG. 1 and 3b to 19b are longitudinal cross-sectional views in the II-II' and III-III 'directions of FIG.

3A and 3B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes forming a first insulating layer 121 and a second insulating layer 122 on a substrate 110, ) Alternately and repeatedly. The uppermost first insulating layer 120t may be formed to be relatively thick. A buffer layer 125 may further be formed on the uppermost first insulating layer 120t. Forming the first insulating layers 121 and 120t may include performing a deposition process to form the silicon oxide layers. Forming the second insulating layers 122 may include performing a deposition process to form silicon nitride layers. The formation of the buffer layer 125 may include performing a deposition process to form a polycrystalline silicon layer.

4A and 4B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes forming a buffer layer 125, first insulating layers 121 and 120t, and second insulating layers 122 vertically To form a plurality of channel holes (Hd, Hr) that expose the substrate (110). The channel holes Hd and Hr may include both the dummy channel hole Hd at the center and the real channel holes Hr at both sides of the dummy channel hole Hd.

5A and 5B, a method of fabricating a semiconductor device according to an embodiment of the present invention may include filling a sacrificial fill material 140 in channel holes Hd and Hr. The sacrificial fill material 140 may have an etch selectivity with the first insulating layers 121 and 120t and the second insulating layer 122. [ For example, the sacrificial fill material 140 may comprise silicon oxide (SiOC) containing carbon (C) such as spin on hardmask (SOH). A sacrificial fill material 140 may also be formed on the buffer layer 125.

Referring to FIGS. 6A and 6B, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming a cutting trench (Tc). The cutting trench Tc may have a straight line intersecting the dummy channel holes Hd. The cutting trench Tc can cut several of the first insulating layers 121 and 120t and some of the second insulating layers 122 located above. The bottom of the cutting trench Tc may be located in the middle of one of the first insulating layers 121.

7A and 7B, a method of fabricating a semiconductor device according to an embodiment of the present invention may include removing sacrificial fill material 140 from within the channel holes Hd and Hr.

8A and 8B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes forming a protective layer 21 and a trap layer 23 in channel holes Hd and hr and a cut trench Tc, Lt; RTI ID = 0.0 > conformationally < / RTI > The protective layer 21 may comprise silicon oxide. For example, the protective layer 21 may be formed by performing a process of forming a silicon oxide such as an in-situ steam generation (ISSG) process. Alternatively, the protective layer 21 may be formed using a deposition process such as ALD (atomic layered deposition). The trap layer 23 may comprise a silicon nitride layer. The trap layer 23 may comprise multiple layers of insulating layers. For example, the trap layer 23 may be formed of a double layer comprising a silicon nitride layer and a silicon oxide layer. Alternatively, the trap layer 23 may be formed of a triple layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

9A and 9B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes performing an etch-back process to expose a surface of a substrate 110 to the bottom of channel holes Hd and Hr ≪ / RTI > The cut trench Tc has a sufficiently narrow width as compared with the channel holes Hd and Hr so that the protective layer 21 and / or the trap layer 23 can remain intact or selectively on the bottom. The dummy channel protection pattern 221d and the dummy channel trap pattern 223d can be formed in the dummy channel hole Hd and the real channel protection patterns 221r and the real channel Trap patterns 223r may be formed and a cut protection pattern 321 and a cut trap pattern 323 may be formed in the cut trench Tc.

10A and 10B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a channel layer 25 in channel holes Hd and Hr, And forming a core layer 27 filling the interior. Forming the channel layer 25 may include performing a deposition process to conformally form the polycrystalline silicon layer on the active trap pattern 223 and the cut trap pattern 323. [ Forming the core layer 27 may include forming a silicon oxide on the channel layer 25 to fill the channel holes Hd and Hr. In another embodiment, only the channel layer 25 may be formed in the cutting trench Tc.

11A and 11B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes performing a planarization process such as etch-back or CMP to form channel active patterns (not shown) filling channel holes Hd. Hr (220d, 220r) and a cut active pattern (320) filling the interior of the cut trench (Tc). Each of the channel activation patterns 220d and 220r includes channel protection patterns 221d and 221r, channel trap patterns 223d and 223r, channel patterns 225d and 225r, and channel core patterns 227d and 227r, And the cut active pattern 320 may include a cut protective pattern 321, a cut trap pattern 323, a cut channel pattern 325, and a cut core pattern 327. In another embodiment, when the core layer 27 is omitted in the cut trench Tc, the cut active pattern 320 may not include the cut core pattern 327. [

Referring to FIGS. 12A and 12B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes performing an etch-back process or the like to recess the upper portions of the channel active pattern 220 and the cut active pattern 320, Lt; / RTI > Pad spaces Sp may be formed on the recessed channel active pattern 220 and the cut active patterns 320. [

13A and 13B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming channel pad patterns 230d and 230r and a cutting pad pattern 330 in pad spaces Sp ≪ / RTI > Forming the channel pad patterns 230d and 230r and the cutting pad patterns 330 may include forming polycrystalline silicon all over and performing a planarization process such as CMP or etch-back. The channel pad patterns 230d and 230r and the cut pad pattern 330 may include a metal, a metal alloy, a metal compound, or a metal suicide.

14A and 14B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes forming a capping layer 150 covering channel pad patterns 230d and 230r and a cut pad pattern 330 And insulating trenches Ti that expose the surface of the substrate 110. The insulating trenches Ti may expose the surface of the substrate 110 vertically through the capping layer 150, the first insulating layers 120 and 120t, and the second insulating layers 122. With further reference to Figure 1, the isolation trenches Ti may have a straight line shape.

15A and 15B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes removing second interlayer insulating layers 122 through insulation trenches Ti to form word line spaces Sw ). ≪ / RTI >

16A and 16B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a blocking layer 35 and a word line electrode material layer 30 in a word line space Sw can do. Forming the blocking layer 35 may include performing an evaporation process such as ALD to form an insulating material having a high work function such as aluminum oxide. Forming the word line electrode material layer 30 may include performing a deposition process to form a metal such as tungsten. A barrier metal layer (not shown) may be interposed between the blocking layer 35 and the word line electrode material layer 30.

17A and 17B, a method of fabricating a semiconductor device according to an embodiment of the present invention includes performing an etch-back process or the like to expose the top of the capping layer 150 and the inside of the insulating trenches Ti The word line electrode material layer 30 and the blocking layer 35 may be removed to form the blocking patterns 135 and the word line electrodes 130.

18A and 18B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a spacer 170 on the inner wall of the isolation trenches Ti, forming a common source electrode CS Lt; / RTI > Forming the spacers 170 may include performing an ALD-like deposition process and an add-back process. The spacer 170 may comprise silicon oxide or silicon nitride. Formation of the common source electrode CS may include implanting elements such as phosphorous, arsenic, or boron into the substrate 110.

19A and 19B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a trench insulator 180 filling the isolation trenches Ti, To form a bit line plug 410 that is connected to the bit line. The trench insulator 180 may comprise silicon oxide. The bit line plugs 410 may comprise a metal, a metal compound, and / or a metal suicide.

2A and 2B, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming bit lines 420 (not shown) electrically connected to bit line plugs 410 on a capping layer 150, ). ≪ / RTI > The bit lines 420 may comprise a metal, a metal compound, and / or a metal suicide.

According to the technical idea of the present invention, the channel structures 210d and 210r of the semiconductor device 100 and the cut structure 310 can be simultaneously formed by the same process, and thus can be manufactured by a simplified process.

20A conceptually illustrates a semiconductor module 2200 including a semiconductor device 100 according to one embodiment of the technical concept of the present invention. 20A, a semiconductor module 2200 according to an embodiment of the technical idea of the present invention includes a semiconductor device 100 according to an embodiment of the technical idea of the present invention mounted on a semiconductor module substrate 2210, . ≪ / RTI > The semiconductor module 2200 may further include a microprocessor 2220 mounted on the module substrate 2210. Input / output terminals 2240 may be disposed on at least one side of the module substrate 2210. The microprocessor 2220 may comprise a semiconductor device () according to one embodiment of the present invention.

20B is a block diagram conceptually showing an electronic system 2300 including a semiconductor device 100 according to an embodiment of the technical concept of the present invention. Referring to FIG. 20B, the semiconductor device 100 according to one embodiment of the technical idea of the present invention can be applied to the electronic system 2300. The electronic system 2300 may include a body 2310. The body 2310 may include a microprocessor 2320, a power supply 2330, a functional unit 2340, and / or a display controller 2350. The body 2310 may be a system board or a mother board having a printed circuit board (PCB) or the like. A microprocessor 2320, a power supply 2330, a functional unit 2340, and a display controller 2350 may be mounted or mounted on the body 2310. A display 2360 may be disposed on the top surface of the body 2310 or outside the body 2310. For example, the display 2360 may be disposed on the surface of the body 2310 to display an image processed by the display controller 2350. The power supply 2330 is supplied with a predetermined voltage from an external power supply or the like, and can supply the voltage to the microprocessor 2320, the function unit 2340, the display controller 2350, or the like. The microprocessor 2320 can receive the voltage from the power supply 2330 and control the functional unit 2340 and the display 2360. Functional unit 2340 may perform the functions of various electronic systems 2300. For example, if the electronic system 2300 is a mobile electronic device such as a cellular phone, the functional unit 2340 may be capable of outputting video to the display 2360 by dialing or in communication with an External Apparatus 2370, And the like, and may include a camera, and may serve as an image processor. In another embodiment, when the electronic system 2300 is connected to a memory card or the like for capacity expansion, the functional unit 2340 may be a memory card controller. The functional unit 2340 can exchange signals with the external device 2370 through a wired or wireless communication unit (Communication Unit) 2380. In addition, when the electronic system 2300 requires a universal serial bus (USB) or the like for function expansion, the functional unit 2340 can serve as an interface controller. The semiconductor elements 10a and 10b described in the various embodiments according to the technical idea of the present invention may be included in at least one of the microprocessor 2320 and the functional unit 2340. [

20C is a block diagram schematically illustrating another electronic system 2400 including a semiconductor device 100 according to an embodiment to which the technical idea of the present invention is applied. Referring to FIG. 20C, the electronic system 2400 may include a semiconductor device 100 according to one embodiment of the present invention. The electronic system 2400 can be used to manufacture mobile devices or computers. For example, the electronic system 2400 may include a user interface 2418 that performs data communication using a memory system 2412, a microprocessor 2414, a RAM 2416, and a bus 2420. The microprocessor 2414 may program and control the electronic system 2400. RAM 2416 may be used as an operating memory of microprocessor 2414. [ For example, the microprocessor 2414 or the RAM 2416 may comprise a semiconductor device according to an embodiment of the present invention. Microprocessor 2414, RAM 2416, and / or other components may be assembled into a single package. The user interface 2418 may be used to input data to or output data from the electronic system 2400. Memory system 2412 may store microprocessor 2414 operation codes, data processed by microprocessor 2414, or external input data. Memory system 2412 may include a controller and memory.

20D is a schematic view of a mobile device 2500 including a semiconductor device 100 according to one embodiment of the technical concept of the present invention. Mobile device 2500 may include a mobile phone or tablet PC. In addition, the semiconductor device 100 according to an exemplary embodiment of the present invention may be used in addition to a mobile phone or a tablet PC, a portable computer such as a notebook, an mpeg-1 audio layer 3 (MP3) player, an MP4 player, State disk (SSD), table computers, automobiles, and household appliances.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

100: semiconductor device 110: substrate
120: interlayer insulating layer 120t: uppermost interlayer insulating layer
125: buffer layer 130: word line electrode
135: blocking pattern 140: sacrificial filling material
150: capping layer 170: spacer
180: trench insulation 121: first insulation layer
122: second insulation layer 210: channel structure
220: Channel activity pattern 221: Channel protection pattern
223: Channel trap pattern 225: Channel pattern
227: Channel core pattern 230: Channel pad pattern
310: Cutting structure 320: Cutting active pattern
321: Cutting protection pattern 323: Cutting trap pattern
325: Cutting channel pattern 327: Cutting core pattern
330: cutting pad pattern 410: bit line plug
420: bit line 21: protection layer
23: trap layer 25: channel layer
27: core layer 30: wordline material layer
35: blocking layer Hd: dummy channel hole
Hr: Real channel hole Tc: Cutting trench
Ti: isolation trench CS: common source electrode
Sw: Word line space Sp: Pad space

Claims (10)

Board;
A plurality of layers of insulating layers and word line electrodes alternately and repeatedly stacked on the substrate;
A channel structure vertically penetrating the insulation layers and the word line electrodes to contact the substrate; And
A cut structure vertically cutting an upper portion of the insulating layers and a portion of upper ones of the word line electrodes,
The cutting structure includes:
A cutting trench vertically cutting the upper portions of each of the interlayer insulating layers and the word line electrodes;
A cut protection pattern conformally formed on both sidewalls of the cutting trench; And
And a cut trap pattern formed conformally on the cut protection pattern. The method according to claim 1,
Wherein the cut protection pattern comprises silicon oxide,
Wherein the cut trap pattern comprises a silicon nitride layer and a silicon oxide layer, and
Wherein the cut channel pattern comprises polycrystalline silicon. The method according to claim 1,
Wherein the cut protection pattern is conformally formed so as to be materially continuous on both sidewalls and a bottom surface of the cutting trench. The method of claim 3,
Wherein the cut trap pattern is conformally formed so as to be materially continuous on the side surfaces and the bottom surface of the cut protection pattern. The method according to claim 1,
Wherein the cut structure further comprises a cut channel pattern conformally formed on the cut trap pattern. 6. The method of claim 5,
Wherein the cut channel pattern is materially continuous on the cut cut trap pattern. The method according to claim 1,
The channel structure may include:
A channel hole vertically penetrating the interlayer insulating layers and the word line electrodes to expose a surface of the substrate;
A channel protective pattern conformally formed on an inner wall of the channel hole;
A channel trap pattern conformally formed on the channel protection pattern;
A channel pattern conformally formed on the channel trap pattern and electrically connected to a surface of the substrate; And
And a channel core pattern formed to fill the channel hole on the channel pattern. 8. The method of claim 7,
Wherein the cut protection pattern and the channel protection pattern comprise the same material, and
Wherein the cut trap pattern and the channel trap pattern comprise the same material. Insulating trenches arranged on the substrate in parallel with each other;
The channel holes being arranged in the middle of the insulation trenches, the dummy channel holes being arranged in a row at the center, and a plurality of dummy channel holes disposed between the dummy channel holes and one of the insulation trenches, Holes;
And cutting trenches intersecting the dummy channel holes,
Dummy active patterns formed in the dummy channel holes; And
A cut active patterns formed in the cutting trenches,
Wherein the dummy active patterns and the cleavage active patterns are materially continuous. 10. The method of claim 9,
A spacer formed on sidewalls of the isolation trenches and a trench isolation filling the isolation trenches.

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