KR20140103602A - Field-effect transistor arrray including aligned copper oxide semiconductor nanowire and a method for fabricating the same - Google Patents

Abstract

Provided are a method for fabricating a field-effect transistor array and a field-effect transistor array fabricated thereby. The method for fabricating a field-effect transistor array comprises the following steps: forming a gate electrode on a substrate; forming a gate insulator on the substrate where the gate electrode is formed; preparing a copper oxide semiconductor precursor/organic polymer composite solution by dissolving a copper oxide semiconductor precursor and an organic polymer in distilled water or an organic solvent; aligning a copper oxide semiconductor precursor/organic polymer composite nanowire on the gate insulator by dropping the oxide semiconductor precursor/organic polymer composite solution from a position with a vertical distance of 10 to 20 μm from the gate insulator; forming an aligned copper oxide semiconductor nanowire pattern by heating the aligned copper oxide semiconductor precursor/organic polymer composite nanowire; and forming a source/drain electrode on the aligned copper oxide semiconductor nanowire pattern.

Description

FIELD EFFECT TRANSISTOR ARRAY INCLUDING ALIGNED COPPER OXIDE SEMICONDUCTOR NANOWIRE AND METHOD FOR FABRICATING THE SAME Field of the Invention [0001]

The present invention relates to a field effect transistor array having an active layer including a copper oxide semiconductor and a method of manufacturing the same.

A field-effect transistor (FET) generates a field in a channel by applying a voltage to a gate electrode to control the current between the source electrode and the drain electrode using the principle that a gate is provided for the flow of electrons or holes. Lt; / RTI >

BACKGROUND ART [0002] A field-effect transistor is applied to an active matrix type display as a thin film transistor (TFT).

Recently, as a flat panel display (FPD), a liquid crystal display, an organic EL (electroluminescent) display, an electronic paper and the like have been practically used.

The flat panel display is driven by a driving circuit comprising a thin film transistor having an active layer formed of amorphous silicon or polycrystalline silicon. Flat panel displays have been required to achieve greater size, higher sharpness, and faster drive speeds. Accordingly, there is a demand for a thin film transistor having a higher charge mobility, less fluctuation of a threshold voltage with time, and less variation in characteristics in a panel.

However, a thin film transistor having an active layer formed of amorphous silicon has a disadvantage in that the charge mobility for driving a liquid crystal display (LCD) is insufficient and the threshold voltage shift during continuous driving is large. Thin film transistors having an active layer formed of low-temperature polysilicon have high charge mobility. However, since the variation of the threshold voltage is large during the process of crystallizing the active layer by annealing using an eximer laser, A large mother glass can not be used. Therefore, it has been difficult to manufacture a thin film transistor having a high charge mobility and a small variation in threshold voltage.

 Furthermore, in the case of a thin film transistor having a silicon active layer, it is not suitable to form the silicon active layer in a thin film transistor using a flexible substrate having a relatively low heat resistance, since a high temperature treatment is indispensably required in a conventional manufacturing process.

As the need for flexible substrates such as plastic films increases to address these problems and to produce displays that are lightweight, flexible, and have high impact resistance and low cost, inorganic semiconductor nanowires are used as active layers of transistors Researches to be used have been actively carried out. As a representative method of making semiconductors using inorganic semiconductor nanowires, a method of growing nanowires on a substrate by chemical vapor deposition has been used. When a silicon nano wire or a zinc oxide (ZnO) nanowire grown through the chemical vapor deposition method is used for a transistor, a transistor having a high charge mobility can be manufactured.

However, processes such as anodic aluminum oxide template, hydrothermal synthesis, electroless etching, etc., including the conventionally known chemical vapor deposition processes, have the following problems.

1) In order to manufacture a transistor including an inorganic semiconductor nanowire as an active layer, the nanowire must be laid horizontally. Since the nanowire grown through a conventional process grows in a direction perpendicular to the substrate, the nanowire is separated from the substrate And a separate process of dispersing is required. In this process, the nanowires spread irregularly, making it impossible to fabricate a highly integrated large-area nanowire device array.

2) In order to fabricate a device including nanowires that are laid horizontally with respect to the substrate, an electrode must be deposited. Since the size of the nanowire is very small and irregular, expensive equipment such as E-beam evaporation should be used . Further, since it is necessary to set a position for directly depositing electrodes on individual nanowires, it is not suitable for mass production of electronic devices including nanowires.

Accordingly, there is a need for a method of manufacturing an electronic device including an inorganic semiconductor nanowire suitable for mass production by precisely adjusting the position and direction of the inorganic semiconductor nanowire and reducing manufacturing time.

The following references are the references of the present invention.

[1] H.-S. Lee et al., Biosensors and Bioelectronics, 24: 1801-1805 (2009).

[2] X. Yang et al., Inorganic Chem. Commu. 7, 176-178 (2004).

[3] H. Wu, and W. Pan, J. Am. Ceram. Soc., 89, 699-701 (2006).

One embodiment of the present invention provides a field effect transistor array in which a pattern of copper oxide semiconductor nanowires is formed by aligning a copper oxide semiconductor nanowire in a desired direction and a desired number with high speed and accuracy.

Yet another embodiment of the present invention provides a method of fabricating a field effect transistor array in which the pattern of copper oxide semiconductor nanowires is formed.

One embodiment of the present invention is a method

Forming a gate electrode on the substrate;

Forming a gate insulating film on the substrate on which the gate electrode is formed;

Dissolving a copper oxide semiconductor precursor and an organic polymer in distilled water or an organic solvent to provide a composite solution of a copper oxide semiconductor precursor / organic polymer;

A step of dropping a complex solution of the copper oxide semiconductor precursor / organic polymer at a point 10 to 20 mm away from the gate insulating film vertically to align the nanowires of the copper oxide semiconductor precursor / organic polymer complex on the gate insulating film ;

Heating the nanowires of the ordered copper oxide semiconductor precursor / organic polymer composite to form a pattern of aligned copper oxide semiconductor nanowires; And

Forming a source / drain electrode on the ordered copper oxide semiconductor nanowire pattern;

Gate copper oxide semiconductor nanowire field effect transistor array.

Another embodiment of the present invention is a method

Forming a source / drain electrode on the substrate;

Dissolving a copper oxide semiconductor precursor and an organic polymer in distilled water or an organic solvent to provide a copper oxide semiconductor precursor / organic polymer complex solution;

Aligning the nanowires of the copper oxide semiconductor precursor / organic polymer complex by dropping the copper oxide semiconductor precursor / organic polymer complex solution at a point 10 to 20 mm away from the source / drain electrode vertically;

Heating the aligned copper oxide semiconductor precursor / organic polymer composite nanowire to form a pattern of aligned copper oxide semiconductor nanowires;

Forming a gate insulating film on the aligned copper oxide semiconductor nanowire pattern; And

And forming a gate electrode on the gate insulating film. The present invention also provides a method of manufacturing a field-effect transistor array of a top-gate structure.

The step of forming the ordered copper oxide semiconductor nanowire pattern may include heating the nanowire of the copper oxide semiconducting precursor / organic polymer composite at a temperature of 100 ° C to 900 ° C for 1 to 24 hours .

The step of aligning the ordered copper oxide semiconductor precursor / organic polymer composite nanowires may be performed by an electric field assisted robotic nozzle printer. The electric field assisted robotic nozzle printer comprises: i) a solution storage device for containing a copper oxide semiconductor precursor / organic polymer complex solution; ii) a nozzle device for discharging the solution supplied from the solution storage device; iii) a voltage applying device for applying a high voltage to the nozzle; iv) a collector for holding said substrate; v) a robot stage for moving the collector in a horizontal direction; vi) a micro-distance adjuster for moving the collector in a vertical direction; And vii) a lithotripter that supports the collector.

The step of aligning the ordered copper oxide semiconductor precursor / organic polymer composite nanowire comprises the steps of: i) supplying the solution of copper oxide semiconducting precursor / organic polymer complex to the solution storage device; ii) discharging the copper oxide semiconductor precursor / organic polymer complex solution from the nozzle by applying a high voltage to the nozzle through the voltage application device of the electric field assisted robotic nozzle printer, wherein the copper oxide And moving the collector on which the substrate is placed in a horizontal direction when the semiconductor precursor / organic polymer composite solution is ejected.

The vertical distance between the collector and the nozzle may be 10 [mu] m to 20 [mu] m.

The substrate may be selected from the group consisting of an insulating material, a metal material, a carbon material, and a composite material of a conductor and an insulating film.

The forming of the gate electrode and the gate insulating layer may be performed independently of each other by a method such as drop casting, spin-coating, dip-coating, E-beam evaporation, the method may be carried out by a method selected from the group consisting of thermal evaporation, printing, soft-lithography, and sputtering.

The gate electrode may be selected from the group consisting of a metal, a conductive polymer, a carbon material, a doped semiconductor, and a combination thereof.

The thickness of the gate electrode may be 1 nm to 1 占 퐉.

The gate insulating film contains at least one functional group selected from the group consisting of an acid group such as a carboxyl group (-COOH) and a hydroxyl group (-OH), a thiol group (-SH), and a trichlorosilane group (-SiCl ₃ ) Self-assembled molecules, insulating polymers, inorganic oxides, polymer electrolytes, and combinations thereof.

The thickness of the gate insulating film may be 1 nm to 10 탆.

The copper oxide semiconductor precursor may be selected from the group consisting of copper trifluoroacetate, copper acetate, copper acetate hydrate, copper acetylacetonate, copper i-butyrate, ), Copper carbonate, copper chloride, copper chloride hydrate, copper ethylacetoacetate, copper 2-ethylhexanoate, copper fluoride Copper fluoride, Copper formate hydrate, Copper gluconate, Copper hexafluoroacetylacetonate, Copper hexafluoroacetylacetonate hydrate, Copper hexafluoroacetylacetonate hydrate, Copper hexafluoroacetylacetonate hydrate, Copper methoxide, Copper neodecanoate, Copper nitrate (Copper nitrate) e hydrate, copper nitrate, copper perchlorate hydrate, copper sulfate, copper sulfate hydrate, copper tartrate hydrate, copper triflouroacetylacetonate (Copper trifluoroacetylacetonate), Copper trifluoromethanesulfonate, Tetraamminecopper sulfate hydrate, and combinations thereof.

The organic polymer may be at least one selected from the group consisting of polyvinyl alcohol (PVA), polyethylene oxide (PEO), polystyrene (PS), polycaprolactone (PCL), polyacrylonitrile (PAN), poly (methyl methacrylate) Polyvinylidene fluoride (PVDF), polyaniline (PANI), polyvinyl chloride (PVC), nylon, poly (acrylic acid), poly (chlorostyrene), poly (dimethylsiloxane) Poly (ethyl acrylate), poly (ethyl vinyl acetate), poly (ethyl-co-vinyl acetate), poly (ethylene terephthalate), poly (lactic acid- Poly (styrene sulfonate), poly (styrene-co-acrylonitrile), poly (styrene-co (meth) acrylate) -Butadiene), poly (styrene-co-divinylbenzene), poly (vinyl acetate), poly Poly (vinyl alcohol), polyacrylamide, polybenzimidazole, polycarbonate, poly (dimethylsiloxane-co-polyethylene oxide), poly (etheretherketone), polyethylene, polyethyleneimine, polyisoprene, polylactide , Polypropylene, polysulfone, polyurethane, poly (vinylpyrrolidone), and combinations thereof.

The organic solvent is selected from the group consisting of dichloroethylene, trichlorethylene, chloroform, chlorobenzene, dichlorobenzene, dichloromethane, styrene, dimethylformamide, dimethylsulfoxide, tetrahydrofuran, xylene, toluene, cyclohexene, 2 - methoxyethanol, ethanolamine, acetonitrile, butyl alcohol, isopropyl alcohol, ethanol, methanol and acetone, and combinations thereof.

Another embodiment of the present invention provides a field effect transistor array fabricated by the above-described fabrication method.

Specifically, the field effect transistor array includes:

A gate electrode formed on the substrate;

A gate insulating film formed on the gate electrode;

An aligned copper oxide semiconductor nanowire pattern formed on the gate insulating film; And

And a source / drain electrode formed on the aligned copper oxide semiconductor nanowire pattern. The bottom-gate structure may be a copper oxide semiconductor nanowire field effect transistor array.

Alternatively, the field effect transistor array comprises:

A source / drain electrode formed on the substrate;

An aligned copper oxide semiconductor nanowire pattern formed on the source / drain electrode;

A gate insulating layer formed on the aligned copper oxide semiconductor nanowire pattern; And

And a gate electrode formed on the gate insulating film,

And may be a copper oxide semiconductor nanowire field effect transistor array of a top-gate structure. The diameter of the copper oxide semiconductor nanowire fabricated on the field effect transistor array may be 10 nm to 1000 nm, and the length may be very long in the meter range.

By providing a method of aligning copper oxide semiconductor nanowires in a desired position, orientation, and shape, a field effect transistor array using copper oxide semiconductor nanowires can be manufactured in a quick and simple manner. In particular, according to the present invention, a large area high performance nanowire field effect transistor array can be manufactured with higher speed and accuracy.

In addition, the field effect transistor array using the copper oxide semiconductor nanowire manufactured by the above method has high charge mobility and current on / off ratio, and thus can be used as a flat or flexible display, a memory, a direct circuit, a chemical and biological sensor, It is also suitable for RFID.

1 is a process diagram showing a method of manufacturing a bottom-gate structure copper oxide semiconductor nanowire field effect transistor.
2 is a process diagram showing a method of manufacturing a copper oxide semiconductor nanowire field-effect transistor having a top-gate structure.
FIG. 3A shows a schematic diagram of an electric field assisted robotic nozzle printer for use in manufacturing a copper oxide semiconductor precursor / organic polymer composite nanowire pattern.
4 is a SEM photograph showing a copper oxide nanowire pattern arranged on a source / drain electrode.

Hereinafter, embodiments of the present invention will be described in detail. However, the present invention is not limited thereto, and the present invention is only defined by the scope of the following claims.

One embodiment of the present invention provides a method of fabricating a field effect transistor array in which copper oxide semiconductor nanowires are aligned, and more particularly, to a method of fabricating a field effect transistor array in which copper oxide semiconductors < RTI ID = 0.0 > A method of fabricating a nanowire field effect transistor array is provided.

As used herein, the term "aligned" nanowires refers to nanowires whose nanowires are positioned and oriented as desired.

A method of fabricating a copper oxide semiconductor nanowire field effect transistor array of a bottom-gate structure according to an embodiment of the present invention includes: forming a gate electrode on a substrate; Forming a gate insulating film on the substrate on which the gate electrode is formed; Dissolving a copper oxide semiconductor precursor and an organic polymer in distilled water or an organic solvent to provide a composite solution of a copper oxide semiconductor precursor / organic polymer; Aligning the copper oxide semiconductor precursor / organic polymer composite nanowire on the gate insulating film by dropping a copper oxide semiconductor precursor / organic polymer complex solution at a position vertically 10 μm to 20 mm away from the gate insulating film; Heating the aligned copper oxide semiconductor precursor / organic polymer composite nanowire to form a pattern of aligned copper oxide semiconductor nanowires; And forming a source / drain electrode on the aligned copper oxide semiconductor nanowire pattern.

FIG. 1 is a process diagram showing a method of manufacturing a bottom-gate structure copper oxide semiconductor nanowire field effect transistor for explaining an embodiment of the present invention. Specifically, forming a gate electrode on a substrate 110 ); Forming a gate insulating layer on the substrate on which the gate electrode is formed (120); Providing a composite solution of a copper oxide semiconductor precursor / organic polymer (130); (140) aligning the copper oxide semiconductor precursor / organic polymer composite nanowire on the gate insulating film by dropping the copper oxide semiconductor precursor / organic polymer complex solution; Heating the aligned copper oxide semiconductor precursor / organic polymer composite nanowire to form a pattern of aligned copper oxide semiconductor nanowires (150); And forming (160) source / drain electrodes on the aligned copper oxide semiconductor nanowire pattern.

A method of fabricating a copper oxide semiconductor nanowire field effect transistor array of a top-gate structure according to another embodiment of the present invention includes: forming a source / drain electrode on a substrate; Dissolving a copper oxide semiconductor precursor and an organic polymer in distilled water or an organic solvent to provide a complex solution of a copper oxide semiconductor precursor / organic polymer; Aligning the copper oxide semiconductor precursor / organic polymer composite nanowire by dropping a copper oxide semiconductor precursor / organic polymer complex solution at a point 10 to 20 mm away from the source / drain electrode vertically; Heating the aligned copper oxide semiconductor precursor / organic polymer composite nanowire to form a pattern of aligned copper oxide semiconductor nanowires; Forming a gate insulating film on the aligned copper oxide semiconductor nanowire pattern; And forming a gate electrode on the gate insulating film.

FIG. 2 is a process diagram illustrating a method of manufacturing a copper-oxide semiconductor nanowire field effect transistor having a top-gate structure for explaining an embodiment of the present invention. Specifically, a step 210 of forming a source / ); Providing (220) a composite solution of a copper oxide semiconductor precursor / organic polymer; (230) dropping the composite solution of the copper oxide semiconductor precursor / organic polymer to align the copper oxide semiconductor precursor / organic polymer composite nanowire; Heating the aligned copper oxide semiconductor precursor / organic polymer composite nanowire to form a pattern of aligned copper oxide semiconductor nanowires (240); Forming a gate insulating layer on the aligned copper oxide semiconductor nanowire pattern (250); And forming a gate electrode on the gate insulating layer (260).

The substrate may be selected from the group consisting of an insulating material, a metal material, a carbon material, a composite material of a conductor and an insulating film, and combinations thereof. For example, the insulating material may be a glass plate, a plastic film, paper, fabric, wood, etc. The metal material may be copper, aluminum, titanium, gold, silver, stainless steel, As the material, graphene, carbon nanotubes, graphite amorphous carbon and the like can be used. As the conductor / insulating film composite material, a semiconductor wafer substrate, a silicon (Si) / silicon dioxide (SiO ₂ ) ) / Aluminum oxide (Al ₂ O ₃ ) substrate can be used.

The gate electrode may be selected from the group consisting of a metal, a conductive polymer, a carbon material, a doped semiconductor, and combinations thereof. Specifically, the metal may be selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Y, Zr, Nb, Mo, Ta, W, Ni, Cu, Ag, As the conductive polymer, polyethylene dioxythiophene (PEDOT), polyaniline, or polypyrrole may be used. As the carbon material, graphene, carbon nanotube, graphite amorphous carbon, or the like may be used. The doped semiconductor may be doped-Si, doped-Ge, or the like.

The gate electrode may be formed by a method such as drop casting, spin-coating, dip-coating, E-beam evaporation, thermal evaporation, ), Soft-lithography, sputtering, or the like can be used, and can be appropriately selected according to the purpose.

The thickness of the gate electrode is 1 nm to 1 占 퐉, and more preferably 3 nm to 500 nm.

Wherein the gate insulating film comprises an insulating material such as an insulating polymer, an inorganic oxide, a polymer electrolyte, an acid group such as a carboxyl group (-COOH) or a hydroxyl group (-OH), a thiol group (-SH), or a trichlorosilane group (-SiCl ₃ ) Self-assembled molecules, and combinations thereof. Specifically, examples of the insulating polymer include polyvinyl alcohol (PVA), polyethylene oxide (PEO), polystyrene (PS), polycaprolactone (PCL), polyacrylonitrile (PAN), poly (methyl methacrylate) Polyimide, polyvinylidene fluoride (PVDF), polyaniline (PANI), polyvinyl chloride (PVC), nylon, poly (acrylic acid), poly (chlorostyrene), poly (dimethylsiloxane) Poly (ethyl acrylate), poly (ethyl vinyl acetate), poly (ethyl-co-vinyl acetate), poly (ethylene terephthalate), poly poly (styrene sulfonic acid) salt, poly (styrene sulfonyl fluoride), poly (styrene-co-acrylonitrile), poly (methacrylic acid) salt, Styrene-co-butadiene), poly (styrene-co-divinylbenzene), poly Poly (ethylene oxide), poly (ether ether ketone), polyethylene, polyethyleneimine, polyisoprene, polyimide, polyimide, polyimide, , Poly (lactide), poly (propylene), polysulfone, polyurethane, poly (vinylpyrrolidone), CYTOP (amorphous fluoropolymer product of Asahi Glass), or a combination thereof. is silicon dioxide (SiO _2), aluminum oxide (Al ₂ O _3), tantalum oxide (Ta ₂ O _5), titanium dioxide (TiO _2), strontium titanate (SrTiO _3), zirconium (ZrO ₂₎ oxide, Hafnium (HfO ₂ ), hafnium silicate (HfSiO ₄ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), lanthanum aluminate (a-LaAlO ₃ ) or a combination thereof may be used.

Examples of the polymer electrolyte include LiClO ₄ , LiTFSI (lithium-bis (trifluoromethylsulfonyl) imide), LiPSS (lithium poly (styrenesulfonate)), and [EMIM] [TFSI] (Methylimidazolium bis (trifluoromethylsulfonyl) imide), [BMIM] [PF ₆ ] (1-butyl-3-methylimidazolium hexafluorophosphate) or [EMIM] [OctOSO ₃ ] PS-PMMA-PS or PEGDA (poly (ethylene glycol) diacrylate), or an ionic liquid containing at least one selected from the group consisting of 1-ethyl-3-methylimidazolium n -octyl sulfate A combination of these may be used.

The gate insulating layer may be formed by a method such as drop casting, spin-coating, dip-coating, E-beam evaporation, thermal evaporation, ), Soft-lithography, atomic layer deposition, or sputtering may be used, but not limited thereto, and may be manufactured using any of the known general methods.

The thickness of the gate insulating film may be 1 nm to 10 탆, and more preferably 3 nm to 500 nm.

In general, the source and drain may comprise a transparent oxide semiconductor with a conductive electrode and a capacitance charge injection scheme for controlling and / or modulating the source-drain current.

The source / drain electrodes may be selected from the group consisting of a metal, a conductive polymer, a carbon material, a doped semiconductor material, and combinations thereof.

The metal may be selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Y, Zr, Nb, Mo, Ta, W, Ni, Cu, Ag, As the conductive molecule, polyethylene dioxythiophene (PEDOT), polyaniline, polypyrrole, or a combination thereof may be used. As the carbon material, graphene, carbon nanotube, graphite amorphous carbon, or the like may be used have.

The source / drain electrodes may be formed by a method such as drop casting, spin-coating, dip-coating, E-beam evaporation, thermal evaporation, printing, soft-lithography, or sputtering may be used, but is not limited thereto, and may be manufactured using any of the known general methods.

The thickness of the source / drain electrode is 1 nm to 1 占 퐉, and more preferably 3 nm to 500 nm.

The gate electrode should be formed to include a gap between the source and drain electrodes.

Since copper oxide semiconductors have a wide band gap, they are widely used as electronic and optoelectronic materials. One embodiment of the present invention provides a method of fabricating a transistor of a bottom-gate structure or a top-gate structure by aligning the copper oxide semiconductor nanowire on a gate insulating film or a source / drain electrode.

Specifically, a method of aligning the copper oxide semiconductor nanowires is as follows.

First, a solution containing a copper oxide semiconductor precursor and an organic polymer is prepared.

The copper oxide semiconductor precursor may be selected from the group consisting of copper trifloroacetate, copper acetate hydrate, copper acetylacetonate, copper i-butyrate, copper carbonate ), Copper chloride, copper chloride hydrate, copper ethylacetoacetate, copper 2-ethylhexanoate, copper fluoride, copper formate Copper formate hydrate, Copper gluconate, Copper hexafluoroacetylacetonate, Copper hexafluoroacetylacetonate hydrate, Copper methoxide, Copper hexafluoroacetylacetonate hydrate, Copper formate hydrate, Copper gluconate, Copper hexafluoroacetylacetonate, Copper hexafluoroacetylacetonate hydrate, Copper neodecanoate, copper nitrate hydrate, copper nitrate, Copper perchlorate hydrate, Copper sulfate, Copper sulfate hydrate, Copper tartrate hydrate, Copper trifluoroacetylacetonate, Copper triphosphate, Copper sulphate, Copper sulphate, Copper sulphate, Copper trifluoromethanesulfonate, tetraaminecopper sulfate hydrate, and combinations thereof. ≪ Desc / Clms Page number 7 >

Examples of the organic polymer include polyvinyl alcohol (PVA), polyethylene oxide (PEO), polystyrene (PS), polycaprolactone (PCL), polyacrylonitrile (PAN), poly (methyl methacrylate) (Polyvinylidene fluoride) (PVDF), polyaniline (PANI), polyvinyl chloride (PVC), nylon, poly (acrylic acid), poly (chlorostyrene), poly (dimethylsiloxane) Poly (ethyl acrylate), poly (ethyl vinyl acetate), poly (ethyl-co-vinyl acetate), poly (ethylene terephthalate), poly (lactic acid- poly (styrenesulfonyl fluoride), poly (styrene-co-acrylonitrile), poly (styrene-co-glycolic acid) (co-butadiene), poly (styrene-co-divinylbenzene), poly Poly (ethylene oxide), poly (etheretherketone), polyethylene, polyethyleneimine, polyisoprene, polyimide, polyimide, polyimide, , Polylactide, polypropylene, polysulfone, polyurethane, poly (vinylpyrrolidone), and combinations thereof.

In the preparation of the solution, water or an organic solvent may be used as the solvent. Examples of the organic solvent include dichloroethylene, trichlorethylene or chloroform, chlorobenzene, dichlorobenzene, dichloromethane, styrene, dimethylformamide, Methylene chloride, methyl sulfoxide, tetrahydrofuran, xylene, toluene, cyclohexene, 2-methoxyethanol, ethanolamine, acetonitrile, butyl alcohol, isopropyl alcohol, ethanol, methanol, acetone or mixtures thereof.

The mixing ratio of the copper oxide semiconductor precursor and the organic polymer may be a weight ratio of 10:90 to 90:10. When the mixing ratio of the copper oxide semiconductor precursor and the organic polymer is within the above range, the finally obtained copper oxide semiconductor nanowire can be formed with a uniform diameter without breaking. Since the organic polymer is decomposed by heating, if the proportion of the organic polymer is more than 90 wt%, the amount of copper oxide semiconductor remaining after heating is insufficient, so that the nanowire may not be uniformly formed and may be broken. If the proportion of the organic polymer is less than 10% by weight, the viscosity of the copper oxide semiconductor precursor-organic polymer solution is too low and the copper oxide semiconductor precursor / organic polymer composite nanowire pattern is not formed properly by the electric field assistant robotic nozzle printer Problems may arise.

The concentration of the copper oxide semiconductor precursor and the organic polymer solution may be 3 to 20 wt%. When the mixing ratio of the copper oxide semiconductor precursor and the organic polymer is within the above range and the concentration of the copper oxide semiconducting precursor and the organic polymer solution is in the above range, the viscosity of the solution is sufficient and the electric field assisted robotic nozzle A nanowire pattern can be formed through the printer. If the concentration of the copper oxide semiconductor precursor and the organic polymer solution is less than 3% by weight, the viscosity may be too low to form a droplet of the solution rather than the nanowire. If the concentration of the copper oxide semiconductor precursor and the organic polymer solution exceeds 20% by weight, the viscosity may be too high and the solution may not be properly discharged through the electric field assisted robotic nozzle printer.

By using a solution of the copper oxide semiconductor precursor / organic polymer composite prepared above, a solution of the copper oxide semiconductor precursor / organic polymer complex can be formed in a thickness of 10 [micro] m to 10 [micro] m or more vertically from the gate insulating film of the bottom-gate structure field effect transistor array substrate or from the source / drain of the top- 20 And the solution of the copper oxide semiconductor precursor / organic polymer complex is dropped at a point spaced by a few millimeters from the surface of the copper oxide semiconductor precursor / organic polymer composite nanowire.

As the distance of the dropping of the copper oxide semiconductor precursor / organic polymer complex solution from the substrate is increased, the speed of the aligned nanowires in the horizontal direction increases as the solution of the copper oxide semiconductor film / organic polymer complex drops, The possibility of bending is increased. Thus, the nanowire is disturbed, making it difficult to align the nanowire in the desired direction or parallel. However, in the present invention, by dropping a composite solution of a copper oxide semiconductor precursor / organic polymer at a distance of 10 탆 to 20 탆 over the gate insulating film or the source / drain electrode, it is possible to suppress the warping of the nanowire, To align the nanowires. FIG. 4 shows SEM photographs of copper oxide nanowires formed on the source / drain electrodes, and nanowires aligned in parallel directions can be identified.

In addition, the step of aligning the ordered copper oxide semiconductor precursor / organic polymer composite nanowire may be performed by an electric field assisted robotic nozzle printer. The electric field assisted robotic nozzle printer comprises i) a solution storage device for containing a copper oxide semiconductor precursor / organic polymer complex solution; ii) a nozzle device for discharging the solution supplied from the solution storage device; iii) a voltage applying device for applying a high voltage to the nozzle; iv) a collector for fixing the substrate; v) a robot stage for moving the collector in a horizontal direction; vi) a micro-distance adjuster for moving the collector in a vertical direction; And vii) a collector that supports the collector below the collector.

3 is a schematic diagram of an electric field assisted robotic nozzle printer 100. Fig. Specifically, the electric field assisted robotic nozzle printer 100 includes a solution storing device 10, a discharge regulator 20, a nozzle 30, a voltage applying device 40, a collector 50, a robot stage 60, A stone quartz plate 61, and a micro distance adjuster 70.

The solution storage device 10 stores a solution of a copper oxide semiconductor precursor / organic polymer complex and supplies the solution to the nozzle 30 so that the nozzle 30 can discharge the solution. The solution storage device 10 may be in the form of a syringe. The solution storage device 10 may be made of plastic, glass, or stainless steel. The storage capacity of the solution storage device 10 may be selected within the range of about 1 쨉 l to about 5,000 ml. Preferably, it can be selected within the range of about 10 μl to about 50 ml. In the case of the solution storage device 10 made of stainless steel, there is a gas inlet (not shown) for injecting gas into the solution storage device 10 so that the solution is discharged out of the solution storage device . On the other hand, a plurality of solution storage devices 10 for forming copper oxide nanowires having a core shell structure may be formed.

The discharge regulator 20 is configured to apply pressure to the solution in the solution storage device 10 to discharge the copper oxide semiconductor precursor / organic polymer complex solution in the solution storage device 10 at a constant rate through the nozzle 30 Section. As the discharge regulator 20, a pump or gas pressure regulator may be used. The discharge regulator 20 can adjust the discharge speed of the solution within a range of 1 nL / min to 50 mL / min. When a plurality of solution storage devices 10 are used, each solution storage device 10 is provided with a separate discharge controller 20 so that it can operate independently. A gas pressure regulator (not shown) may be used as the discharge regulator 20 in the case of the solution storage device 10 made of stainless steel.

The nozzle 30 receives the solution of the copper oxide semiconductor precursor / organic polymer complex from the solution storage device 10 and discharges the solution. The solution is discharged from the nozzle 30 at the end of the nozzle 30, Can be formed. The diameter of the nozzle 30 may range from about 15 [mu] m to about 1.5 mm.

The nozzle 30 may include a single nozzle, a dual-concentric nozzle, and a triple-concentric nozzle. In the case of forming an organic wire having a core shell structure, two or more organic solutions can be discharged using a double nozzle or a triple nozzle. In this case, two or three solution storage devices 10 may be connected to the double or triple nozzles.

The voltage application device 40 may include a high voltage generating device for applying a high voltage to the nozzle 30. The voltage application device 40 may be electrically connected to the nozzle 30 through the solution storage device 10, for example. The voltage application device 40 can apply a voltage of about 0.1 kV to about 30 kV. There is an electric field between the nozzle 30 to which the high voltage is applied by the voltage applying device 40 and the collector 50 which is grounded and the droplet formed at the end of the nozzle 30 by the electric field becomes the Taylor cone, And the nanowires are formed continuously at the ends.

The collector 50 is a portion where nanowires formed from the solution discharged from the nozzle 30 are aligned. The collector 50 is flat and movable on a horizontal plane by the robot stage 60 beneath it. The collector 50 is grounded to have a grounding characteristic relative to the high voltage applied to the nozzle 30. [ Reference numeral 51 denotes that the collector 50 is grounded. The collector 50 may be made of a conductive material, for example, a metal, and may have a flatness within a range of 0.5 μm to 10 μm (when the flatness of a completely horizontal surface has a value of 0, Represents the maximum error value from the plane).

The robot stage 60 is a means for moving the collector 50. The robot stage 60 is driven by a servo motor and can move at a precise speed. The robot stage 60 can be controlled to move in two directions, for example, x-axis and y-axis on a horizontal plane. The robot stage 60 can move the distance in a range of 100 nm to 100 cm, for example, within a range of 10 μm or more and 20 cm or less. The moving speed of the robot stage 60 may range from 1 mm / min to 60,000 mm / min. The robot stage 60 may be installed on a base plate 61 and may have a planar view within a range of 0.5 μm to 5 μm. The distance between the nozzle 30 and the collector 50 can be controlled to be constant by the plan view of the stone pot 61. The stone stone table 61 can control the precision of the organic wire pattern by suppressing the vibration generated by the operation of the robot stage.

The micro distance adjuster 70 is a means for adjusting the distance between the nozzle 30 and the collector 50. The distance between the nozzle 30 and the collector 50 can be adjusted by moving the solution storage device 10 and the nozzle 30 vertically by the micro distance adjuster 70. [

The micro distance adjuster 70 may include a jog 71 and a micrometer 72. The jog 71 can be used to roughly adjust the distance in mm or centimeters, and the fine adjuster 72 can be used to adjust a fine distance of at least 10 microns. The distance between the nozzle 30 and the collector 50 can be precisely adjusted by the fine adjuster 72 after the nozzle 30 approaches the collector 50 with the jog 71. [ The distance between the nozzle 30 and the collector 50 by the micro distance adjuster 70 can be adjusted in the range of 10 to 20 mm.

The three-dimensional path of nanowires emanating from the nozzle in electrospinning can be represented by the following equation (DH Reneker, AL Yarin, H. Fong, S. Koombhongse, "Bending instability of polymer solutions in electrospinning & Appl. Phys., 87, 9, 4531-4546 (2000)). As can be seen from the following formulas (1a) and (1b), the greater the distance between the collector and the nozzle, the greater the perturbation of the nanowire.

‥‥‥‥‥‥‥ 식 (1a)

... (1a)

‥‥‥‥‥‥‥ 식 (1b) 이다.

... (1b).

L is a constant representing the length scale, lambda is the perturbation wavelength, z is the collector of the nanowire (z (z), z = 0), and h is the distance between the nozzle and the collector. From the above equations (1a) and (1b), it can be seen that the larger the distance h between the collector and the nozzle with respect to the same z value, the larger the x and y values indicating the disturbance of the nanowire.

For example, the collector 50 parallel to the xy plane can be moved on the xy plane by the robot stage 60 and can be moved between the nozzle 30 and the collector 50 in the z- Can be adjusted.

The electric field assisted robotic nozzle printer 100 according to an embodiment of the present invention can sufficiently narrow the distance between the nozzle 30 and the collector 50 by a unit of tens to several tens of micrometers so that the collector 50 so that the pattern of the precise nanowire can be formed by the movement of the collector 50.

The formation of the nanowire pattern by movement of the collector makes it possible to form a more precise nanowire pattern by reducing the disturbance parameter of the organic wire pattern as compared to the movement of the nozzle.

Meanwhile, the electric field assisted robotics nozzle printer 100 may be placed in the housing. The housing may be formed of a transparent material. The housing is hermetically sealed and can inject gas into the housing through a gas inlet (not shown). The gas to be injected may be nitrogen, dry air or the like, and the copper oxide semiconductor precursor / organic polymer complex solution, which is easily oxidized by moisture by the injection of the gas, can be stably maintained. Also, a ventilator and a lamp may be installed in the housing. The role of the ventilator is to control the evaporation rate of the solvent when the nanowire is formed by controlling the vapor pressure in the housing. In robotic nozzle printing, which requires rapid evaporation of the solvent, the speed of the ventilator can be controlled to help evaporate the solvent. The evaporation rate of the solvent affects the morphological and electrical properties of the copper oxide semiconductor nanowires. If the evaporation rate of the solvent is too high, the solution will dry out at the nozzle tip before the copper oxide semiconductor nanowires are formed, causing the nozzle to clog. If the evaporation rate of the solvent is too slow, the nanowires of the solid copper oxide semiconductor precursor / organic polymer complex will not form and will be placed on the collector in liquid form. The liquid-state copper oxide semiconductor precursor / organic polymer complex solution can not be used for device fabrication because it does not have characteristic electrical properties of the nanowire. As the evaporation rate of the solvent affects the formation of the nanowires, the ventilator plays an important role in nanowire formation.

Specifically, the step of aligning the ordered copper oxide semiconductor precursor / organic polymer composite nanowire using the electric field assisted robotic nozzle printer 100 may include the steps of: i) depositing the copper oxide semiconducting precursor / Supplying an organic polymer complex solution; ii) discharging the copper oxide semiconductor precursor / organic polymer composite solution from the nozzle while applying a high voltage to the nozzle through the voltage application device of the electric field assisted robotic nozzle printer, When the semiconductor precursor / organic polymer composite solution is ejected, moving the collector on which the substrate is placed in the horizontal direction.

The solution containing the copper oxide semiconductor precursor and the organic polymer is injected into the syringe 10 and then discharged from the nozzle 30 by the syringe pump 20. In this case, An enemy is formed. When a voltage in the range of 0.1 kV to 30 kV is applied to the nozzle 30 using the high voltage generator 40, the droplet is scattered by the electrostatic force between the charge formed in the droplet and the collector 50 And sticks to the substrate on the collector 50 while extending in the direction of the electric field.

At this time, as the droplet increases, a copper oxide semiconductor precursor / organic polymer composite nanowire having a longer length in one direction than the other direction from the droplet may be formed. The diameter of the copper oxide semiconductor precursor / organic polymer composite nanowire can be adjusted to the micrometer level or the sub micrometer level by adjusting the applied voltage and the nozzle size.

The copper oxide semiconductor precursor / organic polymer composite nanowire formed from the charged discharge of the nozzle 30 may be aligned with the substrate on the collector 50. [ At this time, by adjusting the distance between the nozzle 30 and the collector 50 to be within the range of 10 μm to 20 mm, the copper oxide semiconductor precursor / organic polymer composite nanowire is not entangled, On the substrate. At this time, the distance between the nozzle 30 and the collector 50 can be adjusted using the micro distance adjuster 70.

Thus, by moving the collector 50 very finely as the microdistance adjuster 70 and the fine adjuster 72, the copper oxide semiconductor precursor / organic polymer composite nanowire can be positioned at a desired position on the substrate in a desired direction, As shown in Fig.

By annealing the copper oxide semiconductor precursor / organic polymer composite nanowires aligned to the desired position, direction and number of times at a temperature of 100 ° C to 900 ° C for 1 to 24 hours, a pattern of aligned copper oxide semiconductor nanowires is formed can do. More specifically, it is heated at a temperature in the range of 400 ° C to 800 ° C for 3 hours to 10 hours. In this case, the copper oxide semiconductor crystal having the most uniform size is formed and the charge mobility is improved. Heating utilizes equipment that can be heated uniformly globally, such as a furnace or a vacuum hot-plate.

Since the organic polymer is decomposed as the copper oxide semiconductor precursor / organic polymer composite nanowire is heated, and the copper oxide semiconductor precursor is converted into a copper oxide semiconductor, an aligned nanowire-type copper oxide semiconductor can be obtained. The copper oxide semiconductor nanowire has a diameter ranging from 10 nm to 1000 nm, and the diameter of the copper oxide semiconductor nanowire can be controlled according to the ratio and concentration of the copper oxide semiconductor precursor and the organic polymer. One feature of the copper oxide semiconductor nanowires produced is a small diameter and hence a large surface area. A diameter much smaller than that of visible light or visible light can be easily produced, and a very large surface area can be formed.

Another embodiment of the present invention provides a field effect transistor array fabricated according to the above-described fabrication method.

Specifically, the field effect transistor array includes:

A gate electrode formed on the substrate;

A gate insulating film formed on the gate electrode;

An aligned copper oxide semiconductor nanowire pattern formed on the gate insulating film; And

And a source / drain electrode formed on the aligned copper oxide semiconductor nanowire pattern. The bottom-gate structure may be a copper oxide semiconductor nanowire field effect transistor array.

Alternatively, the field effect transistor array comprises:

A source / drain electrode formed on the substrate;

An aligned copper oxide semiconductor nanowire pattern formed on the source / drain electrode;

A gate insulating layer formed on the aligned copper oxide semiconductor nanowire pattern; And

And a gate electrode formed on the gate insulating film,

And may be a copper oxide semiconductor nanowire field effect transistor array of a top-gate structure.

The field effect transistor array using the copper oxide semiconductor nanowire has high charge mobility and current on / off ratio and is suitable for use in a flat or flexible display, memory, integrated circuits, chemical and biological sensors, and RFID.

Hereinafter, specific embodiments of the present invention will be described. However, the embodiments described below are only intended to illustrate or explain the present invention, and thus the present invention should not be limited thereto.

Example

Example  One

A bottom-gate structure copper oxide nanowire transistor having an area of 7 cm x 7 cm was fabricated according to the method described below.

First, copper trifloro acetate hydrate (Cu (CO2CF3) 2 · xH20) (25 wt%) and polyvinylpyrrolidone (PVP) (10 wt%) were dissolved in dimethylformamide and tetrahydrofuran, A precursor / PVP solution was prepared. The concentration of the precursor / PVP solution was 31 wt%. The prepared copper oxide precursor / PVP solution was placed in a syringe of an electric field assisted robotic nozzle printer, and a copper oxide precursor / PVP solution was discharged from the nozzle while applying a voltage of about 0.5 kV to the nozzle. A copper oxide precursor / PVP composite nanowire pattern was formed on the substrate of the collector moved by the robot stage.

At this time, the diameter of the used nozzle was 100 mu m and the applied voltage was 0.5 kV. The distance between the nozzle and the collector was kept constant at 7 mm. The moving distance in the Y axis direction of the robot stage was 200 mu m, and the moving distance in the X axis direction was 15 cm. The size of the collector was 20 cm x 20 cm, and the size of the substrate on the collector was 7 cm x 7 cm. The substrate was a silicon (Si) wafer in which a silicon oxide film (SiO ₂ ) was coated to a thickness of 300 nm. At this time, silicon (Si) and silicon oxide film (SiO ₂ ) were used as gate and gate insulating films, respectively.

The ordered copper oxide precursor / PVP nanowire pattern was heated from the furnace to 450 < 0 > C each for 1 hour to form aligned copper oxide nanowire patterns. And 100 nm thick gold was deposited thereon by thermal evaporation to form a source / drain electrode. A total of 144 copper oxide nanowire transistor devices were fabricated on the substrate.

Example  2 to 4

Examples 2 to 4 were prepared in the same manner as in Example 1 except that the ordered copper oxide precursor / PVP nanowire pattern was heated from the furnace at 450 DEG C for 2 hours and 4 hours, respectively, Nanowire transistors were fabricated.

Example  5

A top-gate structure copper oxide nanowire transistor array having an area of 7 cm x 7 cm was fabricated using a nanowire field effect transistor fabrication method of a top-gate structure according to another embodiment of the present invention.

The source / drain electrodes were formed by depositing 100 nm thick gold on the silicon (Si) wafer coated with a silicon oxide film (SiO ₂ ) with a thickness of 100 nm through thermal vapor deposition. This was used as a substrate.

 Copper triflorato acetate hydrate (Cu (CO2CF3) 2 · xH20) (25 wt%) and polyvinylpyrrolidone (PVP) (10 wt%) were dissolved in dimethylformamide and tetrahydrofuran to give a copper oxide precursor / PVP solution. The concentration of the copper oxide precursor / PVP solution was 31 wt%. The prepared copper oxide precursor / PVP solution was placed in a syringe of an electric field assisted robotic nozzle printer, and a precursor / PVP solution was discharged from the nozzle while applying a voltage of about 0.5 kV to the nozzle. A copper oxide precursor / PVP composite nanowire pattern was formed on the substrate of the collector moved by the robot stage.

At this time, the diameter of the used nozzle was 100 mu m, the distance between the nozzle and the collector was 7 mm, and the applied voltage was 0.5 kV. The moving distance in the Y axis direction of the robot stage was 200 mu m, and the moving distance in the X axis direction was 15 cm. The size of the collector was 20 cm x 20 cm, and the size of the substrate on the collector was 7 cm x 7 cm.

The aligned copper oxide precursor / PVP nanowire pattern was heated from the furnace to 450 < 0 > C for 1 hour each to form aligned copper oxide nanowire patterns. And polystyrene (PS) having a thickness of 50 nm was coated thereon by spin coating to form a gate insulating film. A 100 nm thick titanium layer was deposited on the gate insulating layer by thermal evaporation to form a gate electrode.

Example  6 to 8

Examples 6 to 8 produced transistors according to the same method as in Example 5, except that aligned copper oxide precursor / PVA nanowire patterns were heated from the furnace to 450 占 폚 for 2 hours and 4 hours, respectively.

(Charge mobility and current on / Off-beat  Measure)

The charge mobility and the current on / off ratio were measured for the transistors manufactured in Examples 1 to 10 above.

The average mobility of Examples 1 to 4 has an average value of about 0.1 cm ² / V · s when the drain voltage is 40 V and the gate voltage is 25 V, and the average on / off ratio is about 10 ⁴ Respectively.

The average mobility of Examples 5 to 8 has an average value of about 0.12 cm ² / V · s when the drain voltage is 40 V and the gate voltage is 27.5 V, and the average on / off ratio is about 10 ⁴ Respectively.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. As will be understood by those skilled in the art. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

Claims (26)

Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate on which the gate electrode is formed;
Dissolving a copper oxide semiconductor precursor and an organic polymer in distilled water or an organic solvent to provide a copper oxide semiconductor precursor / organic polymer composite solution;
Aligning the copper oxide semiconductor precursor / organic polymer composite nanowire on the gate insulating film by dropping the copper oxide semiconductor precursor / organic polymer composite solution at a position vertically 10 μm to 20 mm away from the gate insulating film;
Heating the aligned copper oxide semiconductor precursor / organic polymer composite nanowire to form a pattern of aligned copper oxide semiconductor nanowires; And
And forming a source / drain electrode on the aligned copper oxide semiconductor nanowire pattern. ≪ Desc / Clms Page number 20 > Forming a source / drain electrode on the substrate;
Dissolving a copper oxide semiconductor precursor and an organic polymer in distilled water or an organic solvent to provide a copper oxide semiconductor precursor / organic polymer complex solution;
Aligning the copper oxide semiconductor precursor / organic polymer composite nanowire by dropping the copper oxide semiconductor precursor / organic polymer composite solution at a point 10 to 20 mm away from the source / drain electrode vertically;
Heating the aligned copper oxide semiconductor precursor / organic polymer composite nanowire to form a pattern of aligned copper oxide semiconductor nanowires;
Forming a gate insulating film on the aligned copper oxide semiconductor nanowire pattern; And
And forming a gate electrode on the gate insulating film. ≪ RTI ID = 0.0 > 11. < / RTI > 3. The method according to claim 1 or 2,
The step of forming the ordered copper oxide semiconductor nanowire pattern comprises heating the copper oxide semiconductor precursor / organic polymer composite nanowire at a temperature of 100 ° C to 900 ° C for 1 to 24 hours, Method of manufacturing a nanowire field effect transistor array. 3. The method according to claim 1 or 2,
The step of aligning the ordered copper oxide semiconductor precursor / organic polymer composite nanowires is performed by an electric field assisted robotic nozzle printer, the electric field assisted robotic nozzle printer
i) a solution storage device for containing a copper oxide semiconductor precursor / organic polymer complex solution;
ii) a nozzle device for discharging the solution supplied from the solution storage device;
iii) a voltage applying device for applying a high voltage to the nozzle;
iv) a collector for fixing the substrate;
v) a robot stage for moving the collector in a horizontal direction;
vi) a micro-distance adjuster for moving the collector in a vertical direction; And
vii) a lithotripsy support for supporting the collector. < Desc / Clms Page number 20 > 5. The method of claim 4,
The step of aligning the ordered copper oxide semiconductor precursor / organic polymer composite nanowire
i) supplying the copper oxide semiconductor precursor / organic polymer complex solution to the solution storage device;
ii) discharging the copper oxide semiconductor precursor / organic polymer composite solution from the nozzle while applying a high voltage to the nozzle through the voltage application device of the electric field assisted robotic nozzle printer,
Wherein when the copper oxide semiconductor precursor / organic polymer composite solution is discharged from the nozzle, the collector on which the substrate is placed is moved in the horizontal direction. 5. The method of claim 4,
Wherein the vertical distance between the collector and the nozzle is 10 占 퐉 to 20 占 퐉. 3. The method according to claim 1 or 2,
Wherein the substrate is selected from the group consisting of an insulating material, a metal material, a carbon material, and a composite material of a conductor and an insulating film. 3. The method according to claim 1 or 2,
The step of forming the gate electrode, the gate insulating film, and the source / drain electrode may be performed independently of each other by a method selected from the group consisting of drop casting, spin-coating, dip-coating, A copper oxide semiconductor nanowire field effect, which is performed by one method selected from the group consisting of E-beam evaporation, thermal evaporation, printing, soft-lithography and sputtering. A method of manufacturing a transistor array. 3. The method according to claim 1 or 2,
Wherein the gate electrode and the source / drain electrode are each independently selected from the group consisting of a metal, a conductive polymer, a carbon material, a doped semiconductor, and combinations thereof. 3. The method according to claim 1 or 2,
Wherein the gate electrode has a thickness of 1 nm to 1 占 퐉; a method of manufacturing a copper oxide semiconductor nanowire field effect transistor array 3. The method according to claim 1 or 2,
Wherein the gate insulating film has a self-assembled structure including at least one functional group selected from the group consisting of a carboxyl group (-COOH), a hydroxyl group (-OH), a thiol group (-SH), and a trichlorosilane group (-SiCl ₃ ) A method for fabricating a copper oxide semiconductor nanowire field effect transistor array, the method comprising the steps of: 3. The method according to claim 1 or 2,
Wherein the thickness of the gate insulating film is 1 nm to 10 占 퐉. 3. The method according to claim 1 or 2,
Wherein the source / drain electrode has a thickness of 1 nm to 1 占 퐉. 3. The method according to claim 1 or 2,
The copper oxide semiconductor precursor may be selected from the group consisting of copper trifloroacetate, copper acetate hydrate, copper acetylacetonate, copper i-butyrate, copper carbonate ), Copper chloride, copper chloride hydrate, copper ethylacetoacetate, copper 2-ethylhexanoate, copper fluoride, copper formate Copper formate hydrate, Copper gluconate, Copper hexafluoroacetylacetonate, Copper hexafluoroacetylacetonate hydrate, Copper methoxide, Copper hexafluoroacetylacetonate hydrate, Copper formate hydrate, Copper gluconate, Copper hexafluoroacetylacetonate, Copper hexafluoroacetylacetonate hydrate, Copper neodecanoate, copper nitrate hydrate, copper nitrate, Copper perchlorate hydrate, Copper sulfate, Copper sulfate hydrate, Copper tartrate hydrate, Copper trifluoroacetylacetonate, Copper triflate hydrate, Wherein the copper oxide nanowire field effect transistor array is selected from the group consisting of copper trifluoromethanesulfonate, tetraaminecopper sulfate hydrate, and combinations thereof. 3. The method according to claim 1 or 2,
The organic polymer may be at least one selected from the group consisting of polyvinyl alcohol (PVA), polyethylene oxide (PEO), polystyrene (PS), polycaprolactone (PCL), polyacrylonitrile (PAN), poly (methyl methacrylate) Polyvinylidene fluoride (PVDF), polyaniline (PANI), polyvinyl chloride (PVC), nylon, poly (acrylic acid), poly (chlorostyrene), poly (dimethylsiloxane) Poly (ethyl acrylate), poly (ethyl vinyl acetate), poly (ethyl-co-vinyl acetate), poly (ethylene terephthalate), poly (lactic acid- Poly (styrene sulfonate), poly (styrene-co-acrylonitrile), poly (styrene-co (meth) acrylate) -Butadiene), poly (styrene-co-divinylbenzene), poly (vinyl acetate), poly Poly (vinyl alcohol), polyacrylamide, polybenzimidazole, polycarbonate, poly (dimethylsiloxane-co-polyethylene oxide), poly (etheretherketone), polyethylene, polyethyleneimine, polyisoprene, polylactide , Polypropylene, polysulfone, polyurethane, poly (vinyl pyrrolidone), and combinations thereof. ≪ Desc / Clms Page number 20 > 3. The method according to claim 1 or 2,
The organic solvent is selected from the group consisting of dichloroethylene, trichlorethylene, chloroform, chlorobenzene, dichlorobenzene, dichloromethane, styrene, dimethylformamide, dimethylsulfoxide, tetrahydrofuran, xylene, toluene, cyclohexene, 2 Wherein the metal oxide is selected from the group consisting of methoxyethanol, ethanolamine, acetonitrile, butyl alcohol, isopropyl alcohol, ethanol, methanol, and acetone, and combinations thereof. 3. The method according to claim 1 or 2,
The step of providing the copper oxide semiconducting precursor / organic polymer complex solution may comprise the step of mixing the copper oxide semiconductor precursor and the organic polymer in distilled water or organic solvent at a weight ratio of 10:90 to 90:10 in a concentration of 3 to 20% Thereby forming a copper oxide semiconductor nanowire field effect transistor array. A copper oxide semiconductor nanowire field effect transistor array fabricated by the method of claim 1,
A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
An aligned copper oxide semiconductor nanowire pattern formed on the gate insulating film; And
And a source / drain electrode formed on the aligned copper oxide semiconductor nanowire pattern.
Bottom - gate structure of copper oxide semiconductor nanowire field effect transistor array. 11. A copper oxide semiconductor nanowire field effect transistor array fabricated by the method of claim 2,
A source / drain electrode formed on the substrate;
An aligned copper oxide semiconductor nanowire pattern formed on the source / drain electrode;
A gate insulating layer formed on the aligned copper oxide semiconductor nanowire pattern; And
And a gate electrode formed on the gate insulating film,
Copper oxide semiconductor nanowire field effect transistor array of top-gate structure. 20. The method according to claim 18 or 19,
Wherein the copper oxide semiconductor nanowire has a diameter of 10 nm to 1000 nm. 20. The method according to claim 18 or 19,
Wherein the substrate is selected from the group consisting of an insulating material, a metal material, a carbon material, a semiconductor, and a composite material of a conductor and an insulating film. 20. The method according to claim 18 or 19,
Wherein the gate electrode and the source / drain electrode are each independently selected from the group consisting of a metal, a conductive polymer, a carbon material, a doped semiconductor, and combinations thereof. 20. The method according to claim 18 or 19,
Wherein the gate electrode has a thickness of 1 nm to 1 占 퐉. 20. The method according to claim 18 or 19,
Wherein the gate insulating film has a self-assembled structure including at least one functional group selected from the group consisting of a carboxyl group (-COOH), a hydroxyl group (-OH), a thiol group (-SH), and a trichlorosilane group (-SiCl ₃ ) Wherein the dielectric layer is selected from the group consisting of a dielectric layer, a dielectric layer, a dielectric layer, a dielectric layer, a dielectric layer, a dielectric layer, and a dielectric layer. 20. The method according to claim 18 or 19,
Wherein the thickness of the gate insulating film is 1 nm to 10 占 퐉. 20. The method according to claim 18 or 19,
Wherein the source / drain electrode has a thickness of 1 nm to 1 占 퐉.

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