KR20140101563A - Group iii-v based transistor and method of fabricating the same - Google Patents

Group iii-v based transistor and method of fabricating the same Download PDF

Info

Publication number
KR20140101563A
KR20140101563A KR1020130014873A KR20130014873A KR20140101563A KR 20140101563 A KR20140101563 A KR 20140101563A KR 1020130014873 A KR1020130014873 A KR 1020130014873A KR 20130014873 A KR20130014873 A KR 20130014873A KR 20140101563 A KR20140101563 A KR 20140101563A
Authority
KR
South Korea
Prior art keywords
semiconductor layer
semiconductor
layer
iii
layers
Prior art date
Application number
KR1020130014873A
Other languages
Korean (ko)
Inventor
모토노부 타케야
이관현
곽준식
정영도
이강녕
Original Assignee
서울반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 서울반도체 주식회사 filed Critical 서울반도체 주식회사
Priority to KR1020130014873A priority Critical patent/KR20140101563A/en
Priority to EP14152839.8A priority patent/EP2765611A3/en
Priority to US14/177,825 priority patent/US9219137B2/en
Priority to JP2014024947A priority patent/JP2014154887A/en
Priority to CN201410049097.5A priority patent/CN103985742A/en
Publication of KR20140101563A publication Critical patent/KR20140101563A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A III-V system transistor and a method of manufacturing the same are disclosed. The III-V system transistor includes a semiconductor structure having an upper surface and a lower surface and including a III-V semiconductor layer, wherein the semiconductor structure includes a first conductive type semiconductor layer including an upper surface, a lower surface, A first semiconductor layer; A second semiconductor layer of a first conductivity type surrounding the lower surface and the side surface of the first semiconductor layer of the first conductivity type; And a second conductive semiconductor layer located between the first semiconductor layer and the second semiconductor layer to separate the first semiconductor layer and the second semiconductor layer from each other. And a second conductivity type semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer to provide a vertical III-V transistor having a normally-off characteristic.

Description

(III-V) BASED TRANSISTOR AND METHOD OF FABRICATING THE SAME < RTI ID = 0.0 >

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor used in a power device, and more particularly, to a III-V transistor and a manufacturing method thereof.

A power device using a silicon semiconductor is used for a power amplifier circuit, a power supply circuit, and a motor drive circuit.

However, due to the limitations of silicon semiconductors, the demand for high-voltage, low-resistance, and high-speed silicon devices has reached their limits and it has become difficult to meet market demands. Therefore, development of a III-V system device having features such as high breakdown voltage, high temperature operation, high current density, high-speed switching and low on-resistance is under consideration.

However, the proposed III-V device has a horizontal structure in which the source, the gate, and the drain are arranged along the surface of the substrate, so that it is not suitable for a power device requiring a large current. Furthermore, there is a problem that it is not easy to realize a normally-off operation required for a power device. In addition, there is a problem that current collapse occurs in which electrons are trapped between the semiconductor and the protective film and the drain current is reduced in a high voltage operation of 600 V or more.

On the other hand, to solve the problem of the horizontal structure, a vertical GaN-based device can be manufactured using a GaN substrate. However, GaN substrates are currently expensive and their use is limited. Alternatively, a GaN-based semiconductor layer may be grown on a sapphire substrate or a silicon substrate to produce a device having a vertical structure. However, due to the lattice constant mismatch between the growth substrate and the semiconductor layer, a high density of threading dislocation) is generated and it is difficult to increase the pressure resistance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved vertical-structured III-V transistor having normally-off characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a III-V system transistor having a vertical structure without using an expensive GaN substrate and a manufacturing method thereof.

Another problem to be solved by the present invention is to provide a vertical-structured III-V transistor having high breakdown voltage characteristics and a method of manufacturing the same.

A III-V system transistor according to an aspect of the present invention includes a semiconductor structure having an upper surface and a lower surface and including a III-V semiconductor layer, the semiconductor structure including an upper surface, a lower surface, A first semiconductor layer of a first conductivity type including a first conductive type; A second semiconductor layer of a first conductivity type surrounding the lower surface and the side surface of the first semiconductor layer of the first conductivity type; And a second conductive semiconductor layer located between the first semiconductor layer and the second semiconductor layer to separate the first semiconductor layer and the second semiconductor layer from each other. And a second conductivity type semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer to provide a vertical III-V transistor having a normally-off characteristic.

The III-V system transistor includes: a source electrode located on an upper surface of the semiconductor structure and connected to the first semiconductor layer; A gate electrode for forming a channel between the first semiconductor layer and the second semiconductor layer; And a drain electrode located on a lower surface of the semiconductor structure. Thereby, a transistor having a vertical structure in which the source electrode and the drain electrode are located on the upper surface and the lower surface of the semiconductor structure is provided. On the other hand, the gate electrode may be positioned on the upper surface of the semiconductor structure to form a channel near the upper surface of the semiconductor structure.

Furthermore, the III-V system transistor may further include a gate insulating film located between the gate electrode and the semiconductor structure.

The semiconductor structure may further include a low-resistance layer located in a region to which the drain electrode is connected. The low-resistance layer can be formed by etching damage by partially etching the second semiconductor layer, and exhibits properties similar to the high-concentration n-type impurity doping layer. The contact resistance of the drain electrode can be lowered by the low resistance layer.

In addition, the III-V system transistor may further include a supporting substrate. The drain electrode may be positioned between the support substrate and the semiconductor structure. Further, the supporting substrate may be a silicon substrate or a metal substrate.

The III-V system transistor may further include a current blocking layer located on the lower surface of the semiconductor structure under the second conductive semiconductor layer. The current blocking layer covers a region having a high actual density of the semiconductor structure and blocks a leakage current. Thus, a III-V system transistor having high breakdown voltage characteristics can be provided.

The upper surface of the semiconductor structure may include an N-face of the gallium nitride-based semiconductor layer. It is difficult to etch the Ga-face of the gallium nitride-based semiconductor layer using wet etching. For this reason, a method of etching the surface by plasma dry etching is used, so that etching damage caused by plasma is generated in the semiconductor layer. Such etching damage on Ga-face is difficult to remove by wet etching. On the other hand, the N-plane of the gallium nitride-based semiconductor layer can be wet-etched using KOH, H 3 PO 4 , NaOH or the like. Therefore, since the upper surface opposite to the support substrate includes the N-surface, the surface of the semiconductor structure can be etched by using the wet etching, thereby preventing the etching damage caused by the plasma. Furthermore, the N-plane may be patterned using dry etching and the damaged portion by plasma may be easily removed using wet etching.

Meanwhile, the first and second semiconductor layers of the first conductivity type may be an n-type gallium nitride based semiconductor layer, and the second conductive type semiconductor layer may be a p-type gallium nitride based semiconductor layer. In addition, the second semiconductor layer may be a doped layer or an undoped layer with a lower impurity concentration than the first semiconductor layer. Since the second semiconductor layer has a relatively high specific resistance, high breakdown voltage characteristics can be achieved.

In some embodiments, the III-V transistor may include a plurality of second conductivity type semiconductor layer regions. Also, at least two first semiconductor layers may be disposed in the second conductive semiconductor layer region.

The first semiconductor layer may have a stripe shape. At this time, the second conductive semiconductor layer is formed along the first semiconductor layer and has a stripe shape.

Further, the III-V system transistor includes: a source electrode connected to the first semiconductor layer; A gate electrode for forming a channel between the first semiconductor layer and the second semiconductor layer; And a drain electrode connected to the lower surface of the semiconductor structure, and the source electrode may be connected to each first semiconductor layer.

The III-V transistor may include current blocking layers located on the lower surface of the semiconductor structure under the second conductive type semiconductor layers, and the drain electrode may be formed on the semiconductor layer between the current blocking layers. And can contact the lower surface of the structure.

Furthermore, the III-V system transistor may further include a low-resistance layer formed on the lower surface of the semiconductor structure connected to the drain electrode.

The method for manufacturing a III-V system transistor according to another aspect of the present invention includes the steps of growing a III-V system semiconductor layer on a growth substrate, patterning the III-V system semiconductor layer to form stripes, The III-V system semiconductor layers are grown to surround the side surfaces and the upper surface of the stripe to form a flat upper surface, and the plurality of Attaching a supporting substrate to the III-V system semiconductor layers and separating the growth substrate from the plurality of semiconductor layers. Thus, a transistor having a vertical structure can be manufactured.

The III-V semiconductor layers may include a second conductive semiconductor layer surrounding the stripe and a second semiconductor layer of a first conductivity type surrounding the second conductive semiconductor layer. Further, the III-V semiconductor layers may further include a first semiconductor layer of a first conductivity type disposed between the second conductive semiconductor layer and the stripe and surrounding the stripe.

And a second conductivity type semiconductor layer is disposed between the first semiconductor layer of the first conductivity type and the second semiconductor layer of the first conductivity type to provide a vertical type transistor having a normally-off characteristic can do.

In some embodiments, the III-V system transistor manufacturing method may further include forming current blocking layers on the III-V system semiconductor layers before attaching the supporting substrate. The current blocking layers may cover the upper regions of the stripes, respectively. A region having a high actual potential density is formed near the upper region of the stripes. Therefore, it is possible to provide a transistor having a high withstand voltage characteristic by blocking the leakage current generated by the current blocking layers.

Further, impurities may be implanted on the III-V semiconductor layers using the current blocking layers as a mask to form a low-resistance layer. The contact resistance of the drain electrode can be lowered by the low resistance layer.

On the other hand, separating the growth substrate may include separating the growth substrate from the semiconductor layers using laser lift-off techniques, and dry etching and wet etching the exposed semiconductor layer. Etching damage due to plasma can be removed by the wet etching.

The III-V system transistor manufacturing method further includes forming a source electrode connected to the stripe, forming a gate insulating film covering a region between the source electrodes, and forming a gate electrode on the gate insulating film can do.

And a second conductivity type semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer to provide a vertical III-V transistor having a normally-off characteristic. Further, by adopting the vertical structure, the thickness of the semiconductor structure can be adjusted to easily provide a transistor having a high breakdown voltage characteristic, and furthermore, the high breakdown voltage characteristic can be further enhanced by disposing the current blocking layer in the high dislocation density region. Further, since the transistor is manufactured using the N-face semiconductor layer, it is not necessary to use an expensive GaN substrate, and a GaN-based transistor free from etching damage due to plasma can be provided. In addition, a power device capable of high-pressure-resistance, low-resistance, and high-speed operation can be provided by using the III-V system transistor.

1 is a schematic cross-sectional view for explaining a III-V system transistor according to an embodiment of the present invention.
FIGS. 2 to 9 are schematic cross-sectional views illustrating a method of manufacturing a III-V system transistor according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of constituent elements can be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 is a schematic cross-sectional view for explaining a III-V system transistor according to an embodiment of the present invention.

1, the III-V system transistor includes a semiconductor structure 20, a source electrode 43, a drain electrode 35, a gate electrode 47, a current blocking layer 31, a gate insulating film 45, And a substrate 41.

The semiconductor structure 20 includes an upper surface and a lower surface and includes a first semiconductor layer 25 of a first conductivity type, a second conductivity type semiconductor layer 27, and a second semiconductor layer 27 of a first conductivity type, . ≪ / RTI > Further, the semiconductor structure 20 may include a low-resistance layer 33. Here, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited thereto and vice versa. Here, the "III-V system semiconductor" may be a GaAs system, a GaP system or a GaN system, and may be a two-component system, a three-component system or a four- Hereinafter, a transistor using a gallium nitride semiconductor is mainly described, but the present invention is not limited to a gallium nitride semiconductor.

 The first semiconductor layer 25 of the first conductivity type includes a stripe 23a and may further include an additional first conductive semiconductor layer 25a covering a side surface and a bottom surface of the stripe 23a.

The stripe 23a is located on the upper surface of the semiconductor structure 20 and may have a long structure in one direction. For example, the stripe 23a may have a longitudinal direction in the <1-100> or <11-20> direction. In addition, the lower surface of the stripe 23a may be c-surface. The stripe 23a may be formed of, for example, gallium nitride of the first conductivity type.

The stripe 23a may be formed of a first conductivity type semiconductor layer having a relatively high impurity concentration, for example, an n-type semiconductor layer.

On the other hand, the additional first conductivity type semiconductor layer 25a surrounds the lower surface and the side surface of the stripe 23a. The additional first conductive semiconductor layer 25a may be formed of the same III-V semiconductor as the stripe 23a and may have the same or similar doping concentration as the stripe 23a. In this case, the stripe 23a and the additional first conductive type semiconductor layer 25a may be combined with each other to form a single first semiconductor layer 25. Alternatively, the additional first conductive type semiconductor layer 25a may be omitted, and the stripe 23a may be the first semiconductor layer 25.

On the other hand, the lower surface of the additional first conductivity type semiconductor layer 25a may be c-plane, and the side surface may be (11-22) or (1-101) plane. On the other hand, when the additional first conductivity type semiconductor layer 25a is a gallium nitride (GaN) semiconductor layer, the upper surface may be an N-face and the lower surface may be a Ga-face .

The second conductive semiconductor layer 27 surrounds the lower surface and the side surface of the first semiconductor layer 25. 1, a part of the second conductivity type semiconductor layer 27 is exposed on the upper surface of the semiconductor structure 20. The second conductive semiconductor layer 27 may be formed of GaN doped with a p-type impurity (for example, magnesium).

The second conductive semiconductor layer 27 is formed along the first semiconductor layer 25 and may have a stripe shape. A plurality of regions of the second conductivity type semiconductor layer 27 may be formed in the semiconductor structure 20 and the first semiconductor layer 25 may be located in each second conductivity type semiconductor layer 27 region. The spacing between the second conductive type semiconductor layers 27 may be in the range of about 7 to 9 [mu] m. The width of the second conductivity type semiconductor layer 27 located between the first semiconductor layer 25 and the second semiconductor layer 29 on the upper surface of the semiconductor structure 20 may be, have. Further, as shown in FIG. 1, at least two first semiconductor layers 25 may be disposed in each second conductive type semiconductor layer 27 region. The first semiconductor layers 25 located in the region of the second conductivity type semiconductor layer 27 may be located within a width of approximately 7 mu m.

On the other hand, the second semiconductor layer 29 of the first conductivity type surrounds the lower surface and the side surface of the second conductive semiconductor layer 27. Therefore, the second semiconductor layer 29 may cover the side surface and the lower surface of the first semiconductor layer 25, and the second conductive semiconductor layer 27 may surround the first semiconductor layer 25 and the second semiconductor layer 25, (29) to separate them. The second semiconductor layer 29 may be formed of GaN, for example, and a part thereof is exposed on the upper surface of the semiconductor structure 20, as shown in the figure. Further, the second semiconductor layer 29 may be exposed on the lower surface of the semiconductor structure 20. The second semiconductor layer 29 of the first conductivity type may be a semiconductor layer to which an impurity (e.g., silicon) is intentionally doped, but is not limited thereto. For example, the second semiconductor layer 29 of the first conductivity type may be an undoped layer formed without intentional doping of impurities. The second semiconductor layer 29 of the first conductivity type has a relatively low impurity concentration as compared with the first semiconductor layer 25.

On the other hand, the second semiconductor layer 29 may also be exposed on the lower surface of the semiconductor structure 29. The thickness Th of the second semiconductor layer 29 located below the lower surface of the second conductive semiconductor layer 27 can be adjusted to improve the withstand voltage characteristics of the III-V transistor.

The thickness Th is formed to be larger than the thickness x n of the depletion layer formed in the second semiconductor layer under the applied bias voltage condition.

The thickness (x n ) and thickness (xp) of the depletion layer can be expressed by the following equations, respectively.

(Equation 1)

Figure pat00001

Equation (2)

Figure pat00002

Where N is the acceptor concentration (cm -3 ), N d is the donor concentration (cm -3 ), N is the donor concentration (cm -3 ) Φ B denotes a built-in potential (V), and Vb denotes a bias voltage (V).

The contact potential difference &amp;phiv; B can be expressed by the following equation (3).

(Equation 3)

Figure pat00003

Here, k is the Boltzmann constant (J / K), T is the temperature (K), and n i is the carrier concentration (cm -3 ) of the intrinsic semiconductor.

On the other hand, the maximum electric field E max can be expressed by the following equation (4).

(Equation 4)

Figure pat00004

Here, Emax represents the maximum electric field generated at the p-n junction surface under a given bias voltage.

When the acceptor concentration Na of the second conductivity type semiconductor layer 27 and the donor concentration Nd and the bias voltage Vb of the second semiconductor layer 29 are given, ) And (3), the thickness and the maximum electric field of the depletion layer can be obtained. At this time, when the second semiconductor layer 29 is a GaN layer, the breakdown of the GaN layer occurs at about 3.3 MV / cm or more. Therefore, the bias voltage should be adjusted so that the maximum electric field is smaller than 3.3 MV / cm, , The thickness of the depletion layer should be smaller than the thickness Th.

For example, Na is 3E17 ㎝ - and 3, Nd is summarized in thickness and the maximum electric field of the depletion layer of the case of 2E16 ㎝ -3, bias voltage (Vb) in the table below.

V b (V) x n (占 퐉) x p (μm) E max (MV / cm) 600 5.44 0.36 2.07 900 6.66 0.44 2.53 1200 7.69 0.51 2.93 1500 8.6 0.57 3.27

Referring to Table 1, when the bias voltage is 1500V, Emax is 3.27 MV / cm, which is smaller than 3.3 MV / cm. Therefore, if the thickness Th is larger than 8.6 占 퐉 in the thickness of the depletion layer xn, no dielectric breakdown occurs. Therefore, when the thickness Th is at least about 9 mu m under the acceptor concentration of the acceptor and the donor, the withstand voltage characteristic of 1500 V or more can be achieved.

On the other hand, the low-resistance layer 33 is located on the lower surface of the semiconductor structure 20. The low resistance layer 33 may be, for example, an etch damage layer formed by partially dry etching the second semiconductor layer 29. The low resistance layer 33 is located under the region between the second conductivity type semiconductor layers 27 and may have a narrower width than the separation distance between the second conductivity type semiconductor layers 27. [ The low resistance layer 33 lowers the contact resistance of the drain electrode 35.

The current blocking layer 31 is located on the lower surface of the semiconductor structure 20 under the first semiconductor layer 25. The current blocking layer 31 may have a width approximately equal to or slightly larger than the width of the lower surface of the second conductive semiconductor layer 27. A relatively high density of electric potential is generated below the first semiconductor layer 25. [ The current blocking layer 31 prevents current leakage through the actual potential formed below the first semiconductor layer 25. In addition, the current blocking layers 31 may be located below the plurality of second conductive semiconductor layers 27, and the low resistive layer 33 may be formed between the current blocking layers 31.

On the other hand, the drain electrode 35 is located on the lower surface side of the semiconductor structure 20. The drain electrode 35 may be connected to the semiconductor structure 20 through the high concentration impurity doping layer 33 and may be formed of a metal layer such as Ti / Pt / Au. In addition, the drain electrode 35 may cover the current blocking layer 31. The drain electrode 35 may include a bonding metal for bonding the supporting substrate 41 and the semiconductor structure 20. [

The supporting substrate 41 is not particularly limited as long as it can be used as a substrate for supporting the semiconductor structure 20. However, the metal substrate may suitably be used for the silicon substrate in consideration of the price of the support substrate 41 and the manufacturing process.

On the other hand, the source electrode 43 is electrically connected to the first semiconductor layers 25. The source electrode 43 may also be connected to the semiconductor layer 27 of the second conductivity type. As shown in FIG. 1, at least two first semiconductor layers 25 are disposed in the region of the second conductivity type semiconductor layer 27, and the source electrode 43 includes first semiconductor layers 25, And may be connected to the second conductivity type semiconductor layer 27. Alternatively, the source electrode 43 may be connected to the first semiconductor layer 25, and a separate electrode may be connected to the second conductive type semiconductor layer 27. The source electrode 43 is formed of a conductive material that makes an ohmic contact with the first semiconductor layer 25 and can further make an ohmic contact with the second conductive semiconductor layer 27. The source electrode 43 may be formed of, for example, Ti / Ni / Pt / Au. Although two source electrodes 43 connected to the first semiconductor layers 25 are shown in Fig. 1, these source electrodes 43 can be electrically connected to each other to maintain the same potential.

On the other hand, the gate insulating film 45 may cover the source electrode 43 and the upper surface of the semiconductor structure 20. The gate insulating film 45 may be formed of SiO 2 and may be formed to a thickness of 60 to 1000 nm.

The gate electrode 47 is located on the gate insulating film 45. The gate electrode 47 may also be formed so as to cover the source electrode 43. [ The gate electrode 47 is formed on the second conductive semiconductor layer 27 exposed on the upper surface of the semiconductor structure 20 so as to form a channel between the first semiconductor layer 25 and the second semiconductor layer 29 And may be located in an area between the semiconductor layers 27 of the second conductivity type.

Hereinafter, the operation of the transistor according to the present embodiment will be briefly described.

First, if no voltage is applied to the gate electrode 47, a channel is not formed between the first semiconductor layer 25 and the second semiconductor layer 29, and the carriers are cut off. Thus, the transistor according to the present invention has a normally off-off characteristic.

On the other hand, when a positive voltage is applied to the gate electrode 47, a channel is formed in the second conductive type semiconductor layer 27 under the gate electrode 47. Therefore, the carriers (electrons) move from the source electrode 43 to the drain electrode 45 by the voltage difference between the source electrode 43 and the drain electrode 35. [ Here, the carrier moves from the first semiconductor layer 25 to the second semiconductor layer 29 through the channel under the gate electrode 47, and the region between the second conductive semiconductor layers 27 . Thereafter, the carrier is moved to the drain electrode 35. At this time, the current blocking layer 31 prevents carriers from moving downward in the vertical direction from the first semiconductor layers 25.

FIGS. 2 to 9 are cross-sectional views illustrating a method of manufacturing a III-V system transistor according to an embodiment of the present invention.

Referring to FIG. 2, a III-V system semiconductor layer 23 is grown on a growth substrate 21. The growth substrate 21 is not particularly limited as long as it is a substrate on which the III-V semiconductor layer 23 can be grown. For example, the growth substrate 21 may be a sapphire substrate on which GaN can be grown.

The semiconductor layer 23 and the III-V semiconductor layers described below may be grown using MOCVD or MBE techniques. The semiconductor layer 23 may include a core layer (not shown). The semiconductor layer 23 may be formed of, for example, GaN doped with an n-type impurity.

Referring to FIG. 3, the semiconductor layer 23 is patterned to form stripes 23a. The semiconductor layer 23 may be patterned using photolithography and etching processes. For example, when the substrate 21 is a c-plane sapphire substrate, the stripes may be formed along the <1-100> direction or the <11-20> direction. During the patterning of the semiconductor layer 23, the growth substrate 21 may also be partly recessed to form a protrusion 21a under the stripe 23a.

The stripes 23a may be formed such that at least two stripes 23a are relatively close to each other as shown. For example, the stripes 23a located close to each other may be located within a width in the range of about 7 mu m, and the separation distance between the stripes 23a distant from each other may be about 10 mu m. As shown, the side surfaces of the stripes 23a may be perpendicular to the surface of the substrate 21, but the present invention is not limited thereto, and the side surfaces may be inclined.

Referring to FIG. 4, an additional first conductive semiconductor layer 25a may be grown on the stripe 23a. An additional first conductive semiconductor layer 25a may be grown to restore etch damage formed on the sides of the stripes 23a. The additional first conductive semiconductor layer 25a may be formed to have the same or similar doping concentration as the stripe 23a and may be formed of a semiconductor layer of the same composition. Thus, the stripe 23a and the additional second conductive semiconductor layer 25a are integrated to form the first semiconductor layer 25. Alternatively, the additional first conductive semiconductor layer 25a may be omitted. In this case, the stripe 23a becomes the first semiconductor layer 25.

A further first conductive semiconductor layer 25a is grown on the upper surface and the side surface of the stripe 23a and a second conductive semiconductor layer 27 and a second conductive semiconductor layer 25 are formed on the first semiconductor layer 25, The second semiconductor layer 29 is grown. The second conductivity type semiconductor layer 27 is grown on the upper surface and the side surface of the first semiconductor layer 25 and the second semiconductor layer 29 of the first conductivity type is grown on the upper surface And are grown on the sides. The second semiconductor layer 29 is formed to have a lower impurity concentration than the first semiconductor layer 25 and may be formed as an undoped layer without intentional doping of the impurity. The second semiconductor layer 29 may be formed to have a thickness of about 5 탆 to 10 탆 on the second conductive semiconductor layer 27.

When the substrate 21 is a c-plane sapphire substrate, the upper surfaces of the semiconductor layers 25a, 27 and 29 are grown in the c-plane in the [0001] direction and the upper surface is in the Ga plane. On the other hand, the side surfaces of the semiconductor layers 25a, 27 and 29 are grown in the [11-22] or [1-101] direction to become the (11-22) or (1-101) The lateral direction of the semiconductor layers 25a, 27, 29 is determined in accordance with the longitudinal direction of the stripe 23a. For example, when the longitudinal direction of the stripe 23a is < 1-100 >, the side surface is a (11-22) surface, and when the longitudinal direction of the stripe 23a is < (1-101) plane.

The top growth rate and the lateral growth rate of each of the semiconductor layers 25a, 27, and 29 can be controlled by adjusting the growth conditions, particularly, the growth temperature and / or the flow rate of each source gas. Therefore, the thicknesses of the semiconductor layers 25a, 27, and 29 in the vertical direction and the lateral direction can be controlled to be the same or different from each other.

On the other hand, since the potential is transferred from the stripe 23a to the top surface, a dislocation-defective region is formed on the upper surface of the stripe 23a, but a region with a low dislocation density is formed in the lateral direction.

4, the second conductive semiconductor layers 27 grown on the respective stripes 23a are separated from each other, and the second semiconductor layers 29 can be joined together to form one layer .

Referring to FIG. 5, current blocking layers 31 may be formed on the second semiconductor layer 29. The current blocking layers 31 may be formed by forming an SiO2 layer on the second semiconductor layer 29 and then forming the second conductive semiconductor layers 27 while leaving a portion covering the first semiconductor layers 25. [ To expose a region between the gate electrode and the gate electrode. The width of the current blocking layer 31 may be similar to or larger than the width of the upper surface of the second conductive semiconductor layer 27. A high density real potential can be formed in the semiconductor layers (for example, 25a, 27, 29) grown in the vertical direction on the upper surface of the stripe 23a. The current blocking layer 31 is located on a region where a relatively high density real potential is formed to block current leakage through the actual potential.

On the other hand, the second semiconductor layer 29 can be dry-etched using the current blocking layers 31 as a mask, etch damage is induced in the second semiconductor layer 29 by dry etching, A low resistance layer 33 may be formed in an area between the barrier layers 31. [

On the other hand, when the second conductive semiconductor layer 27 is formed of Mg-doped GaN, the current blocking layers 31 are formed before or after the current blocking layers 31 are formed, Type semiconductor layer 27 can be activated. For example, Mg may be activated in the second conductive semiconductor layer 27 by heat treatment at a temperature of 700 to 900 ° C for 30 minutes.

Referring to FIG. 6, the supporting substrate 41 is then attached on the second semiconductor layer 29. The support substrate 41 is formed by forming a metal layer 35 (drain electrode) such as Ti / Pt / Au on the current blocking layer 31 and the low resistance layer 33 and then forming the metal layer 35 ). &Lt; / RTI &gt; Alternatively, the supporting substrate 41 may be formed on the metal layer 35 by plating. The supporting substrate 41 is not particularly limited, but may be, for example, a ceramic or semiconductor substrate such as AlN, AlSi or Si, or the same metal substrate including Cu, Mo and / or W. Or the support substrate 41 and the metal layer 35 may be integrally formed.

The metal layer 35 is electrically connected to the low resistance layer 33 and is located between the support substrate 41 and the second semiconductor layer 29. The metal layer 35 may function as a drain electrode.

Referring to FIG. 7, the growth substrate 21 is separated from the semiconductor layers. The growth substrate 21 may be separated from semiconductor layers such as the stripe 23a using, for example, a laser lift-off technique.

When the growth substrate 21 is separated using the laser lift-off technique, the surface of the exposed semiconductor layers may be damaged by the laser, and also Ga droplets may remain. Thus, the surface of the exposed semiconductor layers can be entirely recessed using a wet etch, or a dry etch and a wet etch, whereby the damaged surface or Ga agglomerates can be removed. The dry etching may be performed using reactive ion etching (RIE), and the wet etching may be performed using a KOH, NaOH or H 3 PO 4 solution. In order to prevent the side surfaces of the support substrate 41 and the second semiconductor layer 29 from being etched and damaged during the wet etching, the etch stopper film, such as photoresist, (29) and the lower surface of the support substrate (41).

The semiconductor structure 20 is formed by the wet etching and the upper surface thereof includes exposed surfaces of the first semiconductor layer 25, the second conductive semiconductor layer 27, and the second semiconductor layer 29 do.

Referring to FIG. 8, a source electrode 43 is formed on the semiconductor structure 20. The source electrode 43 is electrically connected to each first semiconductor layer 25. The source electrode 43 may also be connected to the second conductive semiconductor layer 27. The source electrode 43 is located within the region of the second conductive semiconductor layer 27 as shown and is spaced from the second semiconductor layer 29. The source electrode 43 may have a metal laminated structure, for example, Ti / Ni / Pt / Au, and may be formed using a photolithography process or a lift-off process after forming a metal layer.

Referring to FIG. 9, a gate insulating film 45 is formed. The gate insulating film 45 may be formed of, for example, a silicon oxide film or a silicon nitride film. The gate insulating film 45 may cover the second conductive semiconductor layer 27 and the second semiconductor layer 29 exposed on the upper surface of the semiconductor structure 20 and may further cover the source electrode 43 . The gate insulating layer 45 may be patterned using a photolithography and etching process, whereby the source electrode 43 may be partially exposed.

On the other hand, a gate electrode 47 is formed on the gate insulating film 45 to produce a III-V system transistor. The gate electrode 45 is located on the second conductive semiconductor layer 27 located between the first semiconductor layer 25 and the second semiconductor layer 29 and exposed on the upper surface of the semiconductor structure 20 And may be located on the second semiconductor layer 29 exposed on the upper surface of the semiconductor structure 20. [ The gate electrode 47 is formed to form a channel between the first semiconductor layer 25 and the second semiconductor layer 29 and the gate electrode 47 is formed so as to move from the first semiconductor layer 25 to the second semiconductor layer 29 The carriers are uniformly dispersed in the region between the second conductive semiconductor layers 27.

While various embodiments have been described above, the elements described in the specific embodiments may be applied to other embodiments as long as they do not depart from the scope of the invention. On the other hand, a power device can be provided by using the various III-V transistors described above.

20: semiconductor structure, 21: growth substrate,
21a: protruding portion, 23: III-V semiconductor layer, 23a: stripe,
25a: an additional first conductivity type semiconductor layer,
25: a first semiconductor layer of a first conductivity type, 27: a second semiconductor layer of a second conductivity type
29: a second semiconductor layer of the first conductivity type, 35: a metal layer (drain electrode)
41: support substrate, 43: source electrode,
45: gate insulating film, 47: gate electrode

Claims (22)

A semiconductor structure having an upper surface and a lower surface and including a III-V semiconductor layer,
The semiconductor structure may include:
A first semiconductor layer of a first conductivity type including a top surface, a bottom surface, and a side surface;
A second semiconductor layer of a first conductivity type surrounding the lower surface and the side surface of the first semiconductor layer of the first conductivity type; And
And a second conductive semiconductor layer which is located between the first semiconductor layer and the second semiconductor layer and separates the first semiconductor layer from the second semiconductor layer. The method according to claim 1,
A source electrode located on an upper surface of the semiconductor structure and connected to the first semiconductor layer;
A gate electrode for forming a channel between the first semiconductor layer and the second semiconductor layer; And
And a drain electrode located on a lower surface of the semiconductor structure. The method of claim 2,
And a gate insulating film disposed between the gate electrode and the semiconductor structure. The method of claim 2,
Wherein the semiconductor structure further includes a high concentration impurity doping layer located in a region to which the drain electrode is connected. The method of claim 2,
Further comprising a support substrate,
And the drain electrode is located between the supporting substrate and the semiconductor structure. The method of claim 5,
Wherein the supporting substrate is a silicon substrate or a metal substrate. The method according to claim 1,
And a current blocking layer located on the lower surface of the semiconductor structure under the second conductive type semiconductor layer. The method according to claim 1,
And an upper surface of the semiconductor structure includes an N-face of a gallium nitride-based semiconductor layer. The method according to claim 1,
The first and second semiconductor layers of the first conductivity type are n-type gallium nitride based semiconductor layers,
And the second conductive semiconductor layer is a p-type gallium nitride-based semiconductor layer. The method of claim 9,
Wherein the second semiconductor layer is a doped layer or an undoped layer with a lower impurity concentration than the first semiconductor layer. The method according to claim 1,
A plurality of second conductivity type semiconductor layer regions,
And at least two first semiconductor layers are disposed in the second conductive semiconductor layer region. The method of claim 11,
Wherein the first semiconductor layer has a stripe shape. The method of claim 11,
A source electrode connected to the first semiconductor layer;
A gate electrode for forming a channel between the first semiconductor layer and the second semiconductor layer; And
And a drain electrode connected to the lower surface of the semiconductor structure,
And the source electrode is connected to each first semiconductor layer. 14. The method of claim 13,
And current blocking layers located on the lower surface of the semiconductor structure under the second conductive type semiconductor layers,
And the drain electrode contacts the lower surface of the semiconductor structure between the current blocking layers. 15. The method of claim 14,
And a high concentration impurity doping layer formed on a lower surface of the semiconductor structure connected to the drain electrode. A III-V system semiconductor layer is grown on a growth substrate,
The III-V system semiconductor layer is patterned to form stripes, the upper surface of the growth substrate is recessed,
The III-V system semiconductor layers are grown on the stripe so as to surround the side surfaces and the upper surface of the stripe to form a flat upper surface,
A supporting substrate is attached to the plurality of III-V system semiconductor layers,
And separating the growth substrate from the plurality of semiconductor layers. 18. The method of claim 16,
The III-
A second conductive semiconductor layer surrounding the stripe, and a second semiconductor layer of a first conductivity type surrounding the second conductive semiconductor layer. 18. The method of claim 17,
The III-V system semiconductor layer further includes a first semiconductor layer of a first conductivity type disposed between the second conductive semiconductor layer and the stripe and surrounding the stripe. 18. The method of claim 16,
Before attaching the supporting substrate,
Further comprising forming current blocking layers on the III-V semiconductor layers,
Wherein the current blocking layers each cover an upper region of the stripe. The method of claim 19,
Further comprising implanting impurities on the III-V semiconductor layers using the current blocking layers as a mask to form a heavily doped impurity doped layer. 18. The method of claim 16,
To separate the growth substrate,
Separating the growth substrate from the semiconductor layers using a laser lift-off technique,
A method for fabricating a III-V system transistor, comprising: dry-etching and wet-etching an exposed semiconductor layer. 23. The method of claim 21,
A source electrode connected to the stripe is formed,
Forming a gate insulating film covering an area between the source electrodes,
And forming a gate electrode on the gate insulating film.
KR1020130014873A 2013-02-12 2013-02-12 Group iii-v based transistor and method of fabricating the same KR20140101563A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020130014873A KR20140101563A (en) 2013-02-12 2013-02-12 Group iii-v based transistor and method of fabricating the same
EP14152839.8A EP2765611A3 (en) 2013-02-12 2014-01-28 Vertical gallium nitride transistors and methods of fabricating the same
US14/177,825 US9219137B2 (en) 2013-02-12 2014-02-11 Vertical gallium nitride transistors and methods of fabricating the same
JP2014024947A JP2014154887A (en) 2013-02-12 2014-02-12 Vertical gallium nitride transistors and method for manufacturing the same
CN201410049097.5A CN103985742A (en) 2013-02-12 2014-02-12 Vertical gallium nitride transistors and methods of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130014873A KR20140101563A (en) 2013-02-12 2013-02-12 Group iii-v based transistor and method of fabricating the same

Publications (1)

Publication Number Publication Date
KR20140101563A true KR20140101563A (en) 2014-08-20

Family

ID=51746873

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130014873A KR20140101563A (en) 2013-02-12 2013-02-12 Group iii-v based transistor and method of fabricating the same

Country Status (1)

Country Link
KR (1) KR20140101563A (en)

Similar Documents

Publication Publication Date Title
US10325997B2 (en) Vertical III-nitride semiconductor device with a vertically formed two dimensional electron gas
US9184305B2 (en) Method and system for a GAN vertical JFET utilizing a regrown gate
JP2014154887A (en) Vertical gallium nitride transistors and method for manufacturing the same
US20130240951A1 (en) Gallium nitride superjunction devices
KR101922120B1 (en) High electron mobility transistor and method of manufacturing the same
US9589951B2 (en) High-electron-mobility transistor with protective diode
JP5190923B2 (en) Nitride semiconductor transistor having GaN as channel layer and manufacturing method thereof
US9252255B2 (en) High electron mobility transistor and method of manufacturing the same
US9502544B2 (en) Method and system for planar regrowth in GaN electronic devices
WO2013020051A1 (en) Method and system for a gan vertical jfet utilizing a regrown channel
WO2013085748A1 (en) VERTICAL GaN JFET WITH GATE AND SOURCE ELECTRODES ON REGROWN GATE
WO2014107305A1 (en) Method and system for a gallium nitride vertical transistor
WO2014107304A1 (en) Gallium nitride vertical jfet with hexagonal cell structure
TWI569439B (en) Semiconductor cell
CN114402442B (en) Nitride-based semiconductor device and method for manufacturing the same
JP2013172108A (en) Semiconductor device and manufacturing method thereof
US9391179B2 (en) Vertical GaN JFET with low gate-drain capacitance and high gate-source capacitance
TWI732813B (en) Semiconductor device, electronic part, electronic apparatus, and method for fabricating semiconductor device
CN114270532B (en) Semiconductor device and method for manufacturing the same
US20150325689A1 (en) Iii-v transistor and method for manufacturing same
KR20140101563A (en) Group iii-v based transistor and method of fabricating the same
KR20140033258A (en) Gallium nitride based transistor
KR20140147435A (en) Nitnide based field effect transistor and method of fabricating the same
KR20140055408A (en) Normally-off nitride-based transistor using the depletion area and method of fabricating the same
KR20140117840A (en) Nitride semiconductor device having mixed junction drain and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application