KR20140147435A - Nitnide based field effect transistor and method of fabricating the same - Google Patents

Abstract

A field effect transistor according to the present invention includes a first semiconductor layer doped in an n-type as a first polarity and having a drain electrode; a second semiconductor layer formed of non-doped semiconductor on the first semiconductor layer; a third semiconductor layer doped in a p-type as a second polarity and having a source electrode on the second semiconductor; an insulating layer formed on the third semiconductor layer; a gate electrode formed on the insulating layer; and a blocking layer formed in low areas of the gate electrode on the insulating layer and the source electrode to block a vertical current path between the source electrode and the drain electrode. When a gallium nitride field effect transistor is embodied according to the present invention described above, the transistor may have high-voltage resistance, high current density and a normally off property.

Description

[0001] NITRIDE BASED FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride-based transistor device having high-voltage and high-current density, and more particularly to a nitride-based field effect transistor having a normally off characteristic based on an epitaxial lateral overgrowth (ELO) field-effect transistor (HFET) device.

A power device using a silicon semiconductor is used for a power amplifier circuit, a power supply circuit, and a motor drive circuit. However, due to the limitations of silicon semiconductors, the demand for high-voltage, low-resistance, and high-speed silicon devices has reached their limits and it has become difficult to meet market demands. Therefore, the development of a III-V device having features such as high breakdown voltage, high temperature operation, high current density, high speed switching and low on-resistance is under development.

However, the proposed III-V device has a horizontal structure in which the source, gate, and drain are arranged along the surface of the substrate, so that it is not suitable for a power device requiring a large current. Furthermore, there is a problem that it is not easy to realize a normally-off operation required for a power device. Further, there is a problem in that a so-called current collapse phenomenon occurs in which electrons are trapped between the semiconductor and the protective film in a high-voltage operation and the drain current is reduced. Furthermore, a III-V device of a horizontal structure, especially a GaN device, is used for high-speed response of 600 V or less due to insufficient pressure resistance.

CAVET (Current Aperture Vertical Electron Transistor) is a vertical type field effect transistor grown on a GaN substrate. The field effect transistor uses 2DEG and CBL (Current Blocking Layer) So that the performance can be improved. However, since CAVET is a normally-on device, there is a practical limitation.

On the other hand, when a GaN substrate is used for manufacturing a gallium nitride transistor, there is a disadvantage due to a high price. When a sapphire substrate is used, a breakdown voltage (BV) is generated due to a large amount of occurrence of threading dislocation (TD) Is low.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a vertical type nitride-based field-effect transistor having high breakdown voltage, high current density, and normally off characteristics.

Alternatively, the present invention aims to provide a nitride-based field-effect transistor having a normally-off characteristic which can be manufactured at low cost.

A field effect transistor according to an aspect of the present invention includes a first semiconductor layer doped with an n-type as a first polarity, a second semiconductor layer formed of an undoped semiconductor formed on the first semiconductor layer, A source electrode formed on the second semiconductor layer, a third semiconductor layer doped with p-type conductivity as a second polarity, an insulating layer formed on the third semiconductor layer, A gate electrode formed on the insulating layer, and a blocking layer formed on the lower region of the source electrode to block a vertical path between the source electrode and the drain electrode.

The first semiconductor layer is formed on the sapphire substrate.

And an additional blocking layer formed on the drain electrode in parallel with the blocking layer.

The first semiconductor layer is characterized by disposing a seed layer for growing a semiconductor layer in a region below the blocking layer.

The first semiconductor layer may include a highly doped gallium nitride based semiconductor layer doped at a high concentration on the drain electrode and a low doped low doped gallium nitride based semiconductor layer formed on the highly doped gallium nitride based semiconductor layer .

And the second semiconductor layer has a thickness of 0.2um or more and 1.0um or less.

And a depletion region formed by the contact of the third semiconductor layer and the second semiconductor layer in a state where no voltage is applied to the gate electrode is formed up to the blocking layer.

When a working voltage is applied to the gate electrode, a depletion region formed by the contact of the third semiconductor layer and the second semiconductor layer is formed only under the third semiconductor layer, and a channel is formed between the source electrode and the drain electrode Is formed.

A drain electrode formed through the first semiconductor layer and a second semiconductor layer formed of the second nitride semiconductor and having a first energy band gap and formed of a first nitride semiconductor; And a channel layer formed through the part of the first semiconductor layer and having a fourth energy band gap different from the first energy band gap and formed of a fourth nitride semiconductor.

The third semiconductor layer having the source electrode and the third energy band gap and being formed of the third nitride semiconductor, the second semiconductor layer having the second energy band gap and being formed of the second nitride semiconductor, And a barrier layer formed of a fifth nitride semiconductor and having a fifth energy band gap different from the second energy band gap.

When a working voltage is applied to the gate electrode, a 2DEG layer is formed between the source electrode, the third semiconductor layer, and the second semiconductor layer.

According to another aspect of the present invention, there is provided a method of manufacturing a field effect transistor, comprising: a first step of forming a seed layer of a first polarity on a first substrate; growing a seed layer of the first polarity; A third step of forming a blocking layer on the first semiconductor layer doped with n-type so as to cover the seed layer, a third step of doping the first semiconductor layer without the blocking layer Forming a third semiconductor layer made of a p-type GaN layer doped with p-type as a second polarity on the barrier layer and the second semiconductor layer; A fifth step of forming an insulating layer on the third semiconductor layer, a seventh step of forming a source electrode in the upper part of the blocking layer, a gate electrode between the source electrodes, , The first step A ninth step of separating and is characterized in that it comprises a tenth step of forming a drain electrode on a surface of the first substrate is removed.

The forming of the first semiconductor layer may include forming a highly doped gallium nitride based semiconductor layer doped at a high concentration on the drain electrode and forming a lightly doped low- And a step of forming a doped gallium nitride based semiconductor layer.

In the step of forming the first semiconductor layer, a channel layer formed of INGaN is formed between the heavily doped high doped gallium nitride based semiconductor layer and the lightly doped low doped gallium nitride based semiconductor layer Further comprising the steps of:

Forming a barrier layer formed of AlGaN on the barrier layer and the second semiconductor layer between the step of forming the second semiconductor layer and the step of forming the third semiconductor layer, do.

When the gallium nitride-based field-effect transistor of the present invention according to the above-described configuration is used, it has an advantage of having high breakdown voltage, high current density, and normally off characteristics.

Alternatively, the present invention has an advantage that a vertical type gallium nitride-based field-effect transistor having a normally off-off characteristic can be manufactured at low cost.

FIG. 1 is a cross-sectional view illustrating a gate off state of a gate of a nitride-based field-effect transistor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a state in which an operating voltage is applied to a gate of a nitride-based field-effect transistor (Gate on) according to an embodiment of the present invention.
FIGS. 3 to 18 illustrate a manufacturing process of a nitride-based field-effect transistor according to an embodiment of the present invention.
FIG. 19 is a diagram illustrating a gate off state of a gate of a nitride-based field-effect transistor according to a second embodiment of the present invention.
20 is a diagram showing a state in which an operating voltage is applied to the gate of a nitride-based field-effect transistor (Gate on) according to the second embodiment of the present invention.
FIG. 21 is a diagram illustrating a state where a gate of a nitride-based field-effect transistor according to the third embodiment of the present invention is not applied with a voltage. FIG.
FIG. 22 is a view showing a state in which an operating voltage is applied to the gate of the nitride-based field-effect transistor according to the third embodiment of the present invention (Gate on). FIG.
23 to 38 are views showing a manufacturing process of the nitride-based field effect transistor of the third embodiment according to the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where there are other components in between. Like reference numerals designate like elements throughout the specification.

In the following description of the embodiments, the expression of a gallium nitride semiconductor is not limited to GaN, but may be a three-component system such as AlGaN or InGaN, or a variety of nitride-based semiconductors such as AlInGaN.

In the description of the following embodiments, the first polarity is described as an n-type, and the second polarity is described as a p-type. However, the opposite case is of course possible.

FIG. 1 is a cross-sectional view illustrating a state where a gate is not applied to a gate of a nitride-based field effect transistor according to an embodiment of the present invention (Gate off), and FIG. 2 is a cross- (Gate on) to which the operating voltage is applied.

FIG. 1 illustrates a structure of a nitride-based field-effect transistor according to an embodiment of the present invention.

1, a nitride-based field effect transistor includes a first semiconductor layer 20, 25 doped with an n-type as a first polarity, a first semiconductor layer 20, 25, A source electrode 62 formed on the second semiconductor layer 40 and a third semiconductor layer 50 doped with p-type impurities as a second polarity, The source electrode 62 and the drain electrode 10 are formed in the lower region of the insulating layer 55, the gate electrode 60 formed on the insulating layer 55 and the source electrode 62 on the third semiconductor layer 50, And a blocking layer 35 formed to block the vertical path.

The illustrated field effect transistor may further include an additional barrier layer 15 formed on the drain electrode 10 in parallel with the barrier layer 35 in a space in which a part of the drain electrode 10 is removed have. Barrier layer 35 and the additional shield layer 15 may be formed of a nitride-based insulating material containing the oxide insulating material, SiNx containing SiO _2. The insulating layer may be formed of SiO ₂ .

Although not shown in FIG. 1, the nitride-based field-effect transistor of this embodiment is directly or indirectly connected through the first semiconductor layer 20, 25 and the second semiconductor layer 40 formed of u-GaN Drain electrode.

In the figure, the first semiconductor layers 20 and 25 may be formed of a first nitride semiconductor having a first energy band gap. Doped gallium nitride-based semiconductor layer formed on the n + GaN layer 20 and the n + GaN layer 20 as a highly doped gallium nitride semiconductor layer doped at a high concentration on the drain electrode 10, Layer 25 as shown in FIG.

n + GaN layer 20 is formed of a 500㎛ 100㎛ to thickness and can form a doping concentration of 1e18 / cm ^3, n- GaN layer 25 is 0.1 20㎛ 2㎛ to the formation and doping concentration in a thickness Lt; 17 > / cm < ³ >.

The second semiconductor layer 40 may be formed of the same or the same material as the first semiconductor layers 20 and 25. A second semiconductor layer 40 is a u-GaN layer is formed include a barrier (35), forming a thickness which is formed from the barrier 35 to the 0.2㎛ to 1.0㎛, the doping concentration of 0.1 to 5e16 / cm ³ .

The third semiconductor layer 50 may be formed of a P-GaN layer and have a hole concentration of 0.1 to 1e18 / cm ³ . Zn, Mg, etc. may be used as a dopant for the P-type doping of the third semiconductor layer 50.

The first, second, and third semiconductor layers 20, 25, 40, and 50 may be formed of MOCVD, MBE, HVPE, or the like.

In the nitride-based field-effect transistor of this embodiment, the n + GaN layer 20 of the first semiconductor layer may have a seed layer 2 for growing gallium nitride in a region below the barrier layer 35.

FIG. 1 shows a state where no voltage is applied to the gate of the nitride-based field effect transistor of this embodiment (Gate off), and FIG. 2 shows a state in which an operating voltage is applied to the gate (Gate on).

A depletion region DL is formed in the gate off state of FIG. 1, which is indicated by DL_off formed from the contact surface between the third semiconductor layer 50 and the second semiconductor layer 40, Layer 35 as shown in FIG.

In this manner, all the paths from the source electrode 62 to the drain electrode 10 can be effectively blocked by the depletion region DL and the barrier layer 35. Therefore, the nitride-based field-effect transistor of this embodiment can have a normally-off characteristic.

Off property to the seed layer 2 and the upper region thereof by a strain in the process of forming the n + GaN layer 20 and / or the n-GaN layer 25, Threading Dislocation: TD) may be formed. In addition, dislocation defects (TD) may also be generated in the merge where the semiconductor layers are grown together. In addition, since the substrate is a high-priced gallium nitride substrate, the use of an inexpensive sapphire substrate inevitably causes dislocation defects due to lattice mismatch.

This may be due to defects occurring at the interface of the grain because the grain size of the seeds increases during the GaN growth at a high temperature and the crystal characteristics of each grain are different when the grains are formed. In general, the presence of these dislocation defects (TD) However, in the case of the nitride-based field-effect transistor of the present invention, the above-described depletion area (DL) at the time of gate voltage off is a current blocking layer (CBL) ) So that the current does not flow. Accordingly, a nitride-based field-effect transistor having a normally-off characteristic can be realized by forming and using a depletion layer as a pn-junction.

In other words, the lower part of the blocking layer 35 is GaN grown by Epitaxial Lateral Growth (ELO) on the substrate and is composed of n +, n-, or undoped GaN layers. The current blocking layer CBL and the blocking layer 35 formed in the depletion region DL are formed to completely cover the threading dislocation TD in the seed layer 2. That is, the portion of the high dislocation defect (TD) in which a large amount of leakage is generated is formed of the blocking layer 35 formed of the insulating material, and the current formed in the depletion region DL between the adjacent blocking layers 35 It can be covered with the barrier layer CBL to block the leakage current. In addition, the side wall growth method (ELO) in which the dislocation defect (TD) is small in the depletion region (DL) exhibits the high withstand voltage characteristic together with the grown portion.

On the other hand, in the gate on state of FIG. 2, the depletion region DL does not reach the blocking layer 35 as denoted by DL_on, and a thin region directly below the third semiconductor layer 50 formed of the p- Lt; / RTI > In this case, a current path as shown by IF is formed, and a current flows from the source electrode 62 to the drain electrode 10. [

The n + GaN layer 20, the n-GaN layer 25, the u-GaN layer 40, and the p-GaN layer 50 are formed as described above for the gate off state and the gate on state. Carrier density and thickness. Particularly, in order to form the depletion region DL as described above, it is preferable that the thickness of the second semiconductor layer 40 formed of the u-GaN layer is 0.2 mu m or more and 1.0 mu m or less.

FIGS. 3 to 18 illustrate a manufacturing process of a nitride-based field-effect transistor according to an embodiment of the present invention. Here, a description will be made with reference to Figs. 1 and 2. Fig.

A method of manufacturing a nitride-based field-effect transistor according to the present embodiment as shown in the figure comprises a first step of forming a seed layer (2) of a first polarity on a first substrate (1), a first step of growing a seed layer A second step of forming first semiconductor layers 20 and 25 doped with n-type as one polarity, a second step of forming a first semiconductor layer 20 and 25 doped with n-type so as to cover the seed layer 2, A fourth step of forming a second semiconductor layer 40 made of a non-doped semiconductor layer on the first semiconductor layers 20 and 25 without the barrier layer 35, A fifth step of forming a third semiconductor layer 50 made of a p-GaN layer doped with a p-type as a second polarity on the barrier layer 35 and the second semiconductor layer 40, A sixth step of forming an insulating layer 55 on the insulating layer 55; A seventh step of forming a source electrode 66 in a region above the blocking layer 35 and a gate electrode 60 between the source electrodes 66; An eighth step of attaching a second substrate (9) to an upper surface; A ninth step of separating the first substrate 1 and a tenth step of forming a drain electrode 10 on the surface on which the first substrate 1 is separated.

In the step of forming the seed layer 2, the first substrate 1 is not limited to any substrate that can grow a semiconductor material such as a sapphire substrate. Undoped GaN can be used as a seed for easy attachment to the first substrate 1. [ As shown in FIG. 3, a layer made of GaN is formed on the first substrate 1, and a part of the layer is removed by etching or the like to remove the undoped GaN layer from the seed layer 2, . At this time, the GaN layer may be formed to a thickness of 1 to 2 탆.

In FIG. 4, n-doped GaN is grown on the seed layer 2 as undoped GaN (u-GaN) to form an n + GaN layer 20. In order to form GaN on the first substrate 1 in FIGS. 3 and 4, a growth process may be performed by MOCVD, MBE, HVPE or the like at the c-plane position of the substrate.

As shown in FIG. 5, an n - GaN layer 25 is formed on the n + GaN layer 20. That is, the step of forming the first semiconductor layers 20 and 25 includes forming the n + GaN layer 20 on the first substrate 1 by growing the seed layer 2 and forming the n + Lt; RTI ID = 0.0 > n-GaN < / RTI > Accordingly, the first semiconductor layers 20 and 25 shown in the figures are formed as an upper layer formed on the n + GaN layer 20 and the n + GaN layer 20, which are lower layers in contact with the first substrate 1, GaN layer 25 having a lower free electron concentration.

5, after formation of the n-GaN layer 25, threading dislocations (TD) are formed in the seed region 2 and the upper region thereof by the strain in the growth process . Further, in the region where the dislocation defects occur, the degree of occurrence of dislocation defects may be increased when additional growth processes are performed.

As shown in FIG. 6, the barrier layer 35 may be formed of an insulating layer slightly wider than the seed layer 2 so as to cover the seed layer 2. The barrier layer 35 may be formed by a process such as ICP-CVD using an insulating material such as an oxide-based or a nitride-based material to form a layer over the entire surface, followed by selective etching.

7, in the step of forming the second semiconductor layer 40, the second semiconductor layer 40 is formed in a shape that partially covers the rim region of the blocking layer 35 as the u-GaN layer is grown As shown in FIG. Or may cover the entire surface of the barrier layer 35.

8, the third semiconductor layer 50 is provided only under the gate electrode 60 in the final stage of the device. However, for convenience of the manufacturing process, the barrier layer 35 and the second semiconductor layer 40 ) P-type GaN layer.

9, the insulating layer 55 is provided only under the gate electrode 55 in the final stage of the device. However, for convenience of the manufacturing process, the barrier layer 35 and the upper portion of the u-GaN layer 40 the insulating layer 55 is formed on the entire surface of the p-GaN layer 50.

10A to 15A, the step of forming the source electrode 66 and the gate electrode 60 includes the steps of forming a metal layer on the insulating layer 55, Removing the metal layer, the insulating layer, and the p GaN layer outside the gate electrode region as shown in FIGS. 13 and 14A; forming a metal layer for the source electrode 66 in the removed region as shown in FIGS. 13 and 14A; and Forming a passivation layer 75 between and above the gate metal and source metal as shown in Figure 15A. The passivation layer 75 may be formed by coating at least once with an oxide-based or a nitride-based insulating material.

The source electrode 66 and the gate electrode 60 are electrically separated from each other. For this purpose, only the region where the source electrode 66 is formed is covered with the blocking material layer A metal layer for the source electrode 66 is formed in a state of being connected to the gate electrode 60 and then a metal layer is formed between the source electrode 66 and the gate electrode 60 (Etching) of the metal layer of the first metal layer may be applied.

14B shows the structure of the drain electrode 68 that has not been shown yet as another embodiment. The drain electrode 68 shown in the figure is formed in the same manner as the case of the source electrode 66 described above, Electrical separation from the electrodes 60 and 66 can be realized. The drain electrode 68 is electrically connected to a channel to be formed later. In the drawing, the drain electrode 68 is formed on the seed layer 2, and a threading dislocation TD formed by lattice defects is formed. The electrical connection path may be provided by the electrical connection path.

15B, a part of the passivation layer 75 is removed to form external connection portions 91, 92, 93 of the source electrode 66, the gate electrode 60, and the drain electrode 68. [

After repeating the step of attaching the second substrate 9 to the upper surface as shown in Fig. 16, the step of separating the first substrate 1 as shown in Fig. 17 Can be performed. The process of separating the first substrate can be removed by a laser lift-off method. The second substrate 9 may be a conductive or insulating substrate. For example, the second substrate 9 may be formed of various materials such as Si, AlN, AlSi, or Cu.

Then, the metal layer may be formed by performing the deposition operation with the second substrate 9 downward after performing the step of separating the first substrate 1. 18, after the first substrate 1 is separated, an additional barrier layer 15 is formed on the separated surface in parallel with the barrier layer 35, and then a metal layer for the drain electrode 10 is formed. Here, the additional barrier layer 15 may be made of the same material and process as the barrier layer 35.

At least one of the drain electrode 10, 68, the gate electrode 60 and the source electrode 66 is made of at least one of Ti, Al, Ni, Au, Pt, Mo, And may be annealed after deposition if necessary.

The nitride-based field-effect transistor according to the present embodiment is characterized in that a 2DEG is formed using an InGaN layer as a channel layer between first semiconductor layers and a drain electrode arranged in the horizontal direction of the 2DEG is connected, . Therefore, in the manufacturing method, the metal layer of the drain electrode is not formed, and a lift-off process may not be included.

The nitride-based field-effect transistor of this embodiment shown in FIG. 19 has a channel layer 210 having a second energy band gap and formed of a fourth nitride semiconductor, a channel layer 210 having a first energy band gap, A first semiconductor layer 220 including a channel layer 210 and doped with n-type impurities as a first polarity, and an undoped u-GaN layer formed on the first semiconductor layers 220 and 225. A source electrode 262 formed on the second semiconductor layer 240 and a third semiconductor layer 250 formed of a p-GaN layer doped with a p-type as a second polarity, A source electrode 262 and a channel layer 210 are formed in a lower region of the gate electrode 260 and the source electrode 262 formed on the insulating layer 255, The barrier layer 235 may be formed to block the vertical path of the barrier layer 235. Here, the first energy band gap and the second energy band gap exhibit different energy band gaps.

The nitride-based field effect transistor of this embodiment may further include a drain electrode 268 connected to the channel layer 210 through the first semiconductor layers 220 and 225 at the surface. That is, in the case of this embodiment, the two-dimensional electron gas (2DEG) and the drain electrode 268 are directly connected.

When the channel layer 210 is made of gallium nitride (GaN), the spontaneous polarization caused by the Wurtzite structure of GaN and the lattice constant of the channel layer 210 and the first semiconductor layers 220 and 225 The electron mobility can be increased by forming a high-density two-dimensional electron gas (2DEG) region by using an electric field by piezoelectric polarization caused by the difference.

In other words, the channel layer 210 and the first semiconductor layers 220 and 225 are formed of semiconductors having different energy band gaps. When the first semiconductor layers 220 and 225 are formed of GaN having a large energy band gap and the channel layer 210 is formed of InGaN having a relatively small energy band gap, the 2DEG region has a channel with a small energy bandgap Layer 210. By forming such a high concentration 2DEG channel, good electron mobility can be secured in the drain electrode region.

In the figure, the channel layer 210 may be formed of InGaN. The first semiconductor layers 220 and 225 may be a heavily doped high doped gallium nitride semiconductor layer in which a GaN layer is buried. The n + GaN layer 220 and the low concentration doped low doping And an n-GaN layer 225 as a gallium nitride-based semiconductor layer. Here, the channel layer 210 may be included in the n + GaN layer 220.

19, the n + GaN layer 220 of the first semiconductor layers 220 and 225 is formed of a seed layer (not shown) for growing semiconductor layers in a region below the blocking layer 235, 202 may be provided.

The n + GaN layer 220 as the first semiconductor layers 220 and 225 of the nitride-based field-effect transistor of this embodiment is located above the substrate 201. In the case of the nitride-based field-effect transistor of another embodiment, the substrate is placed on the substrate 201 during the manufacturing process, but the substrate is removed in the lift-off process for forming the metal drain electrode. On the other hand, in the present embodiment, the drain electrode 268 is formed to be connected to the channel layer 210, so that the drain electrode 268 can be formed without a lift-off process. Therefore, the substrate 201 may be continuously attached to the nitride-based field-effect transistor of the presently completed embodiment.

FIG. 19 is a view showing a state where a gate is not applied to a gate of a nitride-based field-effect transistor according to a second embodiment of the present invention (gate off). FIG. 20 is a cross- (Gate on) in which the operating voltage is applied to the gate of the effect transistor.

The depletion region DL indicated by DL_off formed from the contact surface between the third semiconductor layer 250 which is a p-GaN layer and the second semiconductor layer 240 which is a u-GaN layer in the gate off state of Fig. . Since the entire path from the source electrode 262 to the channel layer 210 is effectively blocked by the depletion region DL and the blocking layer 235, the nitride-based field-effect transistor of this embodiment is a normally- off < / RTI >

On the other hand, in the gate on state of FIG. 20, the depletion region does not reach the blocking layer 235 as indicated by DL_on and exists only in the thin region immediately below the p GaN layer 250, The current flows to the channel layer 210. [

The n-GaN layer 220, the n-GaN layer 225, the u-GaN layer 240, and the p-GaN layer 250 are formed on the n-GaN layer 220, The carrier density and the thickness may be the same as described above. Particularly, in order to form the depletion region as described above, it is advantageous that the thickness of the u-GaN layer 240 as the second semiconductor layer is 0.2 mu m or more and 1.0 mu m or less.

The field effect transistor according to the present embodiment is characterized in that a barrier layer formed of AlGaN is further disposed near the junction surface where the depletion region starts, which is different from the other embodiments. Therefore, the manufacturing method is also similar to that of the first embodiment except that a step of disposing the barrier layer formed of the AlGaN on the bonding surface is added, and some explanations that may be duplicated in the first embodiment are omitted.

FIG. 21 illustrates a structure of a nitride-based field-effect transistor according to an embodiment of the present invention.

The illustrated field effect transistor includes a first semiconductor layer 320 and 325 having a drain base layer 310 and a first energy band gap and formed of a first nitride semiconductor layer and doped with n-type as a first polarity, A second semiconductor layer 340 formed on the first semiconductor layers 320 and 325 to form an undoped u-GaN layer, a source electrode 362 formed on the second semiconductor layer 340, A third semiconductor layer 350 formed of p-type doped p-GaN layer, an insulating layer 355 formed on the third semiconductor layer 350, a gate electrode 360 formed on the insulating layer 355, And a blocking layer 335 formed to block the vertical path of the source electrode 362 and the drain electrode 310 in the lower region of the source electrode 362.

The illustrated nitride-based field-effect transistor further includes an additional barrier layer 315 formed on the drain electrode 310 in a space in which a part of the drain electrode 310 is removed in parallel with the barrier layer 335 can do.

The illustrated nitride-based field-effect transistor includes a source electrode 366 and a p-GaN layer 350 as a third semiconductor layer and an AlGaN layer interposed between the u-GaN layer 340 as the second semiconductor layer And a barrier layer 345 formed thereon.

The nitride-based field-effect transistor of this embodiment has a structure in which the first semiconductor layer 320 and the second semiconductor layer 325 are directly or indirectly connected to each other through the u-GaN layer 340 on the surface Drain electrode 310, as shown in FIG.

In other words, the barrier layer 345 and the first semiconductor layers 220 and 225 are formed of semiconductors having different energy band gaps. The second semiconductor layer 340 may be formed of GaN having a small energy band gap and the barrier layer 345 may be formed of AlGaN having a relatively large energy band gap. In this case, a two-dimensional electron gas (2DEG) region is formed near the interface of the second semiconductor layer 340 having a small energy band gap. Furthermore, since the superlattice structure such as the barrier layer 345 is interposed between the source electrode 362 and the drain electrode 310, the breakdown voltage characteristics can be further enhanced.

In the figure, the first semiconductor layers 320 and 325 are highly doped high doped gallium nitride semiconductor layers, and are formed of an n + GaN layer 320 and a lightly doped low doped gallium nitride semiconductor layer 320 formed on the n + GaN layer 325 as a semiconductor layer.

In the nitride-based field effect transistor of this embodiment, the n + GaN layer 320 of the first semiconductor layer may include a seed layer 302 for growing a semiconductor layer in a region below the blocking layer 335.

FIG. 21 is a view showing a state in which no gate is applied to the gate of the nitride-based field effect transistor according to the third embodiment of the present invention (Gate off), and FIG. 22 is a cross- (Gate on) in which the operating voltage is applied to the gate of the effect transistor.

The depletion region indicated by DL_off formed from the contact surface between the p-GaN layer 350 as the third semiconductor layer and the u-GaN layer 340 as the second semiconductor layer in the gate off state in Fig. And the field effect transistor of this embodiment has a characteristic of being normally-off.

On the other hand, in the gate on state of FIG. 22, the depletion region does not reach the blocking layer 335 as indicated by DL_on, and exists only in the thin region immediately below the p GaN layer 350. In addition, when a working voltage is applied to the gate electrode, a 2DEG layer is formed on the surface layer of the u GaN layer 340 which is the second semiconductor layer just below the p-GaN layer 350 as the source electrode and the third semiconductor layer. The 2DEG layer is created by the presence of the barrier layer 345 and may serve to facilitate current flow from the source electrode 362 to the drain electrode 310. [ That is, the additional structure of the barrier layer 345 is the spontaneous polarization caused by the Wurtzite structure of GaN and the lattice constant difference between the uGaN layer 240 and the AlGaN layer 345 It is possible to increase electron mobility by forming a 2DEG channel of high concentration by using an electric field by piezoelectric polarization induced.

For formation of the 2DEG layer, the barrier layer 345 may have a thickness of 10 nm to 100 nm. For example, when the barrier layer 345 is an Al _{0 .26} Ga _{0 .74} N, may have a thickness of 20nm.

The n + GaN layer 320, the n-GaN layer 325, the u-GaN layer 340, and the p-GaN layer 350 are formed on the n-GaN layer 320, And may have the same carrier density and thickness. In particular, in order to form the depletion region as described above, it is advantageous that the thickness of the u-GaN layer 340 as the second semiconductor layer is 0.2 mu m or more and 1.0 mu m or less.

23 to 38 are views showing a manufacturing process of the nitride-based field effect transistor of the third embodiment according to the present invention. The method of manufacturing a nitride-based field-effect transistor according to the illustrated embodiment includes the steps of forming a seed layer 302 of a first polarity on a substrate 301, growing a seed layer 302 to form n Forming a barrier layer 35 on the n-type doped first semiconductor layers 20 and 25 so as to cover the seed layer 302; forming a first semiconductor layer 320 and 325 doped with n- Forming a u-GaN layer 40 as a second undoped semiconductor layer on the first semiconductor layers 320 and 325 without the blocking layer 335, Forming a barrier layer 345 on the layer 340, forming a third semiconductor layer 350 doped p-type as a second polarity on the barrier layer 345; Forming an insulating layer (55) on the third semiconductor layer (350); Forming a source electrode (66) above the blocking layer (35) and a gate electrode (60) between the source electrode (66); Attaching a second substrate (9) on an upper surface; Separating the sapphire substrate (1); And forming a drain base layer (10) on the separated surface of the sapphire substrate (1).

In the step of forming the seed layer, undoped GaN can be used as the seed layer to facilitate adhesion to the substrate 301. 23, a u-GaN layer 302 is formed on the sapphire substrate 301 and then a part thereof is removed by etching or the like to remove the u-GaN layer that has not been removed as shown in Fig. 24 from the seed region 302 ). In FIG. 24, n-type doped GaN is grown on the seed region 302 as undoped GaN (u-GaN) to form the n + GaN layer 320.

In FIG. 25, an n - GaN layer 325 is formed on the n + GaN layer 320. That is, the step of forming the first semiconductor layers 320 and 325 may include forming an n + GaN layer 320 on the substrate 301 by growing a seed layer 302, Lt; RTI ID = 0.0 > n-GaN < / RTI > Accordingly, the first semiconductor layers 320 and 325 shown in the figures have the n + GaN layer 320 having a higher free electron concentration as a lower layer in contact with the substrate, and a free electron concentration Lt; RTI ID = 0.0 > n-GaN < / RTI >

As shown in FIG. 26, the barrier layer 335 may be formed of an insulating layer slightly wider than the seed layer 302 so as to cover the seed layer 302. The barrier layer 335 may be formed by forming a layer of an insulating material such as SiO ₂ , and then selectively etching the barrier layer 335.

The step of forming the u-GaN layer 340 may be performed so as to form a shape that partially covers the rim region of the insulating layer 335 as the u-GaN layer 340 grows, as shown in Fig. 27 have.

28, the AlGaN layer 345 formed in the step of forming the barrier layer 345 has a larger thickness than that of the u-GaN layer 40 and the p-GaN layer 50 formed above and below the AlGaN layer 345 10 to 100 nm) may have a thin film form.

The insulating layer 355 is provided only under the gate electrode in the final stage of the device. However, as shown in FIG. 29, for convenience of the manufacturing process, the blocking layer 335 and the p-GaN layer An insulating layer 355 is formed on the entire surface of the substrate 350.

The step of forming the source electrode and the gate electrode may include a step of forming a metal layer 360 on the insulating layer 355 as shown in FIG. 30, A step of removing the metal layer 360, the insulating layer 355, and a portion of the p-GaN layer 350; a step of forming a metal layer for the source electrode 366 in the removed region as shown in FIGS. 33 and 34; And forming an insulating layer 375 between and above the gate metal layer and the source metal layer 366 as shown in FIG.

After the step of attaching the second substrate 309 to the upper surface as shown in Fig. 36, a step of separating the substrate 301 as shown in Fig. 37 can be performed.

The metal layer for the drain electrode 310 may be formed by performing the deposition operation with the second substrate 309 downward after performing the step of separating the substrate 301. [ 38, after the substrate 301 is separated, an additional barrier layer 315 is formed on the separated surface in parallel with the barrier layer 335, and then a metal layer for the drain electrode 310 is formed. Here, the additional barrier layer 315 may follow the same materials and processes as the barrier layer 335.

It should be noted that the above-described embodiments are intended to be illustrative, not limiting. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1, 201, 301: substrate
2, 202, 302: seed layer
10, 210 and 310: drain electrode
20, 220, 320: an n + GaN layer
25, 225, 325: n- GaN layer
35, 235, 335: barrier layer
40, 240, 340: a second semiconductor layer
50, 250, 350: a third semiconductor layer
55, 255, 355: insulating layer
60, 260, 360: gate electrode
62, 262, 362: source electrode
68, 268, 368: drain electrode
245: channel layer
345: barrier layer

Claims (15)

A first semiconductor layer doped with n-type conductivity as a first polarity;
A second semiconductor layer formed on the first semiconductor layer and formed of undoped semiconductor;
A source electrode formed on the second semiconductor layer and a third semiconductor layer doped with p-type as a second polarity;
An insulating layer formed on the third semiconductor layer;
A gate electrode formed on the insulating layer; And
A blocking layer formed on a lower region of the source electrode to block a vertical path of the source electrode and the drain electrode;
Wherein the nitride-based field-effect transistor comprises:
The method according to claim 1,
Wherein the first semiconductor layer is formed on a sapphire substrate.
The method according to claim 1,
And an additional blocking layer formed on the drain electrode in parallel with the blocking layer.
Wherein the nitride-based field-effect transistor further comprises:
The method according to claim 1,
Wherein the first semiconductor layer includes a seed layer for growing a semiconductor layer in a region below the blocking layer.
The method according to claim 1,
Wherein the first semiconductor layer comprises a first semiconductor layer,
A highly doped gallium nitride based semiconductor layer doped at a high concentration on the drain electrode; And
A lightly doped low doped gallium nitride based semiconductor layer formed on the highly doped gallium nitride based semiconductor layer;
Wherein the nitride-based field-effect transistor comprises:
The method according to claim 1,
Wherein the second semiconductor layer has a thickness of 0.2 um or more and 1.0 um or less.
The method according to claim 1,
A depletion region formed by the contact of the third semiconductor layer and the second semiconductor layer in a state in which no voltage is applied to the gate electrode,
Wherein the barrier layer is formed up to the barrier layer.
The method according to claim 1,
When an operating voltage is applied to the gate electrode,
And a depletion region formed by the contact of the third semiconductor layer and the second semiconductor layer,
And a channel is formed only between the source electrode and the drain electrode in the lower portion of the third semiconductor layer.
The method according to claim 1,
The drain electrode formed through a first semiconductor layer having a first energy bandgap and formed of a first nitride semiconductor and a second semiconductor layer formed of a second nitride semiconductor;
A channel layer formed of a fourth nitride semiconductor and having a fourth energy bandgap different from the first energy band gap, the channel layer being formed to penetrate a part of the first semiconductor layer, the channel layer being electrically connected to the drain electrode,
Wherein the nitride-based field-effect transistor further comprises:
The method according to claim 1,
The third semiconductor layer having the third energy band gap and the third energy band gap, the third semiconductor layer having the third energy band gap and the second semiconductor layer having the second energy band gap and being formed of the second nitride semiconductor, A barrier layer having a fifth energy band gap different from the second energy band gap and being formed of a fifth nitride semiconductor;
Wherein the nitride-based field-effect transistor further comprises:
11. The method of claim 10,
When an operating voltage is applied to the gate electrode,
And a 2DEG layer is formed between the source electrode, the third semiconductor layer, and the second semiconductor layer.
A first step of forming a seed layer of a first polarity on the first substrate;
A second step of growing the seed layer to form an n-type doped first semiconductor layer as a first polarity;
A third step of forming a blocking layer on the first semiconductor layer doped with n-type so as to cover the seed layer;
A fourth step of forming a second semiconductor layer made of an undoped semiconductor layer on the first semiconductor layer without the blocking layer;
A fifth step of forming the third semiconductor layer including the blocking layer and the p-GaN layer doped with p-type as a second polarity on the second semiconductor layer;
A sixth step of forming an insulating layer on the third semiconductor layer;
A seventh step of forming a source electrode in the upper region of the blocking layer and a gate electrode in the region between the source electrodes;
An eighth step of attaching a second substrate to an upper surface;
A ninth step of separating the first substrate; And
Forming a drain electrode on a surface where the first substrate is separated;
Type field effect transistor.
13. The method of claim 12,
Wherein forming the first semiconductor layer comprises:
Forming a highly doped gallium nitride based semiconductor layer doped at a high concentration on the drain electrode; And
Forming a lightly doped low doped gallium nitride based semiconductor layer formed on the heavily doped gallium nitride based semiconductor layer;
Type field effect transistor.
14. The method of claim 13,
In the step of forming the first semiconductor layer,
Doped high-doped gallium nitride based semiconductor layer and a lightly doped low doped gallium nitride based semiconductor layer,
Forming a channel layer formed of INGaN;
Further comprising the steps of:
13. The method of claim 12,
Forming the second semiconductor layer, and forming the third semiconductor layer,
And forming a barrier layer formed of AlGaN on the barrier layer and the second semiconductor layer.

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