KR20140086931A - Semiconductor bonding assembly - Google Patents

Abstract

The present invention relates to a semiconductor bonding assembly and a method of bonding a semiconductor. A semiconductor bonding assembly according to the present invention includes a semiconductor chip having a first groove formed on the lower surface thereof; a die having a second groove formed on the top surface thereof to correspond to the semiconductor chip, wherein the semiconductor chip is mounted on the die; and an adhesive installed between the semiconductor chip and the die. According to the present invention, adhesive strength is enhanced by reducing air bubbles, and adhesive hardening time is reduced so that productivity is improved. In addition, the adhesive strength, bonding durability and bonding uniformity are improved so that the performance of a product may be improved. Further, the bonding position of the semiconductor chip and the die may be aligned.

Description

Semiconductor bonding assembly < RTI ID = 0.0 >

The present invention relates to a semiconductor bonding assembly, and more particularly, to a semiconductor bonding assembly, and more particularly, to a semiconductor bonding assembly for forming an air passage between a semiconductor chip and a die during bonding to reduce air bubbles, shorten adhesive curing time, Thereby improving the uniformity of the semiconductor chip.

In general, a semiconductor chip is mounted on a die such as a lead frame or a substrate in a packaging process. After a liquid adhesive such as epoxy is applied between the semiconductor chip and the die, the semiconductor chip is contacted with the die, They can be solidly bonded to each other by curing.

Here, when the semiconductor chip is brought into contact with the die while the adhesive is in a liquid state, even if the adhesive is hardly applied evenly to the bonding surface of the semiconductor chip or the die and evenly applied, The probability of instantaneous simultaneous contact of the adhesive surfaces is very low, so air void phenomenon may occur which is caused by the failure of the adhesive to fill the adhesive surface.

Such bubbles deteriorate the adhesive force and cause thermal resistance and thermal stress even after the adhesive is cured, thereby causing deformation and breakage of the semiconductor chip or the die.

The idea of the present invention is to form an air passage using the first groove and the second groove to reduce the generation of air bubbles to thereby improve the adhesive strength and shorten the curing time of the adhesive to improve the productivity, To improve the uniformity of the bonding, to improve the performance of the product, and to align the bonding positions of the semiconductor chip and the die.

According to an aspect of the present invention, there is provided a semiconductor bonding assembly comprising: a semiconductor chip having a first groove formed on a lower surface thereof; A die on which the semiconductor chip is mounted and on which a second groove is formed so as to correspond to the semiconductor chip; And an adhesive provided between the semiconductor chip and the die, wherein the first grooves are a plurality of long grooves formed in parallel in the first axis direction, and the second grooves are formed in the first axis direction at 90 degrees And a plurality of row grooves formed in parallel in the second axis direction intersecting at an angle.

According to an aspect of the present invention, the semiconductor chip may be a cell for concentrating photovoltaics (CPV).

According to an aspect of the present invention, there is provided a semiconductor device, wherein the first grooves are a plurality of long grooves formed in parallel in the first axis direction, and the second grooves are corresponding to the rim of the semiconductor chip so that the semiconductor chips are partially inserted A chip receiving groove formed so as to be in contact with the chip; And a groove provided vertically below the first groove to face the first groove in the same direction as the first groove.

According to an aspect of the present invention, the adhesive may be provided in the first groove and the second groove, and an air layer may be formed in the first groove and the second groove.

According to an aspect of the present invention, the first grooves may be provided at a first interval at a rim portion of the semiconductor chip, and at a second interval at a central portion of the semiconductor chip.

According to an embodiment of the present invention, the first grooves may be formed as a plurality of long grooves arranged in parallel in the first axis direction, and the second grooves may include a plurality of grooves extending in the same direction as the first grooves, And a groove formed between the first grooves.

According to an aspect of the present invention, the first groove and the second groove may have a shape selected from at least one of a rectangular groove, a triangular groove, a round groove, and a combination thereof.

According to an aspect of the present invention, the first groove and the second groove may be lattice grooves formed in the first axis direction and the second axis direction.

The semiconductor bonding assembly according to the present invention improves the product performance by improving the adhesion by reducing the generation of bubbles, improving the productivity by shortening the curing time of the adhesive, improving the bonding strength, bonding durability and bonding uniformity So that the bonding position of the semiconductor chip and the die can be aligned.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a part exploded perspective view of a semiconductor bonding assembly according to some embodiments of the present invention.
Fig. 2 is an assembled sectional view of Fig. 1. Fig.
Fig. 3 is an enlarged view showing a portion A in Fig. 2 on an enlarged scale.
4 is a cross-sectional view illustrating a semiconductor bonding assembly in accordance with some embodiments of the present invention.
5 is a cross-sectional view illustrating a semiconductor bonding assembly in accordance with some embodiments of the inventive concept.
Figure 6 is an enlarged view of a semiconductor bonding assembly in accordance with some embodiments of the present invention.
Figure 7 is an enlarged view of a semiconductor bonding assembly in accordance with some embodiments of the present invention.
8 is a part exploded perspective view of a semiconductor bonding assembly according to some embodiments of the present invention.
Figure 9 is an exploded perspective view of a part of a semiconductor bonding assembly according to some embodiments of the present invention.
10 is a flow chart illustrating a method of assembling semiconductor bonding according to some embodiments of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness and size of each layer are exaggerated for convenience and clarity of explanation.

It will be understood that throughout the specification, when referring to an element such as a film, an area or a substrate being "on", "connected", "laminated" or "coupled to" another element, It will be appreciated that elements may be directly "on", "connected", "laminated" or "coupled" to another element, or there may be other elements intervening therebetween. On the other hand, when one element is referred to as being "directly on", "directly connected", or "directly coupled" to another element, it is interpreted that there are no other components intervening therebetween do. Like numbers refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and / or portions, these members, components, regions, layers and / It is obvious that no. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section described below may refer to a second member, component, region, layer or section without departing from the teachings of the present invention.

Also, relative terms such as "top" or "above" and "under" or "below" can be used herein to describe the relationship of certain elements to other elements as illustrated in the Figures. Relative terms are intended to include different orientations of the device in addition to those depicted in the Figures. For example, in the figures the elements are turned over so that the elements depicted as being on the top surface of the other elements are oriented on the bottom surface of the other elements. Thus, the example "top" may include both "under" and "top" directions depending on the particular orientation of the figure. If the elements are oriented in different directions (rotated 90 degrees with respect to the other direction), the relative descriptions used herein can be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing ideal embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention should not be construed as limited to the particular shapes of the regions shown herein, but should include, for example, changes in shape resulting from manufacturing.

Fig. 1 is an exploded perspective view showing a semiconductor bonding assembly 100 according to some embodiments of the present invention. Fig. 2 is an assembled sectional view of Fig. 1, and Fig. 3 is an enlarged view to be.

1 to 3, a semiconductor bonding assembly 100 according to some embodiments of the present invention includes a semiconductor chip 10, a die 20, and an adhesive 30 .

1 to 3, the semiconductor chip 10 has a first groove 10a formed on a lower surface thereof, and is a cell for a light-converging photovoltaic cell (CPV) .

Such a solar cell is a core element of solar power generation that converts solar energy directly into electricity, and can be applied to various fields ranging from electric power, electronic products, electricity supply to houses and buildings, and industrial power generation.

Such a solar cell can be formed in the form of a unit cell, and may be in the form of a diode composed of a pn junction, a silicon solar cell using silicon as a light absorption layer depending on the material of the light absorption layer, a CIS (CuInSe2 ), Compound solar cells using CdTe, dye-sensitized solar cells adsorbing light-sensitive dye molecules excited by electrons absorbed by visible light on the surface of nanoparticles of porous film, and laminated solar cells having a plurality of amorphous silicon layers can be applied. In addition, such a solar battery cell can be applied to a bulk (including a single crystal or polycrystal) and a thin film (amorphous, polycrystalline) solar cell.

The die 20 has a second groove 20a formed on an upper surface of the semiconductor chip 10 so as to correspond to the semiconductor chip 10 and supports the semiconductor chip 10 sufficiently Such as a lead frame, a printed circuit board, a silicon substrate, a ceramic substrate, or a metal substrate, having various physical and mechanical strengths.

The adhesive 30 is provided between the semiconductor chip 10 and the die 20 and may be a liquid state, a solid state, or a gel or gel state adhesive formed of a resin material such as epoxy .

For example, the adhesive 30 includes a repeating unit having an aromatic structure in the main chain. The adhesive 30 includes a naphthalene type epoxy resin, a biphenyl type epoxy resin, a dicyclopentadiene type epoxy resin, a dicyclopentadiene modified phenol type epoxy A mixture of one or more kinds of resins, a cresol epoxy resin, a bisphenol epoxy resin, a xylyl epoxy resin, a polyfunctional epoxy resin, a phenol novolak epoxy resin, a triphenol methane type epoxy resin and an alkyl modified triphenol methane type epoxy resin Can be used.

Meanwhile, as shown in FIGS. 1 to 3, the first grooves 10a may include a plurality of grooves formed in parallel in the first axis direction.

The second groove 20a includes a chip receiving groove 20a-1 formed to correspond to a rim of the semiconductor chip 10 so that the semiconductor chip 10 is partially inserted, (20a-2) provided below the first groove (10a) so as to face the first groove (10a) in the same direction as the first groove (10a).

Since the chip receiving groove 20a-1 can guide the semiconductor chip 10 to a proper position, the bonding position between the semiconductor chip 10 and the die 20 is firmly aligned, It is possible to prevent the semiconductor chip 10 from being separated from the semiconductor chip 10 and to prevent breakage or damage of the component due to an external impact.

2, the chip receiving groove 20a-1 has a depth H such that the semiconductor chip 10 is partially inserted, and the first groove 10a and the second groove The width W of the second groove 20a may be smaller than the distance S between the first groove 10a and the neighboring first groove 10a.

3, the adhesive 30 is installed in the first groove 10a and the second groove 20a, and an air layer (not shown) is formed inside the first groove 10a, 40 may be formed.

Therefore, the adhesive 30 can be applied to the interface between the first groove 10a and the second groove 20a to firmly adhere to the adhesive 30 during curing of the adhesive 30, By acting as an air discharge passage, it is possible to reduce the occurrence of bubbles and thus to improve the adhesive strength, to shorten the curing time of the adhesive, to improve the productivity, and to improve the performance of the product by improving the bonding strength, durability of bonding and uniformity of bonding .

4 is a cross-sectional view illustrating a semiconductor bonding assembly 200 in accordance with some embodiments of the inventive concept.

4, the first groove 10a is provided at a first interval L1 at the edge of the semiconductor chip 10, and at the second interval G2 at the center of the semiconductor chip 10, L2, so that a weak point can reinforce the bonding strength of the edge portion of the semiconductor chip 10.

5 is a cross-sectional view illustrating a semiconductor bonding assembly 300 in accordance with some embodiments of the inventive concept.

5, the first grooves 10a are a plurality of long grooves arranged in parallel in the first axis direction, and the second grooves 20a are formed in the same direction as the first grooves 10a And a groove 20a-3 provided between the first groove 10a and the first groove 10a adjacent to the first groove 10a so that the position of the first groove 10a and the position of the second groove 20a The adhesive force of the adhesive 30 can be evenly dispersed.

FIG. 6 is an enlarged view of a semiconductor bonding assembly in accordance with some embodiments of the inventive concept, and FIG. 7 is an enlarged view of a semiconductor bonding assembly in accordance with some embodiments of the present invention.

3, the first grooves 10a and the second grooves 20a may have a rectangular cross-section. As shown in FIG. 6, the first grooves 10b and the second grooves 20b may have a rectangular cross- The second groove 20b may be a triangular groove, and as shown in FIG. 7, the first groove 10c and the second groove 20c may be round grooves. 6, when the adhesive 30 is in the form of a liquid, it can be more uniformly applied while being moved in the direction of the arrow in the direction of the arrow, and when the adhesive 30 is a round groove, as shown in FIG. 6, When the adhesive 30 is in a liquid phase, it can be more uniformly applied while being moved in the direction of the double-headed arrow.

FIG. 8 is a part exploded perspective view of a semiconductor bonding assembly 400 in accordance with some embodiments of the present invention.

As shown in FIG. 8, the first grooves 10d are a plurality of grooves formed in parallel in the first axis direction, and the second grooves 20d are formed long in parallel in the second axis direction Can be a string groove. Here, the first axis direction and the second axis direction may intersect at an angle of 90 degrees with respect to each other.

Therefore, when the adhesive 30 is liquid, it can be more firmly adhered while moving more uniformly in the first axis direction and the second axis direction.

9 is an exploded perspective view of a part of a semiconductor bonding assembly 500 according to some embodiments of the present invention.

As shown in FIG. 9, the first groove 10e and the second groove 20e may be lattice grooves formed in the first axis direction and the second axis direction.

Therefore, when the adhesive 30 is liquid, it can be more firmly adhered while moving more uniformly between the lattice grooves.

10 is a flow chart illustrating a method of assembling semiconductor bonding according to some embodiments of the present invention.

As shown in FIG. 10, a method of assembling the semiconductor bonding assembly 100 according to some embodiments of the present invention will now be described. Referring to FIG. 10, a step S1 of manufacturing a semiconductor chip 10 using a semiconductor process (S2) of machining the first groove (10a) on the rear surface of the semiconductor chip (10).

Also, step (S3) of fabricating the die 20 may be performed and step (S4) of machining the second groove 20a on the upper surface of the die 20 may be performed.

Subsequently, a step (S5) of applying an adhesive (30) between the semiconductor chip (10) and the die (20) is performed and a step (S6) of bonding the semiconductor chip (10) to the die The semiconductor bonding assembly 100 of the present invention can be manufactured.

Here, the first groove 10a and the second groove 20a may be formed by using a blade cutting process, a photolithography process, or a laser cutting process.

It is needless to say that the present invention is not limited to the above-described embodiment, and can be modified by those skilled in the art without departing from the spirit of the present invention.

Accordingly, the scope of claim of the present invention is not limited within the scope of the detailed description, but will be defined by the following claims and technical ideas thereof.

10: semiconductor chips 10a, 10b, 10c, 10d, 10e:
20: die 20a-1: chip receiving groove
20a-2: a hook groove 20a-3: a hook groove
20a, 20b, 20c, 20d, 20e:
30: Adhesive
100, 200, 300, 400, 500: semiconductor bonding assembly
H: Depth W: Width
S: distance 40: air layer
L1: first spacing L2: second spacing

Claims (4)

A semiconductor chip on which a first groove is formed;
A die on which the semiconductor chip is mounted and on which a second groove is formed so as to correspond to the semiconductor chip; And
And an adhesive provided between the semiconductor chip and the die,
Wherein the first grooves have a plurality of grooves formed in parallel in the first axis direction and the second grooves are elongated in parallel in the second axis direction intersecting at an angle of 90 degrees with respect to the first axis direction And a barb formed thereon. The method according to claim 1,
Wherein the semiconductor chip is a cell for concentrating photovoltaics (CPV). The method according to claim 1,
Wherein the first grooves are provided at a first interval at an edge of the semiconductor chip and at a second interval at a center of the semiconductor chip. 4. The method according to any one of claims 1 to 3,
Wherein the first groove and the second groove are lattice grooves formed in a first axis direction and a second axis direction.

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