KR20140081542A - Mask layer pattern in semiconductor device, method of fabricating the same, and method of manufacturing the semiconductor device using the resist layer pattern - Google Patents

Mask layer pattern in semiconductor device, method of fabricating the same, and method of manufacturing the semiconductor device using the resist layer pattern Download PDF

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KR20140081542A
KR20140081542A KR1020120151419A KR20120151419A KR20140081542A KR 20140081542 A KR20140081542 A KR 20140081542A KR 1020120151419 A KR1020120151419 A KR 1020120151419A KR 20120151419 A KR20120151419 A KR 20120151419A KR 20140081542 A KR20140081542 A KR 20140081542A
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layer pattern
layer
height
axis direction
pattern
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Korean (ko)
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구미나
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에스케이하이닉스 주식회사
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Publication of KR20140081542A publication Critical patent/KR20140081542A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02678—Beam shaping, e.g. using a mask
    • H01L21/0268—Shape of mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

A mask layer pattern of a semiconductor device according to the present invention includes a resist layer pattern which is arranged on a lower layer and has a minor axis and a major axis, and a polymer layer which is arranged in the upper part of the resist layer pattern and corrects the deviation of an edge height in the minor axis from an edge height in the major axis.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a mask layer pattern of a semiconductor device, a method of forming the same, and a method of manufacturing a semiconductor device using the same,

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a mask layer pattern of a semiconductor device, a method of forming the same, and a semiconductor device manufacturing method using the same.

In recent years, as the degree of integration of semiconductor devices has increased sharply, the size of patterns constituting semiconductor devices has also been drastically reduced. As a result, the present photolithography technology has a limitation in forming a pattern of a certain size or smaller. For example, it is known that current photolithography equipment using an ArF light source is not capable of patterning half-pitich 39 nm or less. Accordingly, in a memory device such as a DRAM (Dynamic Random Access Memory), a bit line pattern of a linear cell side is formed using a SPT (Spacer Patterning Technology) process, and a bit line pattern Is formed using a double patterning technology. When applying a double patterning process that achieves a resolution of at least twice using two or more exposures, the first pattern produced by the first patterning affects the second pattern produced by the second patterning. Therefore, it is necessary that the first pattern is accurately formed. To do this, first, the mask layer pattern used in the first patterning must be accurately formed.

SUMMARY OF THE INVENTION A problem to be solved by the present invention is to provide a mask layer pattern of a semiconductor element and a method of forming the same, the height of which is uniform at the edge in the minor axis direction and the minor axis direction in the minor axis direction.

A problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device using the above-described mask layer pattern.

A mask layer pattern of a semiconductor device according to an embodiment of the present invention includes: a resist layer pattern disposed on a lower layer and having a short axis and a long axis; a resist layer pattern disposed on the top of the resist layer pattern, To compensate for the deviation of the edge height of the polymer layer.

The resist layer pattern has a structure in which the height at both edges is relatively lower than the height in the center.

The height of both edges in the major axis direction of the resist layer pattern is lower than the both side heights in the minor axis direction of the resist layer pattern.

The lower layer has a structure in which a nitride layer, a carbon layer, a silicon oxide nitride layer, and a lower antireflection layer are sequentially laminated.

A mask layer pattern of a semiconductor device according to another example of the present invention includes a resist layer pattern disposed on a lower layer and having a short axis and a long axis and a resist pattern layer disposed on the resist layer pattern, And a polymer layer in which the height and the height above the edge in the major axis direction are different from each other.

A method of forming a mask layer pattern of a semiconductor device according to an embodiment of the present invention includes the steps of forming a resist layer pattern having a short axis and a long axis on a lower layer and forming a polymer layer on the resist layer pattern, So that the height of the polymer layer on the edge of the major axis and the height of the polymer layer on the edge in the major axis direction are different from each other.

The resist layer pattern is formed in a structure in which the height at both edges is relatively lower than the height in the center.

Wherein the polymer layer has a height of the polymer layer on the edge in the minor axis direction of the resist layer pattern and a height of the polymer layer on the edge in the major axis direction of the resist layer pattern are respectively set to the edge height in the short axis direction of the resist layer pattern and the edge height Is compensated for.

The step of forming the polymer layer is performed using HBr gas and CH4 gas in a plasma etching equipment.

The step of forming the polymer layer is performed in a state where only the source power is applied without applying the bias power of the plasma etching equipment.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a first hard mask layer, a second hard mask layer, a third hard mask layer and an antireflection layer on an etching target layer on a substrate, A step of forming a resist layer pattern having a single axis and a long axis and forming a mask layer pattern together with the resist layer pattern on the top of the resist layer pattern, Forming an antireflective layer pattern and a third hard mask layer pattern by etching using a mask layer pattern; etching the third hard mask layer pattern by etching using the third hard mask layer pattern; Forming a first hard mask layer pattern by etching using a second hard mask layer pattern; And patterning the etch target layer by etching using the first hard mask layer pattern.

The step of forming the resist layer pattern is performed such that a structure having a relatively lower height at both edges than the height at the center is formed.

The step of forming the polymer layer may include forming the polymer layer on the polymer layer on the edge in the short axis direction of the resist layer pattern and the height of the polymer layer on the edge in the long axis direction, So as to compensate for the deviation of the height of the edge.

The step of forming the polymer layer is performed using HBr gas and CH4 gas in a plasma etching equipment.

The step of forming the polymer layer is performed in a state where only the source power is applied without applying the bias power of the plasma etching equipment.

The etch target layer, the first hardmask layer, the second hardmask layer, and the third hardmask layer each comprise a tungsten layer, a nitride layer, a carbon layer, and a silicon oxynitride layer.

According to the present invention, it is possible to manufacture a mask layer pattern of a semiconductor element having a uniform height at the edge in the short axis direction and at the edge in the major axis direction. In manufacturing a semiconductor device using such a mask layer pattern, It is possible to suppress the phenomenon that the line width of the liquid crystal display panel changes abnormally.

FIGS. 1A to 1C and FIGS. 2A to 2C are diagrams illustrating a process of forming a pattern of a semiconductor device using a mask layer pattern as a general resist layer pattern.
3A is a plan view showing a resist layer pattern included in a mask layer pattern according to an example of the present invention.
FIG. 3B is a cross-sectional view of the mask layer pattern according to an exemplary embodiment of the present invention, taken along the line 3B-3B 'of FIG. 3A.
FIG. 3C is a cross-sectional view of the mask layer pattern according to an exemplary embodiment of the present invention, taken along the line 3C-3C 'of FIG. 3A.
4 is a view showing an example of an inductively coupled plasma apparatus used for forming a polymer layer.
FIGS. 5A to 9A and FIGS. 5B to 9B are cross-sectional views illustrating a method of manufacturing a semiconductor device using a mask layer pattern according to an embodiment of the present invention.

FIGS. 1A to 1C and FIGS. 2A to 2C are diagrams illustrating a process of forming a pattern of a semiconductor device using a mask layer pattern as a general resist layer pattern. Figs. 1B and 1C are cross-sectional views, respectively, taken along line 1B-1B 'and 1C-1C' of Fig. 1A. Figs. 2B and 2C are cross-sectional views taken along line 2B-2B 'and 2C-2C' of Fig. 2A, respectively. First, as shown in FIGS. 1A to 1C, an etching target layer 120 is disposed on a substrate 110, and a resist layer pattern 130 is formed on the etching target layer 120 using a normal photolithography process. The resist layer pattern 130 has openings exposing a part of the surface of the etching target layer 120 and is formed in a stripe shape arranged long in a predetermined direction, for example, in a lateral direction. Accordingly, the resist layer pattern 130 has a minor axis in the direction 1B-1B 'and a major axis in the direction 1C-1C'. The short axis of the resist layer pattern 130 has a relatively short uniaxial length W1 and the long axis of the resist layer pattern 130 has a relatively long major axis length W2. In the process of forming the resist layer pattern 130, the height at the center portion and the height difference h1 at the edge are relatively small in the short axis direction of the relatively short uniaxial length W1, while the relatively long major axis length The height at the center portion and the height h2 at the edge relatively largely deviate in the major axis direction of the wafer W1. Considering that the height of the resist layer pattern 130 at the central portion in the minor axis direction and the major axis direction is similar, the height h2 at the edge in the major axis direction is relatively larger than the height h1 at the edge in the minor axis direction .

2A to 2C, a dry etching process is performed on the etching target layer (120 in FIGS. 1A to 1C) using the resist layer pattern 130 as an etching mask to form an etching target layer pattern 122. Next, as shown in FIG. After the etching target layer pattern 122 is formed, the resist layer pattern 130 is removed. The dry etching process using the resist layer pattern 130 as an etching mask is performed so that the etching target layer pattern 122 should have substantially the same shape and size as the resist layer pattern 130. [ The shape of the etching target layer pattern 122 is a shape having a short axis and a long axis similarly to the resist layer pattern 130. [ However, as shown in FIG. 2B, the length W1 'of the resist layer pattern 130 is substantially the same as the short axis length W1 of the resist layer pattern 130 in the minor axis direction. However, (W2 ') shorter than the width W2. This is because the edge height h2 of the resist layer pattern 130 in the major axis direction is relatively low, so that over etching is performed on the side surface of the etching target layer 120 in the etching process. The distance d2 between the patterns adjacent to each other along the major axis direction of the finally formed etching target layer pattern 122 is smaller than the distance d2 between adjacent patterns of the resist layer pattern 130 used as the etching mask ). In the case where the etch target pattern 122 having a different standard is formed as described above, if the deviation of the standard exceeds the allowable value, malfunction of the device may be caused. Particularly, a double patterning process in which the first created pattern affects the second generated pattern is applied The possibility of malfunction of the device becomes larger.

Accordingly, the mask layer pattern according to an exemplary embodiment of the present invention includes a resist layer pattern and a polymer layer. The resist layer pattern has a structure having a short axis and a long axis on the lower layer. The polymer layer is disposed on the top of the resist layer pattern so that the edge height in the minor axis direction of the resist layer pattern and the deviation of the edge height in the major axis direction are compensated. That is, the height of the resist layer pattern on the edge in the short axis direction and the height on the edge in the major axis direction are differently arranged on the upper portion of the resist layer pattern. According to such a mask layer pattern, the heights at the edges in the minor axis direction and the major axis direction are substantially equal to each other, and therefore, a deviation in the seed pattern of the etching target film pattern due to the height deviation of the mask layer pattern at the time of etching the lower etching target film . Hereinafter, the present invention will be described in detail with reference to the drawings.

3A is a plan view showing a resist layer pattern included in a mask layer pattern according to an example of the present invention. And FIGS. 3B and 3C are cross-sectional views of the mask layer pattern according to an exemplary embodiment of the present invention, respectively, taken along line 3B-3B 'and 3C-3C' of FIG. 3A. 3A to 3C, an etching target layer 320 is disposed on a substrate 310, and a mask layer pattern 350 according to the present example is disposed on the etching target layer 320. The etching target layer 320 is a target layer on which patterning is performed by etching using the mask layer pattern 350 as an etching mask. The etch target layer 320 may be a single layer, but may be formed of a plurality of layers as the case may be. In this case, at least one hard mask layer may be disposed between the pattern layer 350 and the target layer to be patterned.

The mask layer pattern 350 includes a lower resist layer pattern 330 and an upper polymer layer 340. The resist layer pattern 330 is formed using a normal photolithography process. Specifically, a resist layer is formed on the etching target layer 320, and an exposure process and a developing process are performed. A resist layer pattern 330 having openings exposing a part of the surface of the etching target layer 320 is formed by the exposure process and the developing process. The resist layer pattern 330 may have various shapes, but in this example, the resist layer pattern 330 may be formed in a stripe shape (for example, . Accordingly, the resist layer pattern 330 has a short width in the 3B-3B 'direction and a long length in the 3C-3C' direction. In this example, the short width in the 3B-3B 'direction of the resist layer pattern 330 is defined as a short axis, and the long length in the 3C-3C' direction of the resist layer pattern 330 is defined as the long axis . The minor axis of the resist layer pattern 330 has a relatively short minor axis length W3 and the major axis of the resist layer pattern 330 has a relatively long major axis length W4. The height of the resist layer pattern 330 is not entirely uniform, and in particular, the height at both edges is relatively lower than the height in the center in both the minor axis direction and the major axis direction. The resist layer pattern 330 also has different heights at the edge in the minor axis direction and the edge in the major axis direction. Such a height variation occurs naturally in the process of forming the resist layer pattern 330. Specifically, the height h3 at the edge in the minor axis direction is relatively high, while the height h3 at the edge in the relatively long major axis direction (H4) is relatively low.

The polymer layer 340 disposed on the resist layer pattern 330 has a height h5 at the edge in the minor axis direction is relatively low while a height h6 at the edge in the major axis direction is relatively high. The height h5 of the polymer layer 340 at the edge in the minor axis direction and the height h6 of the polymer layer 340 at the edge in the major axis direction are different from each other. Specifically, the height h6 of the polymer layer 340 at the edge in the major axis direction is higher than the height h5 of the polymer layer 340 at the edge in the minor axis direction. The height deviation is substantially equal to the difference between the edge height in the minor axis direction and the edge height in the major axis direction of the resist layer pattern 330. The polymer layer 340 compensates for the difference in height of the edge of the resist layer pattern 330 in the minor axis direction and the height of the edge in the major axis direction and consequently the resist layer pattern 330 and the polymer layer 340, The total height h3 + h5 at the edge in the minor axis direction of the mask layer pattern 350 made of the main mask 350 and the total height h4 + h6 at the edge in the major axis direction are substantially equal to each other.

3A, in order to form the mask layer pattern 350 composed of the resist layer pattern 330 and the polymer layer 340, a resist layer pattern having a short axis and a long axis is formed on the etching target layer 320 330 are formed. The resist layer pattern 330 is formed using a normal photolithography process. A resist layer pattern 330 having openings for exposing a part of the surface of the etching target layer 320 is formed by forming a resist layer on the etching target layer 320 and then performing an exposure process using a photomask and a developing process using a developing solution, ) Can be formed. The shape of the resist layer pattern 330 is determined by the pattern shape of the photomask used in the exposure process. In this example, the resist layer pattern 330 has openings exposing a part of the surface of the etching target layer 320, and is formed in a stripe shape arranged in a predetermined direction, for example, along the lateral direction. Accordingly, the resist layer pattern 330 has a short axis in the 3B-3B 'direction and a long axis in the 3C-3C' direction. The minor axis of the resist layer pattern 330 has a relatively short minor axis length W3 and the major axis of the resist layer pattern 330 has a relatively long major axis length W4. As shown in FIGS. 3B and 3C, the height of the resist layer pattern 330 is not uniform as a whole, and in particular, the height at both edges is relatively lower than the height in the center in both the minor axis direction and the major axis direction. The resist layer pattern 330 also has different heights at the edge in the minor axis direction and the edge in the major axis direction. Such a height deviation naturally occurs in the process of forming the resist layer pattern 330. Specifically, the height h3 at the edge in the minor axis direction is relatively high, while the height h3 at the edge in the relatively long major axis direction (H4) is relatively low.

3A and 3B, a polymer layer 340 is formed on the resist layer pattern 330 to form a resist layer pattern 330 and a polymer layer 340, The mask layer pattern 350 is formed. The polymer layer 340 is formed such that the height h5 of the polymer layer 340 at the edge in the minor axis direction is different from the height h6 of the polymer layer 340 at the edge in the major axis direction. Specifically, the height h6 of the polymer layer 340 at the edge in the major axis direction is higher than the height h5 of the polymer layer 340 at the edge in the minor axis direction. The height deviation is substantially equal to the difference between the edge height in the minor axis direction and the edge height in the major axis direction of the resist layer pattern 330. The polymer layer 340 compensates for the difference in height of the edge of the resist layer pattern 330 in the minor axis direction and the height of the edge in the major axis direction and consequently the resist layer pattern 330 and the polymer layer 340, The total height h3 + h5 at the edge in the minor axis direction of the mask layer pattern 350 made of the main mask 350 and the total height h4 + h6 at the edge in the major axis direction are substantially equal to each other.

 In one example, the formation of the polymer layer 340 is performed in an Inductively Coupled Plasma (ICP) equipment. As shown in FIG. 4, the ICP equipment 400 has a chamber outer wall 420 defining a reaction space 410 in which a plasma is formed. A susceptor 440 for supporting a plasma processing object, for example, a substrate 310, is disposed below the chamber outer wall 420. A first power source 450 to which bias power is applied is connected to the susceptor 440. An inductive coupled plasma source 460 is disposed on top of the chamber outer wall 420 and a second power source 470 is coupled to the inductive coupled plasma source 460 to which the source power is applied. Although not shown in the drawing, a gas supply port (not shown) for supplying the reaction gas into the chamber is disposed through the chamber outer wall 420.

The substrate 310 on which the resist layer pattern 330 is formed is loaded on the susceptor 440 of the ICP equipment 400. Next, the reaction gas is supplied into the reaction space 410 of the ICP equipment 400, the source power is applied through the second power source 470 in a state where the bias power through the first power source 450 is not applied, Accordingly, a plasma is formed in the ICP equipment 400. The pressure of the ICP equipment 400 is about 5 mTorr to 10 mTorr, and HBr gas and CH4 gas are used as the reaction gas. The supply ratio of the HBr gas and the CH4 gas into the ICP equipment 400 is set to 20: 1 or less so that the polymer is sufficiently induced in the etching process for the resist layer pattern 330. As the source power is applied in the state where the plasma is formed, the resist layer pattern 330 is etched by the ionized particles in the plasma, and at the same time, the polymer is produced. Since the bias power toward the substrate 310 is not applied, the profile change of the resist layer pattern 330 due to the etching of the resist layer pattern 330 is negligible.

3B and 3C, the polymer generated in the etching process for the resist layer pattern 330 is adsorbed on the resist layer pattern 330 to form a polymer layer 340, Lt; RTI ID = 0.0 > 330 < / RTI > 3C) of the resist layer pattern 330, while both edges (390A in Fig. 3B) in the minor axis direction of the resist layer pattern 330 are relatively inclined. On the other hand, The slope is relatively gentle. Thus, the polymer is adsorbed in greater amounts at both edges in the major axis direction, where the slope is gentle than at both edges in the minor axis direction in which the slope is urgent. Accordingly, as the time for polymer adsorption is lengthened, the height of the polymer layer 340 at both edges in the major axis direction becomes higher than the height of the polymer layer 340 at both edges in the minor axis direction. Since the height of the polymer layer 340 formed in this process is proportional to the supply time of the reactive gas, the height of the polymer layer 340 can be controlled through the supply time of the reactive gas.

FIGS. 5A to 9A and FIGS. 5B to 9B are cross-sectional views illustrating a method of manufacturing a semiconductor device using a mask layer pattern according to an embodiment of the present invention. FIGS. 5A to 9A show cross-sectional structures taken along the line 3B-3B 'of FIG. 3A, and FIGS. 5B to 9B show cross-sectional views taken along the line 3C-3C' of FIG. 3A.

Referring to FIGS. 5A and 5B, a first hard mask layer 540, a second hard mask layer 550, a third hard mask layer 560, and a reflective layer 560 are formed on a target layer to be patterned, Blocking layer 570 are sequentially formed. The tungsten layer 530 is disposed on the insulating layer 520 over the substrate 510, but this is by way of example only and not by way of limitation. The first hardmask layer 540 and the second hardmask layer 550 are made of materials having sufficient etch selectivity between each other and likewise the second hardmask layer 550 and the third hardmask layer 560 are also made of Lt; RTI ID = 0.0 > etch selectivity < / RTI > In one example, the first hardmask layer 540, the second hardmask layer 550, and the third hardmask layer 560 are comprised of a nitride layer, a carbon layer, and a silicon oxide nitride layer, respectively. On the antireflection layer 570, a resist layer pattern 580 is formed. This resist layer pattern 580 is the same as the resist layer pattern 330 described with reference to Figs. 3A to 3C. In other words, the resist layer pattern 580 has a nonuniform height distribution as a whole, and particularly has a structure in which the height at both edges is relatively lower than the height in the both the minor axis direction and the major axis direction. The resist layer pattern 580 has different heights at the edges in the minor axis direction and the major axis direction. Specifically, the height h71 at the edge in the minor axis direction is relatively high, while the height h72 at the edge in the relatively long major axis direction is relatively low.

Referring to FIGS. 6A and 6B, a polymer layer 590 is formed on the resist layer pattern 580. The polymer layer 590 constitutes the mask layer pattern 600 together with the resist layer pattern 580. The mask layer pattern 600 is used as an etching mask for etching the lower antireflection layer 570 and the third hard mask layer 560. The height h81 of the polymer layer 590 at the edge in the minor axis direction is different from the height h82 of the polymer layer 590 at the edge in the major axis direction. Specifically, the height h82 of the polymer layer 590 at the edge in the major axis direction is higher than the height h81 of the polymer layer 590 at the edge in the minor axis direction. The height deviation h82-h81 is substantially equal to the deviation h71-h72 between the edge height h71 in the minor axis direction of the resist layer pattern 580 and the edge height h71 in the major axis direction. The polymer layer 590 compensates for the deviation h71-h72 between the edge height h71 in the minor axis direction and the edge height h72 in the major axis direction of the resist layer pattern 580. As a result, The total height h71 + h81 at the edge in the minor axis direction of the mask layer pattern 600 made up of the layer pattern 580 and the polymer layer 590 and the total height h72 + h82 at the edge in the major axis direction, Are substantially equal. In one example, the formation of such a polymer layer 590 is performed in an Inductively Coupled Plasma (ICP) equipment, the formation of which is the same as described with reference to FIG. 4, Is omitted.

7A and 7B, an etching process using the mask layer pattern 600 as an etching mask is performed to remove the exposed portion of the antireflection layer 570, and subsequently, the exposed portion of the third hard mask layer 560 . The third hard mask layer pattern 562 and the anti-reflection layer pattern 572 are formed by this etching process. The etching process is performed using a plasma etching method in an inductive coupled plasma apparatus. In one example, the etch for the antireflective layer 570 may be performed using an HBr / O2 < RTI ID = 0.0 > (HBr / O2) < / RTI & Of the reaction gas. In one example, if the third hardmask layer pattern 560 is formed of a silicon oxide nitride layer, the etch for forming the third hardmask layer pattern 562 may be performed at a pressure of about 8 mTorr to 12 mTorr Condition, a source power of about 600 W to 800 W, and a bias power of about 80 W to 150 W. The reaction gas of CHF3 / SF6 is used.

Since the edge height in the major axis direction of the mask layer pattern 600 is substantially equal to the edge height in the minor axis direction, the antireflection layer pattern 572 and the third hard mask layer pattern 562 are not over-etched. Therefore, the interval d4 between the patterns adjacent to each other along the major axis direction of the antireflection layer pattern 572 and the third hard mask layer pattern 562 finally formed is smaller than the interval d4 between the patterns of the resist layer pattern 600 used as the etching mask. The distance d3 between the adjacent patterns along the major axis direction of the substrate W is substantially the same. After the antireflection layer pattern 572 and the third hard mask layer pattern 562 are formed, the mask layer pattern 600 and the antireflection layer pattern 572 shown by dotted lines in the drawing are removed. The antireflection layer pattern 572 may be removed together with the mask layer pattern 600 in the process of removing the mask layer pattern 600.

Referring to FIGS. 8A and 8B, an exposed portion of the second hard mask layer (550 in FIGS. 7A and 7B) is removed by performing an etching process using the third hard mask layer pattern 562 as an etch mask, A second hard mask layer pattern 552 is formed that exposes some surfaces of the hard mask layer (540 of FIGS. 7A and 7B). The etching process is performed using a plasma etching method in an inductive coupled plasma apparatus. In one example, if the second hardmask layer pattern 550 is formed of a carbon layer, the etch for forming the second hardmask layer pattern 552 may be performed at a pressure of approximately 3 mTorr to 5 mTorr in the inductive coupled plasma equipment, N2 / CH4 with a source power of about 500 W to about 800 W and a bias power of about 250 W to about 350 W. [ After forming the second hard mask layer pattern 552, the third hard mask layer pattern 562 is removed, as indicated by the dotted line in the figure. Next, the exposed portions of the first hard mask layer (540 in FIGS. 7A and 7B) are removed by etching with the second hard mask layer pattern 552 as an etch mask. This etching process produces a first hard mask layer pattern 542 that exposes some surfaces of the tungsten layer 530.

Referring to FIGS. 9A and 9B, an etching process using the first hard mask layer pattern (542 in FIGS. 8A and 8B) and the second hard mask layer pattern (552 in FIGS. 8A and 8B) (530 in Figs. 8A and 8B) is removed to form a tungsten layer pattern 532. [0157] After forming the tungsten layer pattern 532, the second hard mask layer pattern (552 in FIGS. 8A and 8B) and the first hard mask layer pattern (542 in FIGS. 8A and 8B) are sequentially removed.

310, 510 ... substrate 320 ... etch target layer
330, 580 ... resist layer pattern 340 ... polymer layer
400 ... ICP equipment 410 ... reaction space
420 ... chamber outer wall 440 ... susceptor
450 ... first power source 460 ... inductive coupled plasma source
470 ... second power source 520 ... insulating layer
530 ... tungsten layer 540 ... first hard mask layer
550 ... second hard mask layer 560 third hard mask layer
570 ... antireflection layer

Claims (20)

A resist layer pattern disposed on the lower layer and having a short axis and a long axis; And
And a polymer layer disposed on the resist layer pattern so as to compensate for a variation in edge height in the minor axis direction and a minor axis height in the minor axis direction of the resist layer pattern. The method according to claim 1,
Wherein the resist layer pattern has a structure in which the height at both edges is relatively lower than the height in the center. The method according to claim 1,
Wherein the height of both edges in the major axis direction of the resist layer pattern is lower than the height of both edges in the minor axis direction of the resist layer pattern. The method according to claim 1,
Wherein the lower layer has a structure in which a nitride layer, a carbon layer, a silicon oxide nitride layer, and a lower antireflection layer are sequentially laminated. A resist layer pattern disposed on the lower layer and having a short axis and a long axis; And
And a polymer layer disposed on the resist layer pattern, wherein the height of the resist layer pattern on the edge in the minor axis direction and the height on the edge in the major axis direction are different from each other. 6. The method of claim 5,
Wherein the resist layer pattern has a structure in which the height at both edges is relatively lower than the height in the center. 6. The method of claim 5,
Wherein the height of both edges in the major axis direction of the resist layer pattern is lower than the height of both edges in the minor axis direction of the resist layer pattern. 6. The method of claim 5,
The height of the polymer layer in the short axis direction on the edge in the short axis direction and the height on the edge in the major axis direction are set so that the deviation of the edge height in the minor axis direction of the resist layer pattern and the height of the edge in the major axis direction The mask layer pattern of the semiconductor element. 6. The method of claim 5,
Wherein the lower layer has a structure in which a nitride layer, a carbon layer, a silicon oxide nitride layer, and a lower antireflection layer are sequentially laminated. Forming a resist layer pattern having a short axis and a long axis on a lower layer; And
Forming a polymer layer on the resist layer pattern so that the height of the polymer layer on the edge in the minor axis direction of the resist layer pattern and the height of the polymer layer on the edge in the major axis direction are different from each other, Mask pattern. 11. The method of claim 10,
Wherein the resist layer pattern is formed in a structure in which the heights at both edges are relatively lower than the height in the center. 11. The method of claim 10,
Wherein the polymer layer has a height of the polymer layer on the edge in the minor axis direction of the resist layer pattern and a height of the polymer layer on the edge in the major axis direction of the resist layer pattern, Wherein the height of the mask layer pattern is set to be a height to compensate for the deviation of the edge height. 11. The method of claim 10,
Wherein the step of forming the polymer layer is performed using HBr gas and CH4 gas in a plasma etching equipment. 14. The method of claim 13,
Wherein the forming of the polymer layer is performed in a state where only the source power is applied without applying the bias power of the plasma etching equipment. Forming a first hardmask layer, a second hardmask layer, a third hardmask layer, and an antireflective layer on the etch target layer on the substrate;
Forming a resist layer pattern having a short axis and a long axis on the antireflection layer;
Wherein the resist layer pattern is formed on the top of the resist layer pattern to form a mask layer pattern together with the resist layer pattern, wherein the height of the resist layer pattern on the edge in the short axis direction and the height on the edge in the major axis direction are different from each other Forming a layer;
Forming an antireflection layer pattern and a third hard mask layer pattern by etching using the mask layer pattern;
Forming a second hard mask layer pattern by etching using the third hard mask layer pattern;
Forming a first hard mask layer pattern by etching using the second hard mask layer pattern; And
And patterning the etching target layer by etching using the first hard mask layer pattern. 16. The method of claim 15,
Wherein the resist layer pattern is formed so as to have a relatively low height at both edges than the height in the center. 16. The method of claim 15,
Wherein the step of forming the polymer layer comprises the step of forming the polymer layer on the polymer layer on the edge in the minor axis direction of the resist layer pattern and the height of the polymer layer on the edge in the major axis direction, So that the deviation of the edge height in the major axis direction is compensated. 16. The method of claim 15,
Wherein the step of forming the polymer layer is performed using HBr gas and CH4 gas in a plasma etching equipment. 16. The method of claim 15,
Wherein the forming of the polymer layer is performed in a state where only the source power is applied without applying the bias power of the plasma etching equipment. 16. The method of claim 15,
Wherein the etch target layer, the first hardmask layer, the second hardmask layer, and the third hardmask layer each comprise a tungsten layer, a nitride layer, a carbon layer, and a silicon oxynitride layer.
KR1020120151419A 2012-12-21 2012-12-21 Mask layer pattern in semiconductor device, method of fabricating the same, and method of manufacturing the semiconductor device using the resist layer pattern KR20140081542A (en)

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