KR20140080947A - Stack type semiconductor circuit with impedance calibration - Google Patents

Stack type semiconductor circuit with impedance calibration Download PDF

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Publication number
KR20140080947A
KR20140080947A KR1020120150166A KR20120150166A KR20140080947A KR 20140080947 A KR20140080947 A KR 20140080947A KR 1020120150166 A KR1020120150166 A KR 1020120150166A KR 20120150166 A KR20120150166 A KR 20120150166A KR 20140080947 A KR20140080947 A KR 20140080947A
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KR
South Korea
Prior art keywords
semiconductor chips
impedance
impedance adjustment
semiconductor
semiconductor chip
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KR1020120150166A
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Korean (ko)
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KR102047932B1 (en
Inventor
변상진
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에스케이하이닉스 주식회사
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Priority to KR1020120150166A priority Critical patent/KR102047932B1/en
Priority to US13/845,628 priority patent/US9030026B2/en
Publication of KR20140080947A publication Critical patent/KR20140080947A/en
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Publication of KR102047932B1 publication Critical patent/KR102047932B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

Abstract

The present invention relates to a stack type semiconductor circuit in which a plurality of semiconductor chips are stacked. An external resistor connection pad of any one semiconductor chip among the plurality of semiconductor chips is connected to an external resistor. Any one semiconductor chip is impedance-calibrated on the basis of the external resistor, and as a result, an impedance calibration signal is shared by the remaining semiconductor chips through a plurality of through vias.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a stacked semiconductor circuit having an impedance adjusting function,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to a laminate type semiconductor circuit having an impedance adjusting function.

The semiconductor circuit must perform an operation to adjust the impedance of the corresponding configuration to the target value for correct configuration of the on die termination circuit and the driver. Therefore, the semiconductor circuit must have an impedance adjusting section for impedance adjustment.

The semiconductor circuit can be formed by stacking a plurality of semiconductor chips. In this case, if the impedance adjustment is not performed on each semiconductor chip, the operation performance of the system including a plurality of semiconductor chips can be reduced.

An embodiment of the present invention provides a laminate type semiconductor circuit which enables accurate impedance adjustment.

An embodiment of the present invention is a laminate type semiconductor circuit in which a plurality of semiconductor chips are stacked, wherein an external resistor connection pad of one of the plurality of semiconductor chips is connected to an external resistor, As a result of performing the impedance adjustment operation based on the resistance, the impedance adjustment signal may be configured to be shared by the remaining semiconductor chips through the plurality of through vias.

An embodiment of the present invention is a laminate type semiconductor circuit in which a plurality of semiconductor chips are stacked, wherein an external resistor connection pad of one of the plurality of semiconductor chips is connected to an external resistor, The result of performing the impedance adjustment operation based on the resistance may be shared by the remaining semiconductor chips through the plurality of through vias and the data output operation of the plurality of semiconductor chips may be performed through any one of the semiconductor chips.

An embodiment of the present invention is a laminated semiconductor circuit in which a plurality of semiconductor chips are stacked, wherein an external resistor connection pad of one of the plurality of semiconductor chips is connected to an external resistor, Output pads are connected to each other via through vias, and one of the semiconductor chips performs an impedance adjustment operation on the basis of the external resistor, receives data of the other semiconductor chips including itself, Lt; / RTI >

The present technique can improve the impedance performance of the stacked semiconductor circuit.

1 is a block diagram of a stacked-type semiconductor circuit 1 according to an embodiment of the present invention;
2 is a block diagram of a stacked semiconductor circuit 300 according to another embodiment of the present invention.
3 is a block diagram of a layered semiconductor circuit 400 according to another embodiment of the present invention,
4 is a block diagram of a stacked semiconductor circuit 500 according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a layered semiconductor circuit 1 according to an embodiment of the present invention.

1, a first semiconductor chip 10 and a second semiconductor chip 20 are stacked in a stacked type semiconductor circuit 1 according to an embodiment of the present invention.

The external resistors Rext1 and Rext2 are connected to the external resistor connection pads ZQ of the first semiconductor chip 10 and the second semiconductor chip 20, respectively.

That is, the external resistor Rext1 is connected to the external resistor connection pad ZQ of the first semiconductor chip 10 and another external resistor Rext2 is connected to the external resistor connection pad ZQ of the second semiconductor chip 20. [ Lt; / RTI >

The first semiconductor chip 10 includes an impedance adjusting unit 11, a driving block 12, and a data input / output pad DQ.

The driving block 12 drives the data DATA and outputs the data to the data input / output pad DQ.

The impedance adjusting unit 11 adjusts the impedance of the driving block 12 based on an external resistor Rext1 connected to the external resistance connecting pad ZQ.

The impedance adjusting unit 11 sets the impedance of the driving block 12 to the external resistance Rext1 using the impedance adjustment signals PCODE <0: N> and NCODE <0: N> generated based on the external resistance Rext1. Is adjusted to the same value as the impedance adjustment operation.

The second semiconductor chip 20 includes an impedance adjusting unit 21, a driving block 22, and a data input / output pad DQ.

The driving block 22 drives the data DATA and outputs the data to the data input / output pad DQ.

The impedance adjusting unit 21 adjusts the impedance of the driving block 22 based on an external resistor Rext1 connected to the external resistance connecting pad ZQ.

The impedance adjusting unit 21 sets the impedance of the driving block 22 to the external resistance Rext2 using the impedance adjustment signals PCODE <0: N> and NCODE <0: N> Is adjusted to the same value as the impedance adjustment operation.

That is, the first semiconductor chip 10 and the second semiconductor chip 20 can perform independent impedance adjustment operations using external resistors Rext1 and Rext2 that are independent of each other.

2 is a block diagram of a stacked semiconductor circuit 300 according to another embodiment of the present invention.

2, a first semiconductor chip 310 and a second semiconductor chip 320 are arranged in a matrix form for convenience of description. The semiconductor chip 300 includes a plurality of semiconductor chips, Respectively. Hereinafter, the first semiconductor chip 310 and the second semiconductor chip 320 will be mainly described.

In the stacked type semiconductor circuit 300 according to another embodiment of the present invention, only one of the plurality of stacked semiconductor chips performs the impedance adjustment operation, and the impedance adjustment operation result is shared by the remaining semiconductor chips, . At this time, data output of a plurality of stacked semiconductor chips is performed independently through respective data input / output pads DQ.

The external resistor connection pad ZQ of the first semiconductor chip 310 is connected to the external resistor Rext.

The external resistor connection pads ZQ of all the semiconductor chips including the first semiconductor chip 310 and the second semiconductor chip 320 are not connected to each other.

At this time, a through silicon via (TSV) may be used as the through via.

The data input / output pads DQ of the first semiconductor chip 310 and the data input / output pads DQ of the second semiconductor chip 320 are connected to each other through the through vias TSV.

The signal lines for transmitting the impedance adjustment signals PCODE <0: N> and NCODE <0: N> of the first semiconductor chip 310 and the impedance adjustment signals PCODE <0 : N >, NCODE < 0: N >) are connected through a plurality of through vias (TSV).

The first semiconductor chip 310 includes an impedance adjusting unit 311, a driving block 312, a data input / output pad DQ, an external resistance connection pad ZQ and a plurality of through vias TSV.

The driving block 312 sets the impedance in response to the impedance adjustment signals PCODE <0: N> and NCODE <0: N>, drives the data DATA and outputs the data to the data input / output pad DQ .

When the impedance adjustment enable signal ZQCAL is activated, the impedance adjustment unit 311 uses the impedance adjustment signals PCODE <0: N> and NCODE <0: N> generated based on the external resistor Rext, And adjust the impedance of the block 312 to the same value as the external resistance Rext.

At this time, the impedance adjustment enable signal ZQCAL may be an internal signal of the impedance adjusting unit 311 or an external signal.

The impedance adjustment operation may be performed during an initial operation period of the semiconductor circuit, and the impedance adjustment enable signal ZQCAL may be generated internally or externally to define an impedance adjustable period.

The second semiconductor chip 320 may include only the driving block 322, the data input / output pad DQ and the plurality of through vias TSV except for the impedance adjusting portion 321 and the external resistance connecting pad ZQ .

In another embodiment of the present invention, the impedance adjustment signals PCODE <0: N> and NCODE <0: N> generated by performing the impedance adjustment operation in the first semiconductor chip 310 are supplied to the second semiconductor chip 320 So that impedance adjustment can be automatically performed.

Therefore, the semiconductor chips other than the first semiconductor chip 310 can exclude the impedance adjusting section 321 and the external resistor connection pad ZQ from the circuit configuration.

However, it may be more difficult to configure different chips for productivity. Therefore, in the example in which the second semiconductor chip 320 includes the impedance adjusting section 321, the external resistance connection pad ZQ, the driving block 322, the data input / output pad DQ and the plurality of through vias TSV .

The driving block 322 sets the impedance in response to the impedance adjustment signals PCODE <0: N> and NCODE <0: N>, drives the data DATA and outputs the data to the data input / output pad DQ .

The impedance adjusting operation of the above-described embodiment of the present invention will now be described.

First, when the impedance adjustment enable signal ZQCAL is activated, the first semiconductor chip 310 performs an impedance adjustment operation.

The impedance adjustment signals PCODE <0: N> and NCODE <0: N> generated by the first semiconductor chip 310 are transmitted to the second semiconductor chip 320 through the plurality of through vias TSV.

Accordingly, the impedance adjustment operation of the first semiconductor chip 310 and the impedance adjustment operation of all the semiconductor chips including the second semiconductor chip 320 are automatically performed.

At this time, data output of the first semiconductor chip 310 and the second semiconductor chip 320 is performed through their respective data input / output pads DQ.

However, the data output through the data input / output pad DQ of the second semiconductor chip 320 is transmitted to the data input / output pad DQ of the first semiconductor chip 310 through the through vias TSV .

3 is a block diagram of a stacked semiconductor circuit 400 according to another embodiment of the present invention.

3, a first semiconductor chip 410 and a second semiconductor chip 420 are stacked for convenience of description, and a plurality of semiconductor chips are stacked in the stacked semiconductor circuit 400 according to another embodiment of the present invention. Respectively. Hereinafter, the first semiconductor chip 410 and the second semiconductor chip 420 will be mainly described.

In the stacked semiconductor circuit 400 according to another embodiment of the present invention, only one of the plurality of stacked semiconductor chips performs the impedance adjustment operation, the impedance adjustment operation result is shared by the remaining semiconductor chips, and the impedance adjustment is automatically performed . The data output of a plurality of stacked semiconductor chips is also performed through a data input / output pad (DQ) of a semiconductor chip performing an impedance adjustment operation.

However, by connecting the data input / output pads DQ of all the semiconductor chips through the through vias, the semiconductor chips that do not perform the impedance adjustment operation perform the on-die termination operation.

The external resistor connection pad ZQ of the first semiconductor chip 410 is connected to the external resistor Rext.

The external resistor connection pads ZQ of all the semiconductor chips including the first semiconductor chip 410 and the second semiconductor chip 420 are not connected to each other.

The data input / output pads DQ of the first semiconductor chip 410 and the data input / output pads DQ of the second semiconductor chip 420 are connected to each other through the through vias TSV.

At this time, a through silicon via (TSV) may be used as the through via.

The signal lines for transmitting the impedance adjustment signals PCODE <0: N> and NCODE <0: N> of the first semiconductor chip 410 and the impedance adjustment signals PCODE <0: N>, NCODE <0: N>) are connected through a plurality of through vias (TSV).

Signal lines for transmitting data of the first semiconductor chip 410 and signal lines for transmitting data of the second semiconductor chip 420 are connected through a plurality of through vias TSV.

The first semiconductor chip 410 includes an impedance adjusting unit 411, a driving block 412, a data input / output pad DQ, an external resistance connecting pad ZQ and a plurality of through vias TSV.

The driving block 412 sets the impedance in response to the impedance adjustment signals PCODE <0: N> and NCODE <0: N>, drives the data DATA and outputs the data to the data input / output pad DQ .

When the impedance adjustment enable signal ZQCAL is activated, the impedance adjustment unit 411 uses the impedance adjustment signals PCODE <0: N> and NCODE <0: N> generated based on the external resistor Rext, And to adjust the impedance of the block 412 to the same value as the external resistance Rext.

At this time, the impedance adjustment enable signal ZQCAL may be an internal signal of the impedance adjusting unit 411 or an external signal.

The impedance adjustment operation may be performed during an initial operation period of the semiconductor circuit, and the impedance adjustment enable signal ZQCAL may be generated internally or externally to define an impedance adjustable period.

The second semiconductor chip 420 may include only the driving block 422, the data input / output pad DQ and the plurality of through vias TSV except for the impedance adjusting portion 421 and the external resistance connection pad ZQ .

At this time, according to another embodiment of the present invention, the impedance adjustment signals (PCODE <0: N>, NCODE <0: N>) generated by performing the impedance adjustment operation in the first semiconductor chip 410 are supplied to the second semiconductor chip 420 So that impedance adjustment can be automatically performed.

Therefore, the semiconductor chips other than the first semiconductor chip 410 can exclude the impedance adjusting unit 421 and the external resistor connection pad ZQ from the circuit configuration.

However, it may be more difficult to configure different chips for productivity. Therefore, in the example in which the second semiconductor chip 420 includes the impedance adjusting section 421, the external resistance connection pad ZQ, the driving block 422, the data input / output pad DQ and the plurality of through vias TSV .

The driving block 422 sets the impedance in response to the impedance adjustment signals PCODE <0: N>, NCODE <0: N>.

The impedance adjusting operation of the stacked-type semiconductor circuit 400 according to another embodiment of the present invention will now be described.

First, when the impedance adjustment enable signal ZQCAL is activated, the first semiconductor chip 410 performs the impedance adjustment operation.

The impedance adjustment signals PCODE <0: N> and NCODE <0: N> generated by the first semiconductor chip 410 are transmitted to the second semiconductor chip 420 through the plurality of through vias TSV.

Accordingly, the impedance adjustment operation of all the semiconductor chips including the second semiconductor chip 420 is automatically performed simultaneously with the impedance adjustment operation of the first semiconductor chip 410.

Data (DATA) of all the semiconductor chips including the second semiconductor chip 420 is transmitted to the first semiconductor chip 410 through the through vias TSV.

That is, the data output operation of all the semiconductor chips is performed through the data input / output pad DQ of the first semiconductor chip 410.

However, the semiconductor chips that do not perform the impedance adjustment operation by connecting the data input / output pads DQ of all the semiconductor chips through the through vias perform the on-die termination operation.

4 is a block diagram of a stacked semiconductor circuit 500 according to another embodiment of the present invention.

4, a first semiconductor chip 510 and a second semiconductor chip 520 are stacked for convenience of explanation, and a plurality of semiconductor chips are stacked on the stacked semiconductor circuit 500 according to another embodiment of the present invention. Respectively. Hereinafter, the first semiconductor chip 510 and the second semiconductor chip 520 will be mainly described.

A stacked semiconductor circuit 500 according to another embodiment of the present invention performs impedance adjustment only on one of a plurality of stacked semiconductor chips and outputs data of a plurality of stacked semiconductor chips, The data input / output pad DQ of the semiconductor chip of FIG.

The external resistor connection pad ZQ of the first semiconductor chip 510 is connected to the external resistor Rext.

The external resistor connection pads ZQ of all the semiconductor chips including the first semiconductor chip 510 and the second semiconductor chip 520 are not connected to each other.

The data input / output pads DQ of all the semiconductor chips including the first semiconductor chip 510 and the second semiconductor chip 520 are also not connected to each other.

Signal lines for transmitting data of the first semiconductor chip 510 and signal lines for transmitting data of the second semiconductor chip 520 are connected through the through vias TSV.

At this time, a through silicon via (TSV) may be used as the through via.

The first semiconductor chip 510 includes an impedance adjusting unit 511, a driving block 512, a data input / output pad DQ, an external resistance connecting pad ZQ, and a through via (TSV).

The driving block 512 sets the impedance in response to the impedance adjustment signals PCODE <0: N>, NCODE <0: N>, drives the data DATA and outputs the data to the data input / output pad DQ .

When the impedance adjustment enable signal ZQCAL is activated, the impedance adjustment unit 511 uses the impedance adjustment signals PCODE <0: N> and NCODE <0: N> generated based on the external resistance Rext, And adjust the impedance of the block 512 to the same value as the external resistance Rext.

At this time, the impedance adjustment enable signal ZQCAL may be an internal signal of the impedance adjusting unit 511 or an external signal.

The impedance adjustment operation may be performed during an initial operation period of the semiconductor circuit, and the impedance adjustment enable signal ZQCAL may be generated internally or externally to define an impedance adjustable period.

The second semiconductor chip 520 removes the impedance adjusting unit 521, the external resistor connecting pad ZQ, the driving block 522 and the data input / output pad DQ and is provided with through vias TSV).

At this time, in another embodiment of the present invention, only the first semiconductor chip 510 among the plurality of stacked semiconductor chips performs the impedance adjustment operation, and the data output is also applied to the data input / output pads DQ of the first semiconductor chip 510, .

Therefore, the second semiconductor chip 520 (including the remaining semiconductor chips) can exclude the impedance adjusting unit 521, the external resistance connection pad ZQ, the driving block 522, and the data input / output pad DQ from the circuit configuration have.

However, it may be more difficult to configure different chips for productivity. Therefore, in the case where the second semiconductor chip 520 is configured to include the impedance adjusting portion 521, the external resistance connecting pad ZQ, the driving block 522, the data input / output pad DQ, and the through vias TSV will be.

The impedance adjustment operation of the stacked-type semiconductor circuit 400 according to another embodiment of the present invention will now be described.

First, when the impedance adjustment enable signal ZQCAL is activated, the first semiconductor chip 510 performs an impedance adjustment operation.

Meanwhile, data (DATA) of all the semiconductor chips including the second semiconductor chip 520 is transmitted to the first semiconductor chip 510 through the through vias TSV.

That is, the data output operation of all the semiconductor chips is performed through the data input / output pad DQ of the first semiconductor chip 510.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (12)

1. A multi-layered semiconductor circuit in which a plurality of semiconductor chips are stacked,
And the plurality of semiconductor chips share the impedance adjustment information. The method according to claim 1,
The plurality of semiconductor chips
A signal line for transmitting an impedance adjustment signal according to a result of performing an impedance adjustment operation is connected to each other through a through via,
And the impedance adjustment signal is shared as the impedance adjustment information. 1. A multi-layered semiconductor circuit in which a plurality of semiconductor chips are stacked,
Wherein an external resistor connection pad of one of the plurality of semiconductor chips is connected to an external resistor,
And the impedance adjustment signal is shared by the remaining semiconductor chips through the plurality of through vias as a result of the impedance adjustment operation of any one of the semiconductor chips based on the external resistor. The method of claim 3,
The plurality of semiconductor chips
Each of which is configured to independently output data. 5. The method of claim 4,
And the data input / output pads of each of the plurality of semiconductor chips are connected to each other via through vias. The method of claim 3,
The one semiconductor chip
A driving block configured to set an impedance in response to the impedance adjustment signal as a result of performing the impedance adjustment operation and to drive and output data;
And an impedance adjusting unit configured to generate the impedance adjusting signal based on the external resistance. 1. A multi-layered semiconductor circuit in which a plurality of semiconductor chips are stacked,
Wherein an external resistor connection pad of one of the plurality of semiconductor chips is connected to an external resistor,
Wherein the semiconductor chips share the result of performing the impedance adjustment operation based on the external resistor through the plurality of through vias,
And the data output operation of the plurality of semiconductor chips is performed through any one of the semiconductor chips. 8. The method of claim 7,
And the data input / output pads of each of the plurality of semiconductor chips are connected to each other via through vias. 8. The method of claim 7,
The remaining semiconductor chips
And to perform an on-die termination operation according to the result of performing the impedance adjustment operation. 8. The method of claim 7,
The one semiconductor chip
A driving block configured to set an impedance in response to the impedance adjustment signal as a result of performing the impedance adjustment operation and to drive and output data;
And an impedance adjusting unit configured to generate the impedance adjusting signal based on the external resistance. 1. A multi-layered semiconductor circuit in which a plurality of semiconductor chips are stacked,
Wherein an external resistor connection pad of one of the plurality of semiconductor chips is connected to an external resistor,
The data input / output pads of each of the plurality of semiconductor chips are connected to each other through through vias,
Wherein one of the semiconductor chips performs an impedance adjustment operation based on the external resistor and receives data of the remaining semiconductor chips including itself and outputs the data through its own data input / output pad. 12. The method of claim 11,
The one semiconductor chip
A driving block configured to set an impedance in response to the impedance adjustment signal as a result of performing the impedance adjustment operation and to drive and output data;
And an impedance adjusting unit configured to generate the impedance adjusting signal based on the external resistance.
KR1020120150166A 2012-12-17 2012-12-21 Stack type semiconductor circuit with impedance calibration KR102047932B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020120150166A KR102047932B1 (en) 2012-12-21 2012-12-21 Stack type semiconductor circuit with impedance calibration
US13/845,628 US9030026B2 (en) 2012-12-17 2013-03-18 Stack type semiconductor circuit with impedance calibration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120150166A KR102047932B1 (en) 2012-12-21 2012-12-21 Stack type semiconductor circuit with impedance calibration

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Publication number Priority date Publication date Assignee Title
US9479166B1 (en) 2015-09-08 2016-10-25 SK Hynix Inc. Semiconductor devices and integrated circuits

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KR20230055839A (en) 2021-10-19 2023-04-26 한국과학기술원 Semiconductor device including pad pattern layers having stack-pad structure and fabricating method thereof

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KR100738961B1 (en) * 2006-02-22 2007-07-12 주식회사 하이닉스반도체 Apparatus for driving output of semiconductor memory
KR20110001410A (en) * 2009-06-30 2011-01-06 주식회사 하이닉스반도체 Circuit for calibrating impedance and semiconductor apparatus using the same
KR20110112707A (en) * 2010-04-07 2011-10-13 삼성전자주식회사 Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating delay time of transmission lines
KR20140078261A (en) * 2012-12-17 2014-06-25 에스케이하이닉스 주식회사 Stack type semiconductor circuit with impedance calibration

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Publication number Priority date Publication date Assignee Title
KR100738961B1 (en) * 2006-02-22 2007-07-12 주식회사 하이닉스반도체 Apparatus for driving output of semiconductor memory
KR20110001410A (en) * 2009-06-30 2011-01-06 주식회사 하이닉스반도체 Circuit for calibrating impedance and semiconductor apparatus using the same
KR20110112707A (en) * 2010-04-07 2011-10-13 삼성전자주식회사 Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating delay time of transmission lines
KR20140078261A (en) * 2012-12-17 2014-06-25 에스케이하이닉스 주식회사 Stack type semiconductor circuit with impedance calibration

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9479166B1 (en) 2015-09-08 2016-10-25 SK Hynix Inc. Semiconductor devices and integrated circuits

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