KR20140076106A - Transistor - Google Patents

Transistor Download PDF

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Publication number
KR20140076106A
KR20140076106A KR1020120144265A KR20120144265A KR20140076106A KR 20140076106 A KR20140076106 A KR 20140076106A KR 1020120144265 A KR1020120144265 A KR 1020120144265A KR 20120144265 A KR20120144265 A KR 20120144265A KR 20140076106 A KR20140076106 A KR 20140076106A
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KR
South Korea
Prior art keywords
active layer
oxide
layer
gate insulating
transistor
Prior art date
Application number
KR1020120144265A
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Korean (ko)
Inventor
차홍기
안성덕
황치선
Original Assignee
한국전자통신연구원
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Priority to KR1020120144265A priority Critical patent/KR20140076106A/en
Publication of KR20140076106A publication Critical patent/KR20140076106A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

A transistor according to one embodiment of the present invention includes an active layer and a gate insulating layer which touches the active layer. The active layer and the gate insulating layer include the same oxide. The oxygen content of the oxide of the gate insulating layer is higher than the oxygen content of the oxide of the active layer. Because the active layer and the gate insulating layer have the same material, high charge mobility in the active layer is obtained in driving the transistor. In manufacturing the transistor, the active layer and the gate insulating layer are formed by depositing the same material in the same sputtering chamber while changing oxygen partial pressure ratios.

Description

Transistor {Transistor}

The present invention relates to a transistor, and more particularly to an oxide thin film transistor.

As displays become more versatile, high-performance displays are being applied to smartphones, notebooks, and tablet computers. Oxide thin film transistors are attracting attention because they have the advantages of amorphous silicon transistors as well as low temperature polycrystalline silicon (LAPS) transistors. For example, oxide thin film transistors can be fabricated at low process cost and / or low process temperatures.

The transistor may have different characteristics depending on the material and configuration of the active layer. In order to improve the operating characteristics of the transistor, studies have been made to apply an oxide having a high charge mobility as an active layer. However, the active layer containing an oxide may be damaged by moisture and / or oxygen in the manufacturing process. In order to prevent this, it is required to form a protective layer covering the active layer immediately after the active layer is formed in the oxide thin film transistor process. In this case, it is troublesome to deposit the active layer, the protective layer, and the gate insulating film as different materials in different equipment.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a transistor having improved reliability.

It is another object of the present invention to provide a transistor having improved process efficiency.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

The present invention relates to a transistor. According to one embodiment, a transistor includes a source / drain electrode on a substrate, an active layer in contact with an edge of the source / drain electrode on the substrate, a gate electrode provided on the substrate, a gate electrode corresponding to the active layer, And a passivation layer disposed on the gate electrode and covering the active layer, wherein the active layer includes a first oxide, the gate insulating film includes a second oxide, and the first The oxide is composed of the same material as the second oxide, and may have a lower oxygen content ratio than the second oxide.

The transistor according to the present invention may include an active layer and a gate insulating film in contact with the active layer. The active layer may include a first oxide, and the gate insulating film may include a second oxide including the same material as the first oxide, but having a larger oxygen partial pressure ratio. Since the active layer and the gate insulating film include the same material, a high charge mobility in the active layer may be exhibited when the transistor is driven. The reliability of the transistor can be improved. In the manufacturing process of the transistor, the active layer and the gate insulating film can be formed by depositing the same material in the same sputtering chamber while the oxygen partial pressure ratio is different. The transistor can be efficiently fabricated in a short time through a continuous process.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding and assistance of the invention, reference is made to the following description, taken in conjunction with the accompanying drawings, in which:
1 is a cross-sectional view illustrating a transistor according to an embodiment of the present invention.
2 to 8 are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof. Those of ordinary skill in the art will understand that the concepts of the present invention may be practiced in any suitable environment.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

When a film (or layer) is referred to herein as being on another film (or layer) or substrate it may be formed directly on another film (or layer) or substrate, or a third film Or layer) may be interposed.

 Although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., it is to be understood that these regions, Can not be done. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. Like numbers refer to like elements throughout the specification.

The terms used in the embodiments of the present invention may be construed as commonly known to those skilled in the art unless otherwise defined.

Hereinafter, a transistor according to the present invention will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a transistor according to an embodiment of the present invention.

1, a transistor 1 includes a source / drain electrode 200, an active layer 300, a gate insulating film 400, a gate electrode 500, a passivation layer 600, and a metal layer 700).

The source / drain electrodes 200 may be disposed on the substrate 100. The substrate 100 may comprise a silicon wafer, glass, plastic, paper, or the like. The substrate 100 may further include a flat layer (not shown) or an insulating layer (not shown). The source / drain electrode 200 may be formed of an oxide (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or a metal material (e.g., titanium (Ti), molybdenum (Mo) Al) or the like). As another example, the source / drain electrode 200 may have a multilayer structure of titanium / aluminum / titanium (Ti / Al / Ti) or a multilayer structure of molybdenum / aluminum / molybdenum (Mo / Al / Mo).

An active layer 300 is provided on the substrate 100 and may contact the substrate 100 exposed by the source / drain electrodes 200. At least a portion of the active layer 300 may be disposed between the source / drain electrodes 200. The active layer 300 may extend over the source / drain electrodes 200 and may cover a part of the source / drain. The active layer 300 may be in contact with the edge of the source / drain electrode 200. The active layer 300 may include a first oxide, for example, indium gallium zinc oxide (IGZO), zinc oxide, gallium oxide, aluminum oxide, or combinations thereof. The active layer 300 may serve to provide a channel between the source / drain electrodes 200 when the transistor 1 operates. If the first oxide has an oxygen content ratio, the active layer 300 may exhibit nonconductive characteristics, so that it may be difficult to form a channel in the active layer 300. If the first oxide has an excessively low oxygen content ratio, the active layer 300 has a conductive characteristic, and it may be difficult for the transistor 1 to exhibit on / off characteristics. The oxygen content ratio of the first oxide can be adjusted as described later in FIG. 3 so that the active layer 300 exhibits semiconductor properties.

A gate insulating film 400 may be disposed between the active layer 300 and the gate electrode 500. The gate insulating film 400 may not contact the source / drain electrode 200. The gate insulating film 400 may include a second oxide including the same material as the first oxide but having a different oxygen content ratio. For example, the second oxide may have a higher oxygen content ratio than the first oxide. The oxygen content ratio of the second oxide can be adjusted as described later in FIG. 4 so that the gate insulating film 400 exhibits the poor sidewall characteristics. Accordingly, the gate insulating film 400 may have an insulating property.

The gate electrode 500 may be disposed on the gate insulating film 400 at a position corresponding to the active layer 300. The gate electrode 500 may not extend onto the source / drain electrode 200. The gate electrode 500 may include at least one of the materials described as an example of the source / drain electrode 200. For example, the gate electrode 500 may be formed of an oxide (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or a metal material (e.g., titanium (Ti), molybdenum Aluminum (Al) or the like). As another example, the gate electrode 500 may have a multilayer structure of titanium-aluminum-titanium or a multilayer structure of molybdenum-aluminum-molybdenum.

A passivation layer 600 may cover the source / drain electrode 200 and the gate electrode 500 on the substrate 100. The passivation layer 600 may be in contact with a part of the active layer 300. The passivation layer 600 may include an oxide dielectric, for example, aluminum oxide (Al 2 O 3 ), silicon oxide (SiO x ), or silicon nitride (SiN x ). The passivation layer 600 may include an insulating material of organic or inorganic complex. The passivation layer 600 may have a multi-layer structure. The passivation layer 600 may have a pattern and a portion of the gate electrode 500 and the source / drain electrode 100 may be exposed by the passivation layer 600.

A metal layer 700 may be disposed on the passivation layer 600. The metal layer 700 may include a first metal layer 710 and a second metal layer 720 spaced from the first metal layer 710. The metal layer 700 may include at least one of the materials described as examples of the source / drain electrodes 200. The first metal layer 710 may comprise the same material as the second metal layer 720. The first metal layer 710 may contact the gate electrode 500 to electrically connect the gate electrode 500 to the outside. The second metal layer 720 may be in contact with the source / drain electrode 200 to electrically connect the source / drain electrode 200 to the outside.

According to the present invention, an active layer protective film (not shown) may be omitted between the active layer 300 and the gate insulating film 400. The active layer protective film may be a layer containing a material different from that of the active layer 300. [ The active layer 300 may be in direct contact with the gate insulating layer 400. The contact resistance between the active layer 300 and the gate insulating layer 400 may be lower than the contact resistance between the active layer 300 and the active layer protective layer as the active layer 300 and the gate insulating layer 400 include the same material. Accordingly, when the transistor 1 of the present invention is driven, a high charge mobility can be exhibited in the active layer 300. The reliability of the transistor 1 can be improved.

2 to 8 are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention. Hereinafter, the overlapping description with reference to FIG. 1 will be omitted.

Referring to FIG. 2, the source / drain electrode 200 may be formed by depositing and etching an oxide or a metal material on the substrate 100. The formation of the source / drain electrodes 200 can be performed by atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or sputtering. The deposited oxide layer or the metal material layer may be etched to form the source / drain electrode 200 to expose a portion of the substrate 100. As another example, the source / drain electrode 200 may be formed to have a multilayer structure of titanium / aluminum / titanium (Ti / Al / Ti) or a multilayer structure of molybdenum / aluminum / molybdenum have.

Referring to FIG. 3, an active layer 300 may be formed on the substrate 100 by vapor deposition. The formation of the active layer 300 may be performed by atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or sputtering. The substrate 100 on which the source / drain electrodes 200 are formed may be disposed in a sputtering chamber (not shown). The active layer 300 may be formed to cover the source / drain electrode 200 and the exposed substrate 100 by sputtering a first oxide on the substrate 100. The first oxide may be indium gallium zinc oxide, zinc oxide, gallium oxide, aluminum oxide, or a combination thereof. Sputtering can be performed using argon gas and oxygen gas. As an example, sputtering of indium gallium zinc oxide may proceed with an oxygen partial pressure ratio of approximately 16: 4 to 19: 1. The oxygen partial pressure ratio may mean the ratio of argon gas (Ar) to oxygen gas (O 2 ) in the sputtering process. When the oxygen partial pressure ratio is high (for example, when the ratio of argon gas (Ar) to oxygen gas (O 2 ) is higher than 16: 4 in the case of the indium gallium zinc oxide sputtering), the first oxide has a high oxygen content ratio, 300) can exhibit the subduction characteristics. When the oxygen partial pressure ratio in the sputtering process is excessively low (for example, when the ratio of argon gas to oxygen gas in the case of the indium gallium-zinc oxide sputtering is lower than 19: 1), the active layer 300 exhibits conductive characteristics, Off characteristic, and can have an excessive negative threshold voltage. The oxygen partial pressure ratio of the argon gas to the oxygen gas may be adjusted from 16: 4 to 19: 1 so that the active layer 300 exhibits semiconductor characteristics.

Referring to FIG. 4, a gate insulating layer 400 may be formed on the active layer 300. The gate insulating layer 400 is formed by the same deposition method as the active layer 300, and may include a second oxide. For example, the gate insulating film 400 may be formed by sputtering the same material as the active layer 300 on the substrate 100 in the same sputtering chamber. Since the gate insulating layer 400 is formed in the same chamber as the active layer 300, the active layer 300 may not be exposed to moisture and / or air. Accordingly, a separate active layer protective film covering the active layer 300 may not be formed. Since the gate insulating layer 400 is formed by depositing the same material as the active layer 300, the process time may be reduced. The gate insulating film 400 can be sputtered under conditions that have a higher oxygen partial pressure ratio than the deposition of the active layer 300. [ The oxygen partial pressure ratio can be adjusted so that the gate insulating film 400 has the negative electrode characteristic. For example, the gate insulating film 400 may be sputtered with a ratio of argon gas to oxygen gas of 10: 10.

Referring to FIG. 5, a gate electrode 500 layer may be deposited on the gate insulating layer 400. The gate electrode 500 may be formed to cover the gate insulating film 400 by sputtering the material described in the example of FIG. 1 on the substrate 100.

Referring to FIG. 6, a part of the source / drain electrode 200 may be exposed by etching the active layer 300, the gate insulating layer 400, and the gate electrode 500. For example, a part of the gate electrode 500 can be removed by forming a mask on the gate electrode 500 and etching the gate electrode 500 exposed by the mask. A part of the active layer 300 and the gate insulating film 400 can be removed by etching using the gate electrode 500 as a mask. As the first oxide includes the same material as the second oxide, the active layer 300 and the gate insulating film 400 can be etched in a single process using the same etchant. The etching of the active layer 300, the gate insulating layer 400, and the gate electrode 500 can be performed by forming a single mask.

Referring to FIG. 7, a passivation layer 600 may be deposited on the substrate 100 to cover the exposed active layer 300. The passivation layer 600 may be formed by depositing an oxide dielectric or insulating material as described in the example of FIG. 1 on the substrate 100. The passivation layer 600 may be formed to cover the source / drain electrode 200 and the gate electrode 500. The passivation layer 600 may function to protect the active layer 300 exposed from moisture and / or oxygen.

Referring to FIG. 8, a portion of the gate electrode 500 and the source / drain electrode 200 may be exposed by etching the passivation layer 600.

Referring again to FIG. 1, a metal layer 700 may be formed on the exposed gate electrode 500 and the source / drain electrode 200. The metal layer 700 may be formed by depositing and etching the oxide dielectric or insulating material described in the example of FIG. The metal layer 700 may include a first metal layer 710 and a second metal layer 720. A first metal layer 710 and a second metal layer 720 spaced apart from each other by etching may be formed. The first metal layer 710 may contact the gate electrode 500 and the second metal layer 720 may contact the source / drain electrode 200. Thus, the production of the transistor 1 of the present invention can be completed.

In the method of manufacturing the transistor 1 of the present invention, the active layer 300 and the gate insulating layer 400 can be formed by depositing the same material in the same sputtering chamber while the oxygen partial pressure ratio is different. Thus, the transistor 1 can be efficiently manufactured in a short time through a continuous process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the present invention is not limited to the disclosed exemplary embodiments, and various changes and modifications may be made by those skilled in the art without departing from the scope and spirit of the invention. Change is possible.

Claims (1)

Source / drain electrodes on the substrate;
An active layer in contact with an edge of the source / drain electrode on the substrate;
A gate electrode provided on the substrate, the gate electrode corresponding to the active layer;
A gate insulating film interposed between the active layer and the gate electrode; And
And a passivation layer disposed on the gate electrode and covering the active layer,
Wherein the active layer comprises a first oxide,
Wherein the gate insulating film comprises a second oxide,
Wherein the first oxide is comprised of the same material as the second oxide and has a lower oxygen content ratio than the second oxide.
KR1020120144265A 2012-12-12 2012-12-12 Transistor KR20140076106A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110034178A (en) * 2019-04-19 2019-07-19 京东方科技集团股份有限公司 Thin film transistor (TFT) and preparation method thereof, array substrate and display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110034178A (en) * 2019-04-19 2019-07-19 京东方科技集团股份有限公司 Thin film transistor (TFT) and preparation method thereof, array substrate and display device
CN110034178B (en) * 2019-04-19 2022-12-06 京东方科技集团股份有限公司 Thin film transistor, preparation method thereof, array substrate and display device

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