KR20140075040A - Organic light emitting display device and method for driving theteof - Google Patents

Abstract

Disclosed is an organic light emitting display device capable of displaying an image of uniform brightness by compensating deterioration of an organic light emitting diode. The organic light emitting display device according to the present invention comprises: a display panel including multiple unit pixels consisting of multiple subpixels which have organic light emitting diodes emitted by a data current based on a data voltage; a memory having n number of storing areas which are spatially divided; a deterioration compensation unit to group adjacent m number of unit pixels to multiple pixel groups, sample image data to be supplied to a single subpixel in every unit pixel of each pixel group, accumulate the image data in a frame unit to be stored in different storing areas of the memory, and modulate, in the frame unit, the image data to be supplied to the subpixels of each pixel group based on the accumulation data stored in the different storing areas of the memory; and a panel driving unit to convert, to a data voltage, image modulation data of each subpixel which is modulated by the deterioration compensation unit and supply the data voltage to the corresponding subpixel.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display and a driving method thereof, and more particularly, to an organic light emitting display capable of compensating for deterioration of an organic light emitting diode and a driving method thereof.

2. Description of the Related Art In recent years, importance of a flat panel display device has increased with the advent of multimedia. In response to this, flat panel display devices such as liquid crystal display devices, plasma display devices, and organic light emitting display devices have been commercialized. Among such flat panel display devices, organic light emitting display devices have attracted attention as a next generation flat panel display device because they have a high response speed, low power consumption, and self light emission, so that there is no problem in viewing angle.

A general organic light emitting display includes a display panel including a plurality of pixels and a panel driver for emitting each pixel. Here, each pixel is formed in a pixel region defined by the intersection of a plurality of data lines and a plurality of gate lines.

Each of these pixels includes a switching transistor Tsw, a driving transistor Tdr, a capacitor Cst, and a light emitting element OLED, as shown in Fig.

The switching transistor Tsw is switched in accordance with the gate signal GS supplied to the gate line GL to supply the data voltage Vdata supplied to the data line DL to the driving transistor Tdr.

The driving transistor Tdr is switched according to the data voltage Vdata supplied from the switching transistor Tsw and controls the data current Ioled flowing to the light emitting element OLED by the driving voltage VDD.

The capacitor Cst is connected between the gate terminal and the source terminal of the driving transistor Tdr to store a voltage corresponding to the data voltage Vdata supplied to the gate terminal of the driving transistor Tdr, Tdr).

The light emitting device OLED is electrically connected between the source terminal of the driving transistor Tdr and the cathode electrode CE to which the cathode voltage VSS is applied and is turned on by the data current Ioled supplied from the driving transistor Tdr do.

Each pixel of the general organic light emitting display device controls the size of the data current Ioled flowing to the light emitting element OLED by the driving voltage VDD by switching the driving transistor Tdr according to the data voltage Vdata So that a predetermined image is displayed by causing the light emitting device OLED to emit light.

2 is a graph showing luminance characteristics of a general organic light emitting device.

As can be seen from FIG. 2, in general, as the driving time of the organic light emitting diode increases, the degradation rate is accelerated and the luminance characteristic is gradually decreased.

Therefore, in a general organic light emitting display device, there is a problem that an image of uniform luminance can not be displayed due to deterioration of the organic light emitting device OLED.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide an organic light emitting display device and a method of driving the same, which can display an image with uniform luminance by compensating for deterioration of the organic light emitting device.

According to an aspect of the present invention, there is provided an organic light emitting diode display comprising: a display panel including a plurality of unit pixels including a plurality of sub-pixels each having an organic light emitting element emitting light by a data current based on a data voltage; A memory having n storage areas spatially divided; Grouping adjacent m unit pixels into a plurality of pixel groups, sampling image data to be supplied to one sub-pixel for each unit pixel of each of the pixel groups, accumulating them in units of frames, and storing them in different storage areas of the memory A deterioration compensation unit for modulating image data to be supplied to the sub-pixels of each pixel group on a frame-by-frame basis based on accumulated data stored in different storage areas of the memory; And a panel driver for converting the video modulation data of each of the sub-pixels modulated by the deterioration compensating unit into the data voltage and supplying the data voltage to the corresponding sub-pixel.

According to an aspect of the present invention, there is provided a method of driving an organic light emitting diode display, including a plurality of pixel groups each including a plurality of sub-pixels each having an organic light emitting element emitting light by a data current based on a data voltage, Grouping (A); The image data to be supplied to one sub-pixel for each unit pixel of each pixel group is sampled and accumulated in units of frames and stored in different storage areas allocated to the memory, and cumulative data stored in different storage areas of the memory (B) modulating, on a frame-by-frame basis, image data to be supplied to sub-pixels of each pixel group based on the frame; And converting the video modulated data of each modulated sub-pixel into the data voltage and supplying the converted data voltage to the corresponding sub-pixel.

According to the organic light emitting display device and the driving method of the present invention, image data of each of a plurality of unit pixels included in each pixel group is cumulatively stored in different areas of the memory while accumulating data accumulated in different areas of the memory The compensation gain value of each pixel group is generated on a frame basis and is reflected on the image data to compensate the deterioration of the organic light emitting element to display an image of uniform luminance and reduce the number of memories, Similar effects to the interpolation method can minimize image degradation due to data sampling.

FIG. 1 is a view for explaining a pixel structure of a general organic light emitting display device.
2 is a graph showing luminance characteristics of a general organic light emitting device.
3 is a view for explaining an organic light emitting display according to an embodiment of the present invention.
4 is a block diagram for explaining a deterioration compensating unit according to an embodiment shown in FIG.
5 is a diagram for explaining a method of sampling and storing data according to the present invention.
6 is a waveform diagram for explaining the read and write operations of the memory shown in FIG.
FIGS. 7 to 10 are diagrams for explaining a method of generating the compensation gain value generated by the gain value generator shown in FIG.

The meaning of the terms described herein should be understood as follows.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms.

It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one.

Hereinafter, preferred embodiments of the organic light emitting diode display and the driving method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a view for explaining an organic light emitting display according to an embodiment of the present invention.

3, the OLED display includes a display panel 110, a memory 120, a deterioration compensating unit 130, and a panel driver 140. Referring to FIG.

The display panel 110 includes a plurality of sub-pixels SP. The plurality of sub pixels SP are formed in a pixel region defined by a plurality of gate lines GL, a plurality of data lines DL, and a plurality of data lines DL which intersect with each other. A plurality of driving voltage lines PL1 are formed on the display panel 110 in parallel with the plurality of data lines DL and supplied with the driving voltage from the panel driving unit 140. [

Each of the plurality of sub-pixels SP may be any one of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. One unit pixel for displaying one image may include an adjacent red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, or may include a red pixel, a green pixel, and a blue pixel. Hereinafter, it is assumed that one unit pixel is composed of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

Each of the plurality of sub-pixels SP includes an organic light emitting diode OLED and a pixel circuit PC.

The organic light emitting diode OLED is connected between the pixel circuit PC and the second power supply line PL2 and emits a predetermined color light by emitting light in proportion to the amount of data current supplied from the pixel circuit PC do. The organic light emitting diode OLED includes an anode electrode (or a pixel electrode) connected to the pixel circuit PC, a cathode electrode (or a reflective electrode) connected to the second driving power supply line PL2, And a light emitting cell formed between the cathode electrode and the cathode electrode and emitting light of any one of red, green, blue, and white. Here, the light emitting cell may have a structure of a hole transporting layer / an organic light emitting layer / an electron transporting layer or a structure of a hole injecting layer / a hole transporting layer / an organic light emitting layer / an electron transporting layer / an electron injecting layer. Further, the light emitting cell may further include a functional layer for improving the luminous efficiency and / or lifetime of the organic light emitting layer.

The pixel circuit PC responds to the gate signal GS of the gate-on voltage level supplied from the panel driver 140 to the gate line GL and supplies the data voltage Vdd supplied from the panel driver 140 to the data line DL (Vdata) to the organic light emitting diode OLED. To this end, the pixel circuit PC comprises a switching transistor, a driving transistor, and at least one capacitor formed on a substrate by a thin film transistor forming process. Since the pixel circuit PC is the same as the conventional pixel shown in FIG. 1, the description thereof will be omitted.

The memory 120 has n storage areas allocated to be spatially separated. In the memory 120, image data sampled from image data to be supplied to each sub-pixel SP of the display panel 110 is accumulated and stored.

The degradation compensation unit 130 groups adjacent m unit pixels into a plurality of pixel groups and samples image data Idata to be supplied to one subpixel SP for each unit pixel of each pixel group, (Idata) to be supplied to the sub-pixels (SP) of each pixel group based on accumulated data stored in different storage areas of the memory 120, ) On a frame-by-frame basis to generate video modulation data (Mdata).

The panel driver 140 generates a gate control signal GCS and a data control signal DCS based on the input timing synchronization signal TSS and generates a gate signal GS according to the gate control signal GCS And sequentially converts the video modulation data Mdata supplied from the deterioration compensating unit 140 into a data voltage Vdata in accordance with a data control signal DCS to generate a data line DL, . The panel driver 140 includes a timing controller 142, a gate driving circuit 144, and a data driving circuit 146.

The timing control unit 142 controls the driving timing of each of the gate driving circuit unit 144 and the data driving circuit unit 146 according to a timing synchronization signal TSS input from an external system body (not shown) or a graphic card (not shown) . That is, the timing control unit 142 generates a gate control signal based on a timing synchronization signal TSS such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock DCLK, (GCS) and a data control signal (DCS), controls the driving timing of the gate driving circuit part 144 through the gate control signal GCS, and controls the driving timing of the data driving circuit part 146 are controlled.

The timing control unit 142 arranges the red, green, blue, and white video modulation data Mdata supplied from the deterioration compensation unit 140 so as to be suitable for the pixel arrangement structure of the display panel 110, And supplies the aligned data (DATA) to the data driving circuit portion 146 based on a predetermined interface method.

Meanwhile, the timing controller 142 may include the deterioration compensator 120. In this case, the deterioration compensating unit 120 may be embedded in the timing control unit 142, and in this case, the deterioration compensating unit 120 may be embedded in a program or logic form.

The gate driving circuit 144 generates a gate signal GS corresponding to a display order of an image based on the gate control signal GCS supplied from the timing controller 142 and supplies the generated gate signal GS to the gate line GL . The gate driving circuit 144 may be formed in a form of a plurality of integrated circuits or may be formed directly on the substrate of the display panel 110 together with the transistor forming process of each sub pixel P, (GL), respectively.

The data driving circuit 146 receives the data DATA and the data control signal DCS from the timing controller 142 and receives a plurality of reference gamma voltages from an external reference gamma voltage supply unit. The data driving circuit 146 converts the alignment data DATA to an analog data voltage Vdata using a plurality of reference gamma voltages in accordance with the data control signal DCS, ) To the data line DL of the corresponding sub-pixel. The data driving circuit 146 may be formed in a plurality of integrated circuits (IC), and may be connected to one side and / or both sides of the data line DL.

FIG. 4 is a block diagram for explaining a deterioration compensating unit according to an embodiment shown in FIG. 3, and FIG. 5 is a diagram for explaining a method of sampling and storing data according to the present invention.

First, in the deterioration compensating unit 130 according to an embodiment, four-color image data including red image data, green image data, blue image data, and white image data may be supplied in series or in parallel on a unit pixel basis. Here, the 4-color image data is converted from red image data, green image data, and blue image data by a data format conversion unit (not shown), and the data format conversion unit converts red image data, , White image data is extracted based on blue image data, and the extracted white image data is reflected on red image data, green image data, and blue image data to generate the 4-color image data.

The deterioration compensator 130 groups the adjacent m unit pixels formed in the display panel 110 into a plurality of pixel groups and supplies the accumulated pixel data to the unit pixels in each of the m pixels in each pixel group. And compensates for the degradation of the organic light emitting device OLED of each sub-pixel SP by applying different compensation gain values to each pixel group over m frames. Accordingly, in the following description, as shown in Fig. 5, the first to fourth pixel groups PG1 to PG4 adjacent to each other in the up, down, left, and right directions are taken as an example, And PG4 are first to fourth unit pixels disposed in a 2x2 form adjacent to the upper, lower, left, and right sides.

4 and 5, the deterioration compensating unit 130 according to an embodiment includes a data sampling unit 131, a data accumulating unit 133, a memory address controlling unit 135, a compensation gain value generating unit 137, And a data modulation unit 139. [

The data sampling unit 131 groups the 16 unit pixels formed in the display panel 110 into first to fourth pixel groups PG1 to PG4 each having four unit pixels, (A, B, C, D) of the first to fourth unit pixels from the image data (Idata) of each sub-pixel included in the first to fourth unit pixels (PG1 to PG4). For example, the data sampling unit 131 may be configured to select one of red image data, green image data, blue image data, and white image data to be supplied to four sub-pixels included in the first to fourth unit pixels, The image data of the sub-pixels can be sampled by the sampling data (A, B, C, D) of the corresponding unit pixel.

The data accumulation unit 133 accumulates the sampling data A, B, C and D of the first to fourth unit pixels for each of the pixel groups PG1 to PG4 sampled by the data sampling unit 131, And stores them in the first to fourth storage areas S1 to S4 of the memory 120. [

Specifically, the data accumulation unit 133 accumulates the sampling data (A, B, C) of the first to fourth unit pixels sampled by the data sampling unit 131 for each pixel group PG1 to PG4 (D) of the memory 120 allocated in each of the storage areas S1 to S4 of the memory 120. The data sampled by the data sampling unit 131 is stored in the storage areas S1 to S4, (A, B, C, and D) of the four unit pixels are added to the accumulated data of the first through fourth unit pixels that are read, and then the cumulative data of the first through fourth unit pixels (S1_A, S1_B, S1_C, S1_D), S2_A, S2_B, S2_C, S2_D, S3_A, S3_B, S3_C, S3_D, S4_A, S4_B, S4_C, S4_D) And stored in each of the areas S1 to S4. That is, the data accumulation unit 133 accumulates accumulated data in each of the storage areas S1 through S4 of the memory 120 allocated to each of the plurality of unit pixels included in each of the pixel groups PG1 through PG4 during the current frame, (A, B, C, and D) of each unit pixel are added to the cumulative data of the corresponding unit pixel and stored in the storage area of the corresponding memory 120 (S1 to S4).

6, the data accumulation unit 133 accumulates the unit pixels in the memory 120 in the active period H in which the data enable signal DE is high, And stores the cumulative data added to the blank section L in which the data enable signal DE is low in the corresponding storage areas S1 to S4 of the memory 120 . For example, in the first pixel group PG1, the data accumulation unit 133 may accumulate the data of the first pixel group PG1 during the active period H of the data enable signal DE, (S1_A, S1_B, S1_C, and S1_D) of the first to fourth unit pixels by summing the cumulative data up to the previous frame and the sampling data (A, B, C, D) and; The cumulative data S1_A, S1_B, S1_C and S1_D of the first to fourth unit pixels are stored in the first storage area S1 of the memory 120 during the blank interval H of the data enable signal DE, . In this way, the data accumulation unit 133 accumulates the cumulative data (first to fourth unit pixels) of the first to fourth unit pixels in accordance with the data enable signal DE for each of the second to fourth pixel groups PG2, PG3, (S2_A, S2_B, S2_C, and S2_D), S3_A, S3_B, S3_C and S3_D, S4_A, S4_B, S4_C and S4_D of the corresponding memory 120, , S3, and S4, respectively.

The memory address control unit 135 may accumulate the cumulative data S1_A, S1_B, S1_C, and S1_D of the first to fourth unit pixels of each of the pixel groups PG1 to PG4 generated by the data accumulating unit 133, S4 to S4 of the memory 120 in which each of the memory areas S2_A, S2_B, S2_C, S2_D, S3_A, S3_B, S3_C, S3_D, S4_A, S4_B, S4_C and S4_D is stored. That is, the memory address control unit 135 controls a read operation or a write operation of the memory 120, and the data accumulation unit 133 reads the data stored in the storage areas S1- S4) of the first to fourth unit pixels of each of the pixel groups PG1 to PG4 generated by the data accumulating unit 133, S4_B, S1_C, S1_D), S2_A, S2_B, S2_C, S2_D, S3_A, S3_B, S3_C, S3_D, S4_A, S4_B, S4_C, S4_D) To S4.

The compensation gain value generation unit 137 generates the compensation gain value by accumulating the first to fourth unit pixels for each pixel group PG1 to PG4 in the first to fourth storage areas S1, S2, S3, and S4 of the memory 120, S2_D, S2_D, S3_D, and S4_D) for each frame are connected to the data (S1_A, S2_A, S3_A, S4_A), S1_B, S2_B, S3_B, S4_B, S1_C, S2_C, S3_C, S4_C, (S1_A, S2_A, S3_A, S4_A), S1_B, S2_B, S3_B, S4_B, S1_C, S2_C, and S2_B of the first to fourth unit pixels for each of the readout pixel groups PG1 to PG4, (G1_A, G2_A, G3_A, G4_A), (G1_B, G2_B, G3_B, G4_b) for each of the pixel groups (PG1 to PG4) ), (G1_C, G2_C, G3_C, G4_C), (G1_D, G2_D, G3_D, G4_D)) for each frame. At this time, the compensation gain value generator 137 may be a lookup table mapped to correspond to the gray level value of the accumulated data.

For example, in the N frames, the compensation gain value generator 137 generates the compensation gain value of the first to fourth storage areas S1, S2, S3, and S4 of the memory 120, The cumulative data S1_A, S2_A, S3_A and S4_A of the first unit pixel for each of the pixel groups PG1 to PG4 is read from the first unit pixel PG1 to PG4, (G1_A, G2_A, G3_A, G4_A) for each of the pixel groups (PG1 to PG4) based on the accumulated data S1_A, S2_A, S3_A, and S4_A.

As shown in FIG. 8, the compensation gain value generator 137 of the N + 1 frame stores the first to fourth storage areas S1, S2, S3, and S4 of the memory 120, The cumulative data S1_B, S2_B, S3_B and S4_B of the second unit pixel for each of the pixel groups PG1 to PG4 is read from the first unit pixel PG1 to PG4, (G1_B, G2_B, G3_B, G4_B) for each of the pixel groups (PG1 to PG4) based on the accumulated data S1_B, S2_B, S3_B, and S4_B.

9, the compensation gain value generator 137 generates the compensation gain value in the first through fourth storage areas S1, S2, S3, and S4 of the memory 120, The cumulative data S1_C, S2_C, S3_C and S4_C of the third unit pixel for each of the pixel groups PG1 to PG4 is read from the third unit pixel PG1 to PG4, (G1_C, G2_C, G3_C, G4_C) for each of the pixel groups (PG1 to PG4) based on the cumulative data S1_C, S2_C, S3_C, and S4_C.

In the N + 3 frame, the compensation gain value generator 137 generates the compensation gain value of the first to fourth storage areas S1, S2, S3, and S4 of the memory 120, The cumulative data S1_D, S2_D, S3_D and S4_D of the fourth unit pixel for each of the pixel groups PG1 to PG4 are read from the first to fourth unit pixels PG1 to PG4, (G1_D, G2_D, G3_D, G4_D) for each of the pixel groups (PG1 to PG4) based on the cumulative data S1_D, S2_D, S3_D, and S4_D.

(G1_A, G3_A, G4_A), (G1_B, G2_B, G3_B, G4_b), (G1_C, G2_C) are calculated by the compensation gain value generator 137 for each of the pixel groups The data accumulation unit 133 accumulates the first to fourth unit pixels P 1 to P 4 for each of the pixel groups PG 1 to PG 4, as described above, during the generation of the first to fourth unit pixels PG 1 to PG 4, G 3 C, G 4 C, G 1 D, G 2 D, G 3 D, Is repeatedly performed on a frame-by-frame basis.

4, the data modulating unit 139 modulates the compensation gain values (G1_A, G2_A, G3_A, G4_A (G1_A, G2_A, ) Included in each of the input pixel groups (PG1 to PG4) based on (G1_B, G2_B, G3_B, G4_b), (G1_C, G2_C, G3_C, G4_C), (G1_D, G2_D, G3_D, G4_D) And supplies the generated image modulation data Mdata to the panel driving unit 140, that is, the timing control unit 142, by modulating the image data Idata of the pixel by generating the image modulation data Mdata. G2_A, G3_A, G4_A), (G1_B, G2_B, G3_B, G4_b), (G1_C, G2_C, G3_C, and G4_C), (G1_D, G2_D, G3_D, G4_D)) to generate the image modulation data (Mdata).

6, the display panel 110 has a resolution of 1920 (vertical lines) x 1080 (horizontal lines) x 4 (R / G / B / W) The memory 120 must have a capacity of 1920 (Vertical lines) × 1080 (horizontal lines) × 4 (R / G / B / W) × 32 bits = 265,420,800 bits, 120 < / RTI >

When the display panel 110 having the above resolution is driven according to the vertical synchronizing signal of 120 Hz, the dot clock DCLK has a frequency of 75 MHz, and one active period H of the data enable signal DE, The number of generated dot clocks DCLK is 480. Accordingly, the amount of data to be processed during one horizontal period is 480 (DCLK) x 4 (Port) x 4 (R / G / B / W) x 32 (bits) = 245,760 (bits).

The memory 120 operates at 300 MHz and has a number of input / output pins of 16 (bits), performs a read operation (RP) on the active section H of the data enable signal DE, The number of clocks clk of the memory 120 used in the read operation RP is set to be equal to the number of clocks CLK in the blank period L of the enable signal DE, The amount of data that the memory 120 can handle in the read operation RP is 1920 (clk) x 16 (dLRAM), which is four times faster than the DCLK bits) 占 2 (Dual rate) = 61,440 (bits). Accordingly, if a large number of memories are required to generate cumulative data for all the subpixels of the display panel 110, if the number of memories is reduced in order to reduce the cost burden due to an increase in the number of memories, There is a limit to data bandwidth.

However, the deterioration compensating unit 140 according to the present invention samples the image data of one sub-pixel per unit pixel composed of four sub-pixels, that is, 1/4, and stores the entire space of the memory 120 into a plurality of Data can be processed during a read operation of the memory 120 while the number of the memories 120 is reduced because the sampling data is divided into different areas and stored in different storage areas. Since the image data is modulated using the cumulative data stored in the area, image degradation due to data sampling can be minimized through an effect similar to the frame interpolation method.

As described above, the organic light emitting diode display according to the embodiment of the present invention uses a sampling method of sampling only one sub-pixel among a plurality of sub-pixels constituting a unit pixel, One pixel of image data is sampled and accumulated in different areas of the memory 120, and a compensation gain value of each pixel group is generated on a frame basis on the basis of accumulated data stored in different storage areas of the memory 120 Thereby modulating the image data of the sub-pixels included in each pixel group, thereby compensating for the deterioration of the organic light emitting elements included in each sub-pixel, thereby displaying an image of uniform luminance.

Meanwhile, in the OLED display according to the above-described embodiment of the present invention, each pixel group is composed of four unit pixels adjacent to each other in the up, down, left, and right directions. However, the present invention is not limited thereto, And may be composed of a plurality of adjacent unit pixels. In addition, the memory 120 has a plurality of storage areas spatially separated to correspond to the number of pixel groups.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

110: display panel 120: memory
130: deterioration compensating unit 131: data sampling unit
133: Data accumulation unit 135: Memory address control unit
137: compensation gain value generation section 139: data modulation section
140: panel driver 142: timing controller
144: Gate driving circuit part 146: Data driving circuit part

Claims (9)

A display panel including a plurality of unit pixels constituted by a plurality of sub-pixels each having an organic light emitting element emitting light by a data current based on a data voltage;
A memory having n storage areas spatially divided;
Grouping adjacent m unit pixels into a plurality of pixel groups, sampling image data to be supplied to one sub-pixel for each unit pixel of each of the pixel groups, accumulating them in units of frames, and storing them in different storage areas of the memory A deterioration compensation unit for modulating image data to be supplied to the sub-pixels of each pixel group on a frame-by-frame basis based on accumulated data stored in different storage areas of the memory; And
And a panel driver for converting the video modulation data of each sub-pixel modulated by the deterioration compensating unit to the data voltage and supplying the data voltage to the corresponding sub-pixel. The method according to claim 1,
Wherein the deterioration compensator comprises:
A data sampling unit for sampling one of the image data of the inputted image data of each sub-pixel into the sampling data of the unit pixel;
A data accumulation unit accumulating sampling data of each of the sampled unit pixels on a frame-by-frame basis and storing the sampled data in different storage areas of the memory;
A compensation gain value generation unit for reading the accumulated data of the unit pixels in the storage area and generating a gain value of each pixel group based on the accumulated data of the read unit pixels; And
And a data modulator for modulating image data of each sub-pixel included in each pixel group according to a gain value of each of the pixel groups. 3. The method of claim 2,
Wherein the data accumulator comprises:
Reading cumulative data of the unit pixel in a corresponding storage area of the memory in which the image data of the unit pixel to be sampled is stored,
Wherein the sampling data of the sampled unit pixel is added to the accumulated data of the read unit pixel and stored in the corresponding storage area of the memory. The method of claim 3,
Wherein the data accumulator comprises:
Reading accumulated data of the unit pixel from the memory in an active period of the data enable signal,
Wherein the cumulative data is stored in a corresponding storage area of the memory in a blank interval of the data enable signal. 5. The method according to any one of claims 2 to 4,
Wherein the degradation compensation unit further comprises a memory address control unit for designating a storage area of the memory in which cumulative data of the unit pixels is stored. (A) grouping unit pixels constituted by a plurality of sub-pixels having an organic light emitting element emitting light by a data current based on a data voltage into a plurality of pixel groups;
The image data to be supplied to one sub-pixel for each unit pixel of each pixel group is sampled and accumulated in units of frames and stored in different storage areas allocated to the memory, and cumulative data stored in different storage areas of the memory (B) modulating, on a frame-by-frame basis, image data to be supplied to sub-pixels of each pixel group based on the frame; And
(C) converting the modulated data of the modulated sub-pixels into the data voltage and supplying the converted data voltage to the corresponding sub-pixel. The method according to claim 6,
The step (B)
Sampling (B1) any one of the video data of the input sub-pixel with the sampling data of the unit pixel;
Accumulating sampling data of each of the sampled unit pixels on a frame-by-frame basis and storing the sampled data in different storage areas of the memory;
A step (B3) of reading accumulated data of the unit pixel in the storage area and generating a gain value of each pixel group based on accumulated data of the read unit pixel; And
And modulating (B4) image data of each sub-pixel included in each of the pixel groups according to a gain value of each of the pixel groups. 8. The method of claim 7,
The step (B2)
Reading cumulative data of the unit pixel in a corresponding storage area of the memory in which the image data of the unit pixel to be sampled is stored,
Wherein the sampling data of the sampled unit pixel is added to the accumulated data of the read unit pixel and stored in the corresponding storage area of the memory. 9. The method of claim 8,
The step (B2)
Reading accumulated data of the unit pixel from the memory in an active period of the data enable signal,
Wherein the cumulative data is stored in a corresponding storage area of the memory in a blank interval of the data enable signal.

Images