KR20140064016A - Memory system - Google Patents

Memory system Download PDF

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Publication number
KR20140064016A
KR20140064016A KR1020120130864A KR20120130864A KR20140064016A KR 20140064016 A KR20140064016 A KR 20140064016A KR 1020120130864 A KR1020120130864 A KR 1020120130864A KR 20120130864 A KR20120130864 A KR 20120130864A KR 20140064016 A KR20140064016 A KR 20140064016A
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KR
South Korea
Prior art keywords
page
memory
control signal
page control
requests
Prior art date
Application number
KR1020120130864A
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Korean (ko)
Inventor
권용기
이형동
문영석
양형균
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120130864A priority Critical patent/KR20140064016A/en
Priority to US13/844,920 priority patent/US9098389B2/en
Priority to CN201310192573.4A priority patent/CN103823773B/en
Publication of KR20140064016A publication Critical patent/KR20140064016A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory system comprises a memory controller and a memory device. The memory controller generates a page control signal based on the collection whereby a request inputted from a processor is realigned. The memory device includes a memory array including a plurality of memory cells and sets a page size of the memory array based on the page control signal.

Description

[0001] MEMORY SYSTEM [0002]

The present invention relates to a semiconductor memory, and more particularly, to a memory system including a semiconductor memory and a method of operating the same.

To improve the communication speed between a processor and a memory device, such as a CPU or a GPU, a memory controller or interface chip is used. In addition, a semiconductor device of a package type (System In Package) which is a system for packaging a memory device and a memory controller or an interface chip together is being developed.

On the other hand, the memory device has a memory bank composed of a plurality of memory cells. The memory cells of the memory bank can be accessed via word lines and bit lines, typically a memory device has a unit called a page. In a memory device, the page can be defined as the number of memory cells accessible in one active operation. The memory bank of the memory device can generally be referred to as the number of bit lines connected to one word line, since only one word line can be activated in one active operation.

Memory devices, especially DRAMs, generally have a fixed page size. Having a fixed page means that the time for accessing the word line and the time for precharging are fixed. Therefore, accessing a page of a fixed size irrespective of the characteristics of data such as the locality of the data, the size of the data, or the like causes unnecessary loss.

Embodiments of the present invention provide a memory system capable of varying the page size of a memory array that can be accessed according to data characteristics.

Embodiments of the present invention also provide a memory system capable of selectively accessing memory banks having different page sizes according to data characteristics.

A memory system according to an embodiment of the present invention includes a memory controller for generating a page control signal based on the number of times a request input from a processor is rearranged; And a memory array including a plurality of memory cells, the memory array configured to set a page size of the memory array based on the page control signal.

According to another aspect of the present invention, there is provided a memory system including: a memory controller that generates a page control signal based on a number of times a request input from a processor is rearranged; And a memory device including a plurality of memory banks having different page sizes, and activating one of the plurality of memory banks based on the page control signal.

According to the present invention, a page size of a memory array can be variably set based on data characteristics, or a memory bank having various page sizes can be selectively accessed to increase an effective band width and reduce power consumption.

1 is a diagram illustrating a configuration of a memory system according to an embodiment of the present invention;
FIG. 2 is a block diagram schematically illustrating the configuration of an embodiment of the memory controller of FIG. 1;
3 is a diagram schematically showing the configuration of an embodiment of the page control signal generator of FIG. 2,
FIG. 4 is a diagram illustrating the configuration of an embodiment of the memory device of FIG. 1;
Fig. 5 is a diagram showing the configuration of another embodiment of the memory device of Fig. 1;

1 is a diagram showing a configuration of a memory system 1 according to an embodiment of the present invention. In FIG. 1, the memory system 1 includes a memory controller 100 and a memory device 200. The memory device 200 may include, but is not limited to, a non-volatile memory device such as a phase change memory, a resistive memory, a magnetic memory, a flash memory, etc., .

The memory controller 100 relays communications between a processor (not shown) and the memory device 200. That is, the memory controller 100 receives various signals and data from the processor, controls the memory device 200, and provides data and signals output from the memory device 200 to the processor.

The memory controller 100 receives a command signal CMD, an address signal ADD <0: n> and data DATA <0: n> for controlling the memory device 200 by receiving request, 0: m &gt;) and a clock signal (CLK). Also, the memory controller 100 generates a page control signal (PAGE <0: k>) to control the memory device 200. The memory controller 100 generates the page control signal PAGE &lt; 0: k &gt; based on the number of times the requests input from the processor are rearranged. The page control signal PAGE &lt; 0: k &gt; may have a plurality of bits, and may be a signal whose logical value changes according to the number of re-ordering of the request.

In FIG. 1, the memory device 200 includes a memory array 210 that includes a plurality of memory cells in which data is stored. In one embodiment, the memory device 200 may vary the page size of the memory array 210 based on the page control signals PAGE < 0: k >. In the memory system 1, the page size of the memory array 210 can be set to be larger as the number of times the requests are rearranged, and the page size of the memory array 210 becomes smaller as the number of times of re- Can be set. In the memory device 200, the page may generally refer to the number of memory cells accessible with one active operation. That is, a memory device such as a DRAM includes a memory cell array electrically connected to a word line and a bit line, which may refer to the number of bit lines or columns connected to the word line.

In another embodiment, the memory device 200 may include a plurality of memory banks having different page sizes. The plurality of memory banks will be described later in more detail. The memory device 200 may activate one of the plurality of memory banks based on the page control signal PAGE < 0: k >. The memory device 200 can activate a memory bank having a large page size among the plurality of memory banks as the number of times of the re-ordering of the requests increases, and the smaller the number of times the requests are rearranged, A small memory bank can be activated.

2 is a block diagram schematically illustrating the configuration of an embodiment of the memory controller 100 of FIG. 2, the memory controller 100 includes a request buffer 110, a write data queue 120, a read data queue 130, an address mapping unit 140, an arbiter 150, a command generation unit 160, And a page control signal generation unit 170. [ The request buffer 110, the write data queue 120, and the read data queue 130 store and buffer the requests and data input from the processor. The request includes a write request and a read request, address information, and the like for instructing the operation of the memory device 200. The address mapping unit 140 generates an address signal ADD <0: n> input from the output of the request buffer 110 to the memory device 200. The command generation unit 160 generates various command signals CMD to be input to the memory device 200 based on the request.

The arbiter 150 plays a pivotal role in relaying communication between the processor and the memory device 200. The arbiter 150 includes a rearrangement unit 151 for sequentially receiving a plurality of requests from the processor through the request buffer 110 and efficiently rearranging the requests. The reordering unit 151 sequentially receives a plurality of requests input from the processor, and reorders the requests. In order to improve the operation efficiency of the memory device 200, the re-ordering of the requests is performed so that, when the input request is difficult to be executed immediately, the input request later to be executed can be executed first. That is, when an inevitable time delay occurs when the requests are executed in order, the requests can be executed in the order of rearrangement by rearranging the order of the requests without sequentially executing the requests sequentially. As described above, the request reordering operation can efficiently improve the performance of the multi-rank memory device including a plurality of ranks.

If the number of re-ordering of the request is large, the page hit rate is determined to be high, and it is determined that the locality of the page is good. On the other hand, when the number of times the request is rearranged is small, the page hit rate is determined to be a random request having a low rate. If the locality of the page is good, the larger the number of memory cells that can be accessed at a time, the better. In general, it takes a considerable amount of time to activate and precharge one word line. Thus, when a particular word line is active, collecting and performing the requests related to columns accessible to the word line at a time can improve the operating speed of the memory device 200. [ In order to improve the operation efficiency, the reordering unit 151 of the memory controller 100 rearranges the requests input from the processor. Therefore, when the number of re-ordering of the requests is large, there is an advantage that the number of bit lines or columns connected to one word line increases. In other words, if the number of times the requests are rearranged is large, it is advantageous to activate one page having a large page size and execute a re-ordered request by activating and deactivating a plurality of pages having a small page size. Conversely, it is advantageous that the number of bit lines or columns connected to one word line is smaller because it is inefficient to repeat the operation of activating and deactivating a large page when the number of times of re-arrangement of the requests is small. That is, it is advantageous that the size of the page is small if the number of times the request is rearranged is small. Accordingly, the memory controller 100 may set the page size of the memory array 210 to a large value or activate the memory bank having a large page size when the page hit rate is high, Signal (PAGE < 0: k >). In contrast, when the page hit rate is low, the page control signal (PAGE <0: k>) is set so that the memory device 200 can set a page of the memory array 210 to a small size or activate a memory bank having a small page size, ).

In FIG. 2, the page control signal generator 170 is electrically connected to the reorder unit 151. The page control signal generator 170 generates the plurality of chip select signals PAGE <0: k> based on the re-ordering count information RCNT generated by the reordering unit 151. The page control signal generator 170 may generate the page control signal PAGE < 0: k > by comparing the number of rearrangements with a threshold value. For example, when the number of rearrangements is high, the memory device 200 may set the page size of the memory array 210 to a large value or the page control with a high logic value The memory device 200 may generate a signal PAGE < 0: k >, and when the number of times of the reallocation is small, the memory device 200 sets the page size of the memory array 210 small, The page control signal PAGE < 0: k > having a low logic value can be generated.

3 is a block diagram schematically showing the configuration of an embodiment of the page control signal generator 170 of FIG. In FIG. 3, the page control signal generator 170 includes a threshold register 171 and a comparator 172. The threshold register 171 stores one or more threshold values TH <0: 1>. The threshold value (TH < 0: l >) stores information on the number of times of rearrangement that can be a reference for efficiently selecting a page size. The threshold value (TH < 0: l >) may be a plurality of values to provide a criterion for distinguishing between a large number of rearrangements and a small number of rearrangements.

The comparison unit 172 receives information (RCNT) about the number of times the request is reordered from the reordering unit 151. [ Also, the comparing unit 172 receives information on the threshold value TH <0: 1> from the threshold value register 171. The comparator 172 compares the reordering count information RCNT with the threshold value TH <0: 1> to generate the page control signal PAGE <0: k>. The reordering count information RCNT may be generated by counting the occurrence of an operation in which the request is rearranged.

The comparator 172 generates the page control signal PAGE <0: k> having a high logic value when the reordering count information RCNT exceeds the threshold TH <0>, for example. (PAGE <0: k>) having a low logic value when the reordering count information RCNT does not exceed the threshold value TH <0>.

Also, when the threshold register 171 provides a plurality of threshold values, i.e., first and second threshold values TH < 0: 1 >, the comparator 172 may operate as follows. The comparator 172 generates the page control signal PAGE <0: k> to have the highest logical value when the reordering count information RCNT exceeds the first threshold TH <1> can do. The comparison unit 172 may compare the page control signal PAGE <0: k> having an intermediate logical value if the reordering count information is between the first threshold value TH <0: 1> Lt; / RTI &gt; If the reordering count information RCNT does not exceed the second threshold TH <0>, the comparator 172 outputs the page control signal PAGE <0: k> having the lowest logical value, Lt; / RTI &gt;

FIG. 4 is a diagram schematically illustrating the configuration of one embodiment of the memory device 200 of FIG. In FIG. 4, the memory device 200 includes a memory array 210 and a page setup unit 220. The memory array 210 includes a plurality of memory cells, and the page size can be varied. The page setting unit 220 generates a page setting signal PAGESET <0: 2> to set the page size of the memory array 210 based on the page control signal PAGE <0: k> . The page setup signals PAGESET < 0: 2 > may be provided to a row decoder (not shown) of the memory array 210 and used to set the page size.

In FIG. 4, the page setting unit 220 includes a decoder 221 and a setting signal generating unit 222. The decoder 221 receives the page control signal PAGE <0: k> from the memory controller 100 and decodes the page control signal PAGE <0: k>. The setting signal generating unit 222 receives the output of the decoding unit 221 and generates the page setting signal PAGESET <0: 2>. 4, the memory array 210 may have three different page sizes, and the page setting signals PAGESET < 0: 2 > are illustrated as being three, but the present invention is not limited thereto. The number of the page setting signals generated by the decoder 221 and the setting signal generating unit 222 can be increased.

For example, if a first page setup signal PAGESET < 0 > is generated based on the page control signal PAGE < 0: k >, the memory array 210 may be set to have a page size of 2T The memory array 210 can be set to have a page size of T when the second page setting signal PAGESET <1> is generated and when the third page setting signal PAGESET < (210) may be set to have a page size of T / 2. That is, the memory array 210 may have different page sizes according to the first to third page setting signals PAGESET <0: 2>, and accordingly, the number of memory cells accessible in one active operation .

5 is a schematic illustration of another embodiment of the memory device 200 of FIG. In FIG. 5, the memory device 200 includes a plurality of memory banks each having a different page size. The memory device 200 in FIG. 4 has a memory array 210 in which the page size can be changed, and the memory device 200 in FIG. 5 has a memory bank in which the page size is already determined. The memory device includes, for example, a first memory bank (BANK0, BANK1) having the largest page size, a second memory bank (BANK2) having an intermediate page size, and a third memory bank (BANK3) . &Lt; / RTI &gt; However, it is not intended to limit the size of the page and the number of memory banks.

The memory device 200 also includes a bank selector 320. The bank selection unit 320 has substantially the same configuration as the page setting unit 220 of FIG. The bank selector 320 generates a bank selection signal BANKSEL <0: 2> for activating one of the plurality of memory banks based on the page control signal PAGE <0: k>. The bank selection signals BANKSEL <0: 2> may be provided to the row decoders X-DEC of the respective memory banks BANK0, BANK1, BANK2, and BANK3.

The bank selection unit 320 includes a decoder 321 and a selection signal generation unit 322. The decoder 321 receives the page control signal PAGE <0: k> from the memory controller 100 and decodes the page control signal PAGE <0: k>. The selection signal generator 322 receives the output of the decoding unit 321 and generates the bank selection signals BANKSEL <0: 2>. FIG. 5 illustrates that there are three bank selection signals (BANKSEL <0: 2>).

When the first bank select signal BANKSEL <0> is generated based on the page control signal PAGE <0: k>, the memory device 200 generates a first memory bank BANK0 , BANK1). Here, the first memory bank may include both the 0th bank (BANK0) and the 1st bank (BANK1). In the embodiment of the present invention, the 0th bank (BANK0) and the 1st bank (BANK1) are physically separated memory banks, but they can be logically grouped into one memory bank. That is, the first memory bank has a page size of length that traverses two physical memory banks. In an embodiment of the present invention, a memory bank having physically the same size is illustrated to illustrate that the memory device 200 may be implemented as a general memory device. However, it is not limited thereto, and the memory device may have a memory bank having a physically different size.

When the second bank selection signal BANKSEL <1> is generated based on the page control signal PAGE <0: k>, the memory device 200 generates a second memory bank BANK2 having an intermediate page size, . The second memory bank (BANK2) has a page size of a length across one physical memory bank. When the third bank selection signal BANKSEL < 2 > is generated based on the page control signal PAGE < 0: k >, the memory device 200 generates a third memory bank (BANK3). The third memory bank (BANK3) has a page size that is a length across one half of one physical memory bank.

A method of operating the memory system 1 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5 as follows. The memory controller 100 relays communication between the processor and the memory device 200. The memory controller 100 generates a command signal CMD or the like based on a request input from the processor so that the memory device 200 can perform a read or write operation.

The memory controller 100 receives a plurality of requests sequentially input from the processor and rearranges the requests to efficiently control the memory device 200. [ The comparison unit 172 of the page control signal generation unit 170 counts the number of occurrences of the request reordering and compares the reordering count information RCNT with the threshold value TH <0: 1> And generates a page control signal (PAGE <0: k>). When the reordering count information RCNT exceeds the threshold value TH <0: 1>, the page setting unit 220 sets the page order of the memory array (eg, 210 are set to be large. On the contrary, if the reordering count information RCNT does not exceed the threshold value TH <0: 1>, the page setting unit 220 sets the page reordering count RCNT to the memory array The page size of the page 210 is set small.

Similarly, when the reordering count information RCNT exceeds the threshold value TH <0: 1>, the bank selector 320 selects a large page based on the page control signal PAGE <0: k> The memory bank having the size is selected. Conversely, when the reordering count information RCNT does not exceed the threshold value TH <0: 1>, a memory bank having a small page size is selected based on the page control signal PAGE <0: k>.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

1: memory system 100: memory controller
110: request buffer 120: write data queue
130: Read data queue 140: Address mapping unit
150: Arbiter 151:
160: command generation unit 170: page control signal generation unit
200: memory device 210: memory array
220: page setting unit 320: bank selection unit

Claims (12)

A memory controller for generating a page control signal based on the number of times the requests input from the processor are rearranged; And
A memory device including a memory array including a plurality of memory cells, the memory device configured to set a page size of the memory array based on the page control signal. The method according to claim 1,
Wherein the memory device sets a page size of the memory array to be larger as the number of times the requests are rearranged based on the page control signal and sets a page size of the memory array to be smaller as the number of times the requests are rearranged is smaller, system. The method according to claim 1,
Wherein the memory controller comprises: a reordering unit for sequentially receiving a plurality of requests from the processor and reordering the order of the plurality of requests; And
And a page control signal generator for generating the page control signal by comparing the number of times of re-arrangement of the reorder unit with a threshold value. The method of claim 3,
Wherein the page control signal generator comprises: a threshold register storing the threshold; And
And a comparator for comparing the reordering count information with the threshold value to generate the page control signal. The method according to claim 1,
Wherein the memory device comprises a page setting section for generating a page setting signal for setting a page size of the memory array in response to the page control signal. 6. The method of claim 5,
Wherein the page setting unit comprises: a decoding unit decoding the page control signal; And
Generating a page setup signal in response to an output of the decoding unit, and providing the page setup signal to a row decoder. A memory controller for generating a page control signal based on the number of times the requests input from the processor are rearranged; And
A memory device including a plurality of memory banks having different page sizes and activating one of the plurality of memory banks based on the page control signal. 8. The method of claim 7,
Wherein the memory device activates a memory bank having a large page size among the plurality of memory banks as the number of times of re-arrangement of the requests increases based on the page control signal, and, as the number of times of re- A memory system that activates a small memory bank. 8. The method of claim 7,
Wherein the memory controller comprises: a reordering unit for sequentially receiving a plurality of requests from the processor and reordering the order of the plurality of requests; And
And a page control signal generator for generating the page control signal by comparing the number of times of re-arrangement of the reorder unit with a threshold value. 10. The method of claim 9,
Wherein the page control signal generator comprises: a threshold register storing the threshold; And
And a comparator for comparing the reordering count information with the threshold value to generate the page control signal. 8. The method of claim 7,
Wherein the memory device comprises a bank selector for generating a bank select signal to activate one of the plurality of memory banks in response to the page control signal. 12. The method of claim 11,
Wherein the bank selector comprises: a decoding unit decoding the page control signal; And
Generating the bank selection signal in response to an output of the decoding unit, and providing the bank selection signal to a row decoder.
KR1020120130864A 2012-11-19 2012-11-19 Memory system KR20140064016A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020120130864A KR20140064016A (en) 2012-11-19 2012-11-19 Memory system
US13/844,920 US9098389B2 (en) 2012-11-19 2013-03-16 Memory system and operating method thereof
CN201310192573.4A CN103823773B (en) 2012-11-19 2013-05-22 Storage system and its operating method

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KR1020120130864A KR20140064016A (en) 2012-11-19 2012-11-19 Memory system

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