KR20140059987A - Method for manufacturing of phase change random access memory - Google Patents

Abstract

The present invention relates to a method for manufacturing a phase change memory device. According to the present invention, an etch buffer layer is coated before a phase change material is buried in a narrow trench. After that, a CMP process is performed to determine the upper linewidth of the etch buffer layer. And then, the etch buffer layer coated in the trench is removed. After that, the phase change material is buried in an empty space. Thereby, the upper linewidth of the phase change material can be freely controlled and the recess of the phase change material can be minimized.

Description

The present invention relates to a method for manufacturing a phase change memory device,

The present invention relates to a method of manufacturing a phase change memory device, and more particularly, to a method of manufacturing a phase change memory device capable of freely controlling an upper line width of a phase change material film.

As the information and communication field rapidly develops, there is an increasing demand for a next-generation semiconductor memory device capable of high-speed operation and having a large memory storage capacity.

The next-generation semiconductor memory device is developed by taking advantage of a volatile memory device such as a DRAM and a nonvolatile memory device such as a flash memory. The memory device includes a phase change random access memory (PCRAM), a resistive random access memory (RRAM) Transfer Torque Random Access Memory) or PoRAM (Polymer Random Access Memory).

In the above-mentioned next generation semiconductor memory devices, in particular, PCRAM using a phase change material, data storage is performed by using the resistance difference due to the crystal structure change of the phase change material film. As the phase change material, a chalcogenide compound (GST) composed of germanium (Ge), antimony (Sb) and tellurium (Te) may be used. Depending on the magnitude of the supplied current and the supply time The crystal structure is different.

That is, a high-current pulse is applied to the phase-change material for a short time to increase the temperature of the phase-change material to the vicinity of the melting point, and then quenched. On the other hand, when a relatively low-sized current pulse is applied for a long time to crystallize the phase change material at a crystallization temperature lower than the melting temperature, and then cooled, the heat-affected phase change material portion becomes a crystalline state having a low resistance set).

As described above, there is a characteristic in which the magnitude of the resistance varies depending on the crystal structure of the phase change material (the crystalline state has a small resistance and the amorphous state has a large resistance). By using the resistance difference, data of "1" or "0" It is programmed and erased.

On the other hand, in forming the phase change material layer using such a phase change material, the phase change material is buried in the narrow trench by the chemical vapor deposition method which is different from the planar cell type PCRAM in the confined cell type PCRAM. Then, a normal planarization process is performed to isolate the phase change material buried in the trench, thereby realizing the final phase change material film.

1A and 1B illustrate a conventional method of fabricating a confined cell type phase change memory device according to the prior art.

Referring to FIG. 1A, a lower electrode contact 102 is formed on a semiconductor substrate 100. Then, an interlayer insulating film 104 is deposited on the semiconductor substrate 100 on which the lower electrode contact 102 is formed.

A normal photolithography is performed on the interlayer insulating layer 104 to form a trench 106 exposing an upper surface of the lower electrode contact 102. Then, A phase change material 108 is deposited on the front surface of the semiconductor substrate 100. [

Referring to FIG. 1B, a conventional etch back process is performed on the phase change material 108. As a result, the phase change material 108 buried in the trench 106 is isolated to form the final phase change material film 108a.

At this time, a critical dimension (CD) of the top region of the phase change material layer 108a, that is, an upper linewidth, is determined by the time during which the etch back process proceeds. If the etching time is increased to reduce the upper linewidth, A recess is formed in the change material film 108a to cause interface separation in the top region in the subsequent process.

Conversely, if the etch time is reduced in order to minimize the recess of the phase change material layer 108a, the linewidth of the upper region relative to the lower region ("A") (refer to "B ") Is increased and the overlay margin in the subsequent process becomes insufficient.

It is an object of the present invention to provide a method of manufacturing a phase change memory device capable of freely controlling an upper line width without a recess of a phase change material film.

It is another object of the present invention to provide a method of manufacturing a phase change memory device capable of sufficiently ensuring an overlay margin between a phase change material film and an upper pattern.

According to another aspect of the present invention, there is provided a method of fabricating a phase change memory device, comprising: forming a lower electrode contact on a semiconductor substrate; Forming an interlayer insulating film having a first trench exposing the lower electrode contact on the semiconductor substrate; Applying an etch buffer layer over the front surface of the semiconductor substrate on which the first trench is formed; Performing a planarization process on the etch buffer layer to determine an upper line width of the first trench; Removing the etch buffer layer to form a second trench; Depositing a phase change material over the front side of the semiconductor substrate to fill the second trench; And etching the phase change material so that a phase change material exists only in the second trench to form a final phase change material film.

According to the present invention, the upper line width of the etching buffer film is determined by applying a first etching buffer film to the inside of a narrow trench and then performing a CMP process. Then, the etch buffer layer inside the trench is removed, and then the phase change material is applied secondarily and the etch-back process is performed to isolate the phase change material buried in the trench. Thus, the desired upper line width It becomes possible to form a phase change material film.

1A and 1B show a method of manufacturing a phase change memory device according to the prior art.
FIG. 2 illustrates a phase change memory device according to a preferred embodiment of the present invention.
3A and 3E illustrate a method of fabricating a phase change memory device according to a preferred embodiment of the present invention.

Hereinafter, a phase change memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the following drawings.

FIG. 2 illustrates a cross-sectional structure of a phase change memory device according to a preferred embodiment of the present invention.

Referring to FIG. 2, a lower electrode contact 202 is formed on a semiconductor substrate 200 on which a conventional access element is formed. A phase change material layer 212a is formed on the lower electrode contact 202 by filling the trench formed by partially etching the interlayer insulating layer 204 with a phase change material.

In forming the phase-change material layer 212a, a photoresist layer functioning as an etch buffer layer is deposited on the interlayer insulation layer 204, which is to be removed after being primarily etched. Then, the photosensitive film is subjected to a CMP process to control the upper line width of the photosensitive film to a desired size.

Here, the desired size refers to the upper line width of the phase change material film formed through the subsequent process.

Then, the photoresist film in the trench is removed by a strip process, and a phase change material is secondarily deposited inside the trench in which the photoresist film is removed. Then, an etch-back process is performed on the deposited phase change material to isolate the phase change material deposited in the trench, thereby forming a final phase change material film 212a.

As described above, in the present invention, the upper line width of the phase change material layer 212a is previously implemented by using the photoresist layer, thereby minimizing the recess of the phase change material due to the etch back process. That is, since the photoresist layer is an etch buffer layer to be removed through a subsequent stripping process, the photoresist layer is not burdened by a chemical during the CMP process for determining the upper line width. Therefore, the CMP process is sufficiently performed on the photosensitive film until the desired upper line width of the phase change material film is reached.

Then, the photoresist layer is removed, and the phase change material is filled in the trench in which the photoresist layer is removed to form a final phase change material layer. Thus, the desired top line width is minimized while minimizing the recession of the phase change material due to the etch- It becomes possible to form a phase change material film. That is, the line width (denoted by "D") of the upper region as compared to the lower region of the phase change material film (reference character "C") is reduced to provide an overlay margin between the phase change material film 212a and the upper pattern to be formed through a subsequent process Can be sufficiently secured as compared with the prior art.

Hereinafter, the manufacturing process of the phase change memory device shown in FIG. 2 will be described in more detail with reference to the drawings.

FIGS. 3A through 3E sequentially illustrate the fabrication of a phase change memory device according to a preferred embodiment of the present invention.

First, referring to FIG. 3A, a lower electrode contact 202 is formed in a known manner on a semiconductor substrate 200 on which a conventional access element is formed. Then, an interlayer insulating film 204 is deposited on the resultant structure in which the lower electrode contact 202 is formed.

Next, a normal photolithography process is performed on the interlayer insulating layer 204 to form a first trench 206 exposing the upper surface of the lower electrode contact 202. Then, the etch buffer layer 208 is formed on the front surface of the semiconductor substrate 200 on which the first trenches 206 are formed. Here, as the etch buffer layer 208, a material capable of stripping can be used. More specifically, a photoresist layer or an oxide layer can be used. For example, when the photoresist layer is applied to the etch buffer layer 208, the photoresist layer is preferably applied to a thickness of about 300 to 500 Å.

Referring to FIG. 3B, the etching buffer film 208 is subjected to an ordinary CMP process. As a result, the etch buffer layer 208a is present only in the first trench 206. [ At this time, the upper linewidth of the etch buffer layer 208a is controlled so as to reach a desired upper line width of the phase change material layer by controlling the process time during the CMP process for the etch buffer layer 208. [ That is, the upper line width of the phase change material film to be formed through a subsequent process is determined in advance using the etching buffer film 208a.

Typically, a chemical (slurry) is used as a chemical in the CMP process, which causes the underlying material to be attracted by the chemical. Therefore, the etch buffer layer 208 can not be etched by the chemical used in the CMP process. However, since the etching buffer film 208 is an etchant sacrificial film used to control the upper line width of the phase change material film formed through a subsequent process, it is cleanly removed through a subsequent cleaning process. Therefore, even if it is damaged by the chemical in the CMP process, no problem occurs.

Referring to FIG. 3C, the etch buffer layer 208a is removed by a wet clean process. At this time, a PR stripper may be used as the chemical used in the wet cleaning process.

On the other hand, when an oxide-based material layer is applied as the etch buffer layer 208, an HF-based chemical may be used as a material for removing the oxide-based material layer.

Thus, the etch buffer layer 208a in the first trenches 206 is removed to form a second trench 210 for forming a phase change material layer. Here, the upper line width of the second trenches 210 is substantially the same as the upper line width of the phase change material film to be formed through a subsequent process.

Referring to FIG. 3D, the phase change material 212 is deposited on the entire surface of the semiconductor substrate where the second trenches 210 are formed. At this time, the phase change material 212 may be a material selected from the group consisting of Ge, Se, Te, a mixture thereof, and an alloy thereof. More specifically, it may be Ge, Se, Te, Sb, Bi, Pb, Sn, As, S, Si, P, O, N and mixtures or alloys thereof.

Referring to FIG. 3E, a planarization process is performed on the semiconductor substrate 200 on which the phase change material 212 is deposited. At this time, as the planarization process, an etch-back process is performed not a CMP process in which a chemical is used. The etch back process is preferably performed until the interlayer insulating film 204 is exposed.

Thus, the etch back process is performed on the deposited phase change material 212 to isolate the phase change material 212 deposited in the second trench 210, thereby forming the final phase change material film 212a.

As described above, in the present invention, in forming the phase change material layer 212a, an etching buffer layer 208 is first deposited in the first trench 206 formed in the interlayer insulating layer 204 , And the upper line width of the etch buffer layer 208 is controlled to reach the upper line width of the phase change material layer 212a to be formed through a subsequent process by etching with a CMP process. Subsequently, the etching buffer film 208a inside the first trench 206 is removed, and then the phase change material 212 is secondarily deposited and etched back to complete the final phase change material film 212a .

As described above, in the present invention, the upper line width of the phase change material layer 212a is adjusted in advance by using the etch buffer layer 208 filled in the first trenches 206. Then, the etch buffer layer 208a in the first trench 206 is removed to form a second trench 210. In the second trench 210 where the etch buffer layer 208a is removed, By forming the final phase change material film 212a by filling the material 212, it is possible to freely adjust the upper line width of the phase change material film 212a while minimizing or preventing the recess of the phase change material.

The line width of the upper region of the phase change material film 212a according to the present invention is lower than that of the lower region of the phase change material film 212a according to the present invention. (Reference symbol " C ") and the line width of the upper region (reference symbol" D ") are greatly reduced.

By reducing the line width difference of the upper region with respect to the lower region of the phase change material film 212a, the overlay margin between the phase change material film 212a and the upper pattern to be formed through the subsequent process can be sufficiently secured as compared with the conventional one, The reliability of the semiconductor device can be improved, and further the yield can be further increased.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It can be understood that It is therefore to be understood that the above-described embodiments are illustrative and non-restrictive in every respect.

200: semiconductor substrate 202: lower electrode contact
204: interlayer insulating film 206: first trench
208: etching buffer film 210: second trench
212: phase change material 212a: phase change material film

Claims (7)

Forming a lower electrode contact over the semiconductor substrate;
Forming an interlayer insulating film having a first trench exposing the lower electrode contact on the semiconductor substrate;
Applying an etch buffer layer over the front surface of the semiconductor substrate on which the first trench is formed;
Performing a planarization process on the etch buffer layer to determine an upper line width of the first trench;
Removing the etch buffer layer to form a second trench;
Depositing a phase change material over the front side of the semiconductor substrate to fill the second trench;
And etching the phase change material so that a phase change material exists only in the second trench to form a final phase change material film. The method of claim 1, wherein the etch buffer layer is formed of a photoresist or an oxide-based material. 3. The method of claim 2, wherein the photoresist layer is formed to a thickness of 300-500 angstroms. 3. The method of claim 2, wherein the etch buffer layer is planarized by a CMP process. The phase change memory device according to claim 2, wherein the photoresist film existing in the first trench is removed by a PR stripper. The phase-change memory device according to claim 2, wherein the oxide-based material layer existing in the first trench is removed by a HF-based chemical. The method of claim 1, wherein the phase change material is etched by an etch back process.

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