KR20140042248A - Cmos image sensor - Google Patents

Abstract

A CMOS image sensor is disclosed. The CMOS image sensor comprises: a photodiode which is formed in a P conductive type semiconductor substrate and accumulates charges corresponding to an incident light; a first floating diffusion region for receiving photo-charges accumulated in the photodiode; a first transfer transistor for transmitting the accumulated charges in the photodiode to the first floating diffusion region; a second floating diffusion region for receiving photo-charges accumulated in the first floating diffusion region; and a second transfer transistor for transmitting the charges accumulated in the first floating diffusion region to the second floating diffusion region.

Description

CMOS image sensor "

The present invention relates to a CMOS image sensor.

In general, an image sensor is an element that converts an optical image into an electrical signal. Typical examples of such image sensors are a charge coupled device (CCD) and a CMOS image sensor (CIS).

The charge coupled device includes a plurality of MOS capacitors for moving charges (or carriers) generated by light. In contrast, the CMOS image sensor includes a plurality of unit pixels and a CMOS logic circuit for controlling output signals of the unit pixels.

The CMOS image sensor according to the related art has a problem in that leakage current is generated when a signal charge is stored in a floating diffusion region (FD).

The present invention is to provide a CMOS image sensor that can minimize the leakage current when the signal charge is stored in the floating diffusion (FD, Floating Diffusion).

An object of the present invention is to provide a CMOS image sensor capable of realizing a wide dynamic range (WDR) through a dual reading process.

The present invention can implement correlated double sampling (CDS) in both dual read signals and minimize noise by separating the floating diffusion region using a transistor and using the separated floating diffusion region as a charge storage space. To provide a CMOS image sensor that can be.

Other objects of the present invention will become readily apparent from the following description.

For reference, this application reveals that the result was developed through the "Star Fabless System Semiconductor Globalization Development Project," a national research and development project supported by the Ministry of Knowledge Economy.

According to an aspect of the present invention, a CMOS image sensor comprising: a photodiode formed in a P-conductive semiconductor substrate and accumulating charge corresponding to incident light; A first floating diffusion region for receiving the photocharges accumulated in the photodiode; A first transfer transistor transferring charges accumulated in the photodiode to the first floating diffusion region; A second floating diffusion region for receiving the photocharges accumulated in the first floating diffusion region; And a second transfer transistor configured to transfer charges accumulated in the first floating diffusion region to the second floating diffusion region.

The photodiodes each perform charge accumulation for two integration times for one frame of the image, wherein charges accumulated during the preceding integration time are subject to turn-on operation of the first transfer transistor prior to the commencement of the later integration time. It may be transmitted to the first floating diffusion region by.

Different exposure times may be applied in the two integrations.

The first floating diffusion region and the second floating diffusion region are formed on a first active region having a first concentration of N conductivity type formed inside the P conductive semiconductor substrate, and formed on the first active region. The second active region may be formed to have a relatively higher concentration than the first concentration, and some or all of the side surfaces of the first active region may contact the second active region.

The first floating diffusion region and the second floating diffusion region may be disposed so as not to contact the shallow trench isolation (STI) region, respectively.

A P conductive well having a relatively higher concentration than that of the P conductive semiconductor substrate may not be formed below the first floating diffusion region and the second floating diffusion region.

Side walls may be formed only in the second transfer transistor among the first transfer transistor and the second transfer transistor.

The first floating diffusion region may be electrically connected to at least one of a capacitor having a poly-insulator-poly (PiP) structure and a capacitor having a metal-insulator-metal (MiM) structure.

A voltage relatively higher than the reference voltage VDD may be applied to turn on the second transfer transistor.

And a reset transistor configured to transfer the photocharges accumulated in the second floating diffusion region to the source / drain region, and the channel width gradually increases as the second floating diffusion region approaches the source / drain region. It can be formed to.

Other aspects, features, and advantages will become apparent from the following drawings, claims, and detailed description of the invention.

According to the embodiment of the present invention, when the signal charge is stored in the floating diffusion region (FD, Floating Diffusion) there is an effect that the leakage current can be minimized.

It also has the effect of implementing a wide dynamic range (WDR) through dual reading processing.

In addition, by separating the floating diffusion region by using a transistor and using the separated floating diffusion region as a charge storage space, correlated double sampling (CDS) can be realized on all dual read signals and noise can be minimized. There is also an effect.

1 is an equivalent circuit diagram of a unit pixel of a CMOS image sensor according to the related art.
FIG. 2A is a plan view showing a unit pixel of the CMOS image sensor of FIG. 1; FIG.
2B is a cross-sectional view showing a unit pixel of the CMOS image sensor of FIG.
3 is an equivalent circuit diagram of a unit pixel of a CMOS image sensor according to an exemplary embodiment of the present invention.
4A and 4B are schematic plan views of unit pixels of a CMOS image sensor, respectively, according to one embodiment of the present invention;
5 is a cross-sectional view of the CMOS image sensor according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Where an element such as a layer, region or substrate is described as being "on" or "onto" another element, the element may be directly on top of another element or may extend directly over it , Or an intervening element may exist. On the other hand, if one element is referred to as being "directly on" another element or "directly onto" another element, there are no other intermediate elements. Also, when an element is described as being "connected" or "coupled" to another element, the element may be directly connected to or directly coupled to another element, or an intermediate intervening element may be present have. On the other hand, if one element is described as being "directly connected" or "directly coupled" to another element, there are no other intermediate elements.

The terms "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" Relative terms such as " vertical "may be used herein to describe a relationship to another element, layer or region of an element, layer or region, as shown in the figures. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

For the sake of convenience, the unit pixel including four transistors is described in the present specification, but the present invention is not limited thereto. For example, it is natural that the present invention can be applied without limitation to a unit pixel including three transistors or a unit pixel including five transistors.

1 is a diagram illustrating an equivalent circuit of a unit pixel of a CMOS image sensor according to the related art, FIG. 2A is a plan view illustrating a unit pixel of the CMOS image sensor of FIG. 1, and FIG. 2B is a CMOS image of FIG. 1. It is sectional drawing which shows the unit pixel of a sensor.

In general, the unit pixel of the CMOS image sensor includes one photo diode (PD) and four NMOS transistors (Tx, Rx, Sx, and Dx). 1, 2A and 2B, in addition, an overflow transistor (OFD) transistor 110 used as a blooming path for removing photo charges exceeding the capacity of the photodiode PD. The unit pixel of the image sensor further includes a. For reference, FIGS. 2A and 2B are a plan view and a sectional view of the region 120 shown in FIG.

Referring to FIGS. 1, 2A, and 2B, a transfer transistor (Tx) may perform a function for transferring photocharges collected in a photodiode PD to a floating diffusion (FD), and a reset transistor. (Rx, Reset Transistor) performs a function of setting the potential of the floating diffusion region FD to a desired value and discharging the electric charge to reset the floating diffusion region.

The source follower transistor Dx serves as a source follower buffer amplifier and the select transistor Sx serves as a switching element to address the input signal.

The overflow transistor (OFD Tr) 110 prevents a blooming phenomenon in which a photoelectric charge exceeding the capacity of the photodiode PD is injected into a neighboring unit pixel to brighten neighboring unit pixels, .

The operation of the unit pixel of the CMOS image sensor will be briefly described below.

First, when the reset transistor Rx is turned on, the potential of the floating diffusion region FD becomes the applied voltage VDD. When light is incident on the photodiode PD from the outside, an electron-hole pair (EHP) is generated and the signal charge is accumulated in the source region of the transfer transistor Tx.

When the transfer transistor Tx is turned on, the stored signal charge is transferred to the floating diffusion region FD to change the potential of the floating diffusion region FD, and at the same time, the gate potential of the source follower transistor Dx changes. At this time, when the select transistor Sx is turned on by the selection signal, the data data is output to the output terminal Out.

When the reset transistor Rx is turned on again, the potential of the floating diffusion region FD becomes the applied voltage VDD, and this process is repeated to output an image signal. When the overflow transistor 110 is turned on, photocharges exceeding the capacity of the photodiode PD generated by light incident on the photodiode PD are removed while the image signal is output.

3 is a diagram illustrating an equivalent circuit of a unit pixel of a CMOS image sensor according to an exemplary embodiment of the present invention, and FIGS. 4A and 4B are diagrams illustrating unit pixels of a CMOS image sensor according to an exemplary embodiment of the present invention. 5 is a schematic plan view, and FIG. 5 is a cross-sectional view of a CMOS image sensor according to an exemplary embodiment.

Referring to FIG. 3, a CMOS image sensor according to an exemplary embodiment of the present invention includes one photo diode 320 and five NMOS transistors Tx1, Tx2, Rx, Dx, and Sx. do. Although not shown, an overflow transistor (OFD) may be further included to remove the blooming phenomenon as described above.

That is, unlike the foregoing description with reference to the related drawings, the CMOS image sensor according to the present embodiment is divided into two regions by second transfer transistors Tx2 and 335 additionally provided with floating diffusion regions 340 and 345. It has a distinctive structure that is separated from each other, thereby enabling dual reading processing and noise minimization processing.

As described above, the floating diffusion region is divided into the first floating diffusion region 340 and the second floating diffusion region 345 by the second transfer transistor 335, and the first floating diffusion region 340 is temporarily stored. By using it as a space, you can read the reset level first and then the signal level. In addition, as described below, the first floating diffusion region 340 is not contact-etched, and the structures of the active regions of the first floating diffusion region 340 and the second floating diffusion region 345 are defined. By forming differently, it is possible to prevent leakage current in the first floating diffusion region 340.

In this case, dual reading is to acquire two images by performing integration and reading for each image processing of one frame twice. In general, a conventional CMOS image sensor performs only one integration and reading for image processing of one frame.

The CMOS image sensor according to the present embodiment performs one integration, for example, a long exposure time in order to make a dark area visible, and another integration in which a short exposure time is applied to make a bright area visible. By synthesizing the dual read signals, it is possible to implement a wide dynamic range (WDR).

In addition, the CMOS image sensor according to the present exemplary embodiment performs a correlated double sampling (CDS) (ie, a pure signal level is obtained by subtracting a reset level including noise from a signal level including noise) in a dual reading process. This can minimize noise. That is, the correlated double sampling process can be performed without noise for both the photocharges stored in the first floating diffusion region 340 and the photocharges accumulated in the photodiode 320 during each integration time.

For example, the operation process of the CMOS image sensor illustrated in FIG. 3 is briefly described. The photodiode 320 accumulates electric charges during a first integration time, and then turns on the first transfer transistor (Tx1) 330 to turn on the photo. The charge accumulated in the diode 320 is transferred to the first floating diffusion region FD1 340. Before proceeding to this process, if the charge is already stored in the first floating diffusion region 340, the second transfer transistor (Tx2) 335 is turned on and the charge stored in the first floating diffusion region 340 is removed. The processing transmitted to the two floating diffusion regions 345 (that is, the reset processing for the first floating diffusion region 340) will be preceded.

When the charge accumulated in the photodiode 320 is transferred to the first floating diffusion region 340, the photodiode 320 accumulates charges again during the second integration time.

When the second integration time is completed, dual reading starts. That is, the reset level is read by turning on and off the reset transistor Rx 350 after turning on the select transistor Sx. Subsequently, the second transfer transistor (Tx2) 335 is turned on and off so that the charge accumulated in the first floating diffusion region 340 (that is, the photocharge accumulated during the first integration time) is converted into the second floating diffusion region ( After transmitting to 345, the signal level is read and correlation double sampling (CDS) is performed. Correlated double sampling yields a pure first signal level from which noise has been removed.

Subsequently, the reset transistor 350 is turned on and off to read the reset level, and both the first transfer transistor Tx1 330 and the second transfer transistor Tx2 are turned on, and the first transfer transistor 330 is sequentially turned on. And by turning off the second transfer transistor 335, the charge accumulated in the photodiode 320 (that is, the photocharge accumulated during the second integration time) passes through the first floating diffusion region 340 and the second floating diffusion region. To 345. The signal level of the charge accumulated in the second floating diffusion region 345 is read and correlated double sampling is performed to obtain a pure second signal level from which noise is removed. As described above, uncertainty due to charge injection may be minimized by turning off the first transfer transistor 330 before the second transfer transistor 335.

4A and 4B are schematic plan views of unit pixels of a CMOS image sensor according to an embodiment of the present invention, respectively.

4A and 4B, the floating diffusion region is divided into two regions, that is, the first floating diffusion region 340 and the second floating diffusion region 345 by the second transfer transistor (Tx2) 335. You can check it. For reference, the closed drawing regions indicated by thick lines in the drawings conceptually represent relatively high concentration of impurity regions (eg, N + regions).

In addition, as shown in FIG. 4B, in order to reduce partition noise during the reset operation of the reset transistor 350, a channel gradually moves from the second floating diffusion region 345 toward the source / drain region (VDDP) 410. It may be formed in a structure in which the width of the channel is widened.

5 is a cross-sectional view of the CMOS image sensor according to an embodiment of the present invention.

Referring to FIG. 5, the cross-sectional structure of a unit pixel of the CMOS image sensor may include a P conductive semiconductor substrate 510, a photodiode 320, a first floating diffusion region 340, and a second floating diffusion region 345. And a source / drain region 410, a first transfer transistor 330, a second transfer transistor 335, a reset transistor 350, and an STI region 520.

The photodiode 320 that accumulates the charge generated by absorbing light energy may include an N-type active region and a P-conductive pinning layer.

The first and second floating diffusion regions 340 and 345, which receive charges accumulated in the photodiode 320 and transfer them to other regions, may have a relatively high concentration of the first active region (ie, the upper portion) to reduce leakage current. The second active region (ie, the n- region shown) is surrounded by a relatively low concentration of the illustrated n + region.

That is, by first forming a second active region at a predetermined depth in the P conductivity type semiconductor substrate 510 and then forming a first active region at an upper position thereof, a part of the first active region overlaps with each other. It may be formed as if it is surrounded by an area. By adopting such a structure, some of the junctions of the high concentration of the N conductive type first active region and the P conductive type semiconductor substrate 510 are the second active region of the low concentration N conductivity type and the P conductive type semiconductor substrate 510. It is changed to a junction of so that the leakage current can be reduced.

In this case, the process may be simplified by simultaneously forming the lower active regions of the first and second floating diffusion regions 340 and 345 and the active regions of the photodiode 320 using one mask.

Also, by not forming a separate P-conducting well having a higher concentration than the P-conducting semiconductor substrate 510 under the first and second floating diffusion regions 340 and 345, it is relatively connected to the second active region. Leakage current can also be reduced.

Of course, since the second floating diffusion region 345 is not an area for storing the transferred photocharges for a predetermined time (for example, 30usec) or more, the influence of the leakage current may be small, and the lower portion of the P-conducting well This may be formed.

In addition, the first floating diffusion region 340 forms an additional contact to be connected to a separate capacitor (for example, a poly-insulator-poly (PIP), a capacitor having a metal-insulator-metal (MiM) structure, etc.). It may be formed in a structure that is. As a result, sufficient photocharge may be accumulated even when the capacity of the first floating diffusion region 340 itself is insufficient.

In addition, as a structure for reducing leakage current generated by the CMOS image sensor, the first and second floating diffusion regions 340 and 345 may be formed to be spaced apart from the STI region 520 by a predetermined distance.

In addition, as shown in FIG. 5, the sidewalls may be formed only in the second transfer transistor 335, as shown in FIG. 5, to reduce leakage current.

If a high concentration of N-conductive ions are implanted into the semiconductor substrate 510 after the sidewalls are formed, a high-concentration N-conductive ions are not implanted in the portion where the sidewalls are formed, thereby forming a self-aligned mask. Can function. Sidewalls are similar to, for example, CMOS-based processes for forming a lightly doped drain (LDD) structure and may be formed using an etch barrier mask.

That is, after depositing SiO 2 or SiN as an insulator, photoresist is formed only in the photodiode region, the first transfer transistor region, and the first floating diffusion region 340 using an etch barrier mask, and then etched to selectively sidewall. Can be formed. However, a defect may occur because the high energy plasma used in the etching process breaks the crystal of the active region, and a pair of electron holes may be generated from the defect to act as a leakage current.

The upper active region of the second floating diffusion region 345 should form an ohmic contact and in order to improve the photocharge transfer capability from the first floating diffusion region 340 to the second floating diffusion region 345. It should be formed at a relatively higher concentration than the upper active region of the first floating diffusion region 340. Accordingly, by forming a sidewall in the second transfer transistor 335 and then implanting a high concentration of N-conductive ions, the implantation area can be reduced to prevent the capacitance of the second floating diffusion region 345 from increasing.

This is because the sensitivity decreases when the capacitance of the second floating diffusion region 345 increases, and when the n + ion concentration of the semiconductor on which the contact is formed is low, there is an adverse effect that no ohmic contact is formed. For reference, as illustrated, the upper active region of the first floating diffusion region 340 shows a phenomenon in which the depth of penetration and the concentration are lower than those of the upper active region of the second floating diffusion region 345 because of the insulation formed thereon. .

In addition, the first transfer transistor 330 transmits the photocharges accumulated in the active region of the photodiode 320 to the first floating diffusion region 340 by the turn-on process, and the second transfer transistor 335 is turned on. The photocharges accumulated in the active region of the first floating diffusion region 340 are transferred to the second floating diffusion region 345.

The second transfer transistor 335 is turned on by applying a voltage higher than the reference applied voltage VDD to more easily transfer charges from the first floating diffusion region 340 to the second floating diffusion region 345. It may also be configured to. For this purpose, there is a boost circuit that provides a relatively high voltage to the external circuit, and the output of the boost circuit can be applied to the second transfer transistor 335 via the switching decoder circuit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims And changes may be made without departing from the spirit and scope of the invention.

320: photodiode 330: first transfer transistor
335: second transfer transistor 340: first floating diffusion region
345: second floating diffusion region 350: reset transistor
410: source / drain region 510: semiconductor substrate
520: STI area

Claims (10)

In the CMOS image sensor,
A photodiode formed in the P conductivity type semiconductor substrate and accumulating charges corresponding to incident light;
A first floating diffusion region for receiving the photocharges accumulated in the photodiode;
A first transfer transistor transferring charges accumulated in the photodiode to the first floating diffusion region;
A second floating diffusion region for receiving the photocharges accumulated in the first floating diffusion region; And
And a second transfer transistor configured to transfer charges accumulated in the first floating diffusion region to the second floating diffusion region.
The method of claim 1,
The photodiodes each accumulate charge for two integration times for one frame of the image,
Charge accumulated during the previous integration time is transferred to the first floating diffusion region by a turn-on operation of the first transfer transistor before the start of the later integration time.
3. The method of claim 2,
CMOS image sensor, characterized in that different exposure times are applied in the two integrations.
The method of claim 1,
The first floating diffusion region and the second floating diffusion region,
A first active region having a first concentration of N conductivity type formed inside the P conductive semiconductor substrate, and a second active region formed over the first active region and having a relatively higher concentration than the first concentration; Formed,
Some or all of the side surfaces of the first active area are in contact with the second active area.
The method of claim 1,
And the first floating diffusion region and the second floating diffusion region are disposed not to be in contact with the shallow trench isolation (STI) region, respectively.
The method of claim 1,
And a P conductive well having a relatively higher concentration than that of the P conductive semiconductor substrate is not formed below the first floating diffusion region and the second floating diffusion region.
The method of claim 1,
And a side wall is formed only in the second transfer transistor among the first transfer transistor and the second transfer transistor.
The method of claim 1,
And the first floating diffusion region is electrically connected to at least one of a capacitor having a poly-insulator-poly (PiP) structure and a capacitor having a metal-insulator-metal (MiM) structure.
The method of claim 1,
And a voltage higher than a reference voltage (VDD) is applied to turn on the second transfer transistor.
The method of claim 1,
And a reset transistor configured to transfer the photocharges accumulated in the second floating diffusion region to a source / drain region.
And a channel width gradually increases as the second floating diffusion region approaches the source / drain region.

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