KR20140042226A - Semiconductor chip and stack package using the same - Google Patents

Semiconductor chip and stack package using the same Download PDF

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KR20140042226A
KR20140042226A KR1020120108697A KR20120108697A KR20140042226A KR 20140042226 A KR20140042226 A KR 20140042226A KR 1020120108697 A KR1020120108697 A KR 1020120108697A KR 20120108697 A KR20120108697 A KR 20120108697A KR 20140042226 A KR20140042226 A KR 20140042226A
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semiconductor chip
cavity
chip
electrode
chip body
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KR1020120108697A
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Korean (ko)
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양승택
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에스케이하이닉스 주식회사
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Priority to KR1020120108697A priority Critical patent/KR20140042226A/en
Publication of KR20140042226A publication Critical patent/KR20140042226A/en

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Abstract

The present invention relates to a semiconductor chip and a stack package using the same. According to one embodiment of the present invention, the semiconductor chip and the stack package using the same include a chip body; and a through electrode. According to one embodiment of the present invention, the chip body includes a first surface and a second surface facing the first surface. A cavity is formed on the second surface. The through electrode penetrates the first surface and the second surface.

Description

반도체 칩 및 이를 이용한 스택 패키지{semiconductor chip and stack package using the same}Semiconductor chip and stack package using the same

본 발명은 반도체 칩 및 스택 패키지에 관한 것으로, 보다 상세하게는 얼라인 작업을 최소화하고 여러 개의 다이본딩 작업을 동시에 진행할 수 있도록 한 반도체 칩 및 이를 이용한 스택 패키지에 관한 것이다.
The present invention relates to a semiconductor chip and a stack package, and more particularly, to a semiconductor chip and a stack package using the same to minimize the alignment work and to simultaneously perform a plurality of die bonding operations.

최근 들어 전자기기의 박형화·소형화 추세에 따라 반도체 소자를 탑재하는 패키징(packaging) 기술도 고속, 고기능, 고밀도 실장이 요구되며, 이러한 요구에 부응하여 칩 스케일 패키지 형태의 플립칩 실장 기술이 등장하게 되었다.Recently, in accordance with the trend of thinning and miniaturization of electronic devices, packaging technology for mounting semiconductor devices also requires high-speed, high-performance, high-density mounting, and in response to this demand, chip-chip package flip chip mounting technology has emerged. .

플립칩 실장 기술은 반도체 칩을 패키징하지 않고 그대로 기판에 실장하는 기술로, 기판 상에 형성된 접속패드들 위에 대응 배치되는 범프(bump)를 매개로 기판과 반도체 칩은 솔더링 방식으로 접속시키는 것이다.Flip chip mounting technology is a technology in which a semiconductor chip is mounted on a substrate without packaging, and a substrate and a semiconductor chip are connected by soldering through bumps correspondingly disposed on connection pads formed on the substrate.

이와 같은 방법으로 기판에 반도체 칩이 실장되면 반도체 칩의 패드에 부착된 범프의 높이로 인해 반도체 칩과 인쇄회로기판 사이에 갭(gap)이 발생되어 반도체 칩의 지지력이 약화된다.When the semiconductor chip is mounted on the substrate in this manner, a gap is generated between the semiconductor chip and the printed circuit board due to the height of the bumps attached to the pads of the semiconductor chip, thereby weakening the holding force of the semiconductor chip.

따라서, 반도체 칩을 안정적으로 지지하기 위해서는 반도체 칩과 기판 사이에 발생된 갭에 디스펜서(dispenser)를 이용하여 액상의 언더필 부재를 주입하고, 주입된 언더필 부재를 경화시켜 반도체 칩을 지지하는 언더필층을 형성하였다.Therefore, in order to stably support the semiconductor chip, a liquid underfill member is injected into the gap generated between the semiconductor chip and the substrate by using a dispenser, and the underfill layer that supports the semiconductor chip is cured by curing the injected underfill member. Formed.

이와 같이, 기존에는 범프가 형성되어 있는 반도체 칩을 NCP 또는 NCF 등을 적용하여 기판 상에 본딩하게 되는데, 반도체 칩을 기판 상에 얼라인하고 다이 본딩한 후 열과 압력을 가하여 공정을 완료하는 데까지 1~2분 정도 소요가 된다. 따라서, 다수의 반도체 칩을 본딩하기 위해서는 그만큼 시간이 누적될 수 밖에 없다. 또한, TSV가 적용된 반도체 칩의 본딩 작업에서는 그 이상의 추가 시간이 요구된다.As such, conventionally, a semiconductor chip having bumps is bonded to a substrate by applying NCP or NCF, and the semiconductor chip is aligned and die-bonded on the substrate and then subjected to heat and pressure to complete the process. It takes about 2 minutes. Accordingly, in order to bond a plurality of semiconductor chips, time is inevitably accumulated. In addition, bonding time of the semiconductor chip to which TSV is applied requires more time.

따라서 이러한 취약점을 개선하기 위하여 여러 개의 반도체 칩을 얼라인하고 여러 개의 반도체 칩들을 한번에 압력을 가하여 본딩하는 방식이 개발 중에 있으나, 이 또한 얼라인을 위한 시간이 추가로 필요하다.
Therefore, in order to remedy this weakness, a method of aligning several semiconductor chips and bonding several semiconductor chips under pressure is under development, but this also requires additional time for alignment.

본 발명은 얼라인 작업을 최소화하고 다량의 반도체 칩을 동시에 다이본딩할 수 있도록 한 반도체 칩 및 이를 이용한 스택 패키지를 제공한다.
The present invention provides a semiconductor chip and a stack package using the same, which minimizes the alignment work and simultaneously die-bonds a large amount of semiconductor chips.

상술한 과제를 해결하기 위하여, 본 발명은 제1면 및 이에 대향하는 제2면을 가지며, 상기 제2면에 캐버티가 형성된 칩 몸체; 상기 칩 몸체 내에 상기 제1면과 제2면을 관통하도록 형성된 관통전극;을 포함하는 반도체 칩을 제공한다.In order to solve the above problems, the present invention has a first surface and a second surface opposite to the chip body, the cavity is formed on the second surface; And a through electrode formed to penetrate the first and second surfaces of the chip body.

상기 캐버티의 측면을 포함한 칩 몸체의 측면은 상기 제1면으로부터 제2면으로 갈수록 외측으로 벌어지는 경사면을 가질 수 있다.The side surface of the chip body including the side surface of the cavity may have an inclined surface that extends outward from the first surface to the second surface.

상기 제1면에 배치된 관통전극의 단부 상에 형성된 범프를 더 포함할 수 있다.It may further include a bump formed on the end of the through electrode disposed on the first surface.

상기 캐버티의 바닥면과 측면에 형성된 패시베이션층을 더 포함하고, 상기 패시베이션층은 산화막 또는 질화막이 증착되어 형성될 수 있다.Further comprising a passivation layer formed on the bottom and side surfaces of the cavity, the passivation layer may be formed by depositing an oxide film or a nitride film.

또한, 본 발명은 제1면 및 이에 대향하는 제2면을 가지며 상기 제2면에 캐버티가 형성된 제1 칩 몸체, 상기 제1 칩 몸체 내에 상기 제1면과 제2면을 관통하도록 형성된 제1 관통전극을 구비한 적어도 하나 이상의 제1 반도체 칩; 상기 적층된 제1 반도체 칩들 중 최상부에 배치된 제1 반도체 칩의 캐버티에 삽입되는 제3면 및 이에 대향하는 제4면을 갖는 제2 칩 몸체, 상기 제2 칩 몸체 내에 상기 제3면과 제4면을 관통하도록 형성되어 상기 제1 관통전극과 전기적으로 연결되는 제2 관통전극을 구비한 제2 반도체 칩;을 포함하는 스택 패키지를 제공한다.In addition, the present invention is a first chip body having a first surface and a second surface opposite thereto and having a cavity formed on the second surface, the first chip body formed to penetrate the first surface and the second surface in the first chip body. At least one first semiconductor chip having one through electrode; A second chip body having a third surface inserted into a cavity of a first semiconductor chip disposed on a top of the stacked first semiconductor chips and a fourth surface opposite thereto, the third surface in the second chip body; And a second semiconductor chip formed to penetrate a fourth surface and having a second through electrode electrically connected to the first through electrode.

상기 캐버티의 측면을 포함한 제1 및 제2 칩 몸체의 측면은 하부로부터 상부로 갈수록 외측으로 벌어지는 경사면을 가질 수 있다.Side surfaces of the first and second chip bodies including the side surfaces of the cavity may have inclined surfaces that spread outward from the bottom to the top.

상기 제1면에 배치된 제1 관통전극의 단부 상에 형성된 제1 범프를 더 포함할 수 있다.The display device may further include a first bump formed on an end portion of the first through electrode disposed on the first surface.

상기 제3면에 배치된 제2 관통전극의 단부 상에 형성된 제2 범프를 더 포함할 수 있다.The display device may further include a second bump formed on an end portion of the second through electrode disposed on the third surface.

상기 캐버티의 바닥면과 측면에 형성된 패시베이션층을 더 포함하고, 상기 패시베이션층은 산화막 또는 질화막이 증착되어 형성될 수 있다.Further comprising a passivation layer formed on the bottom and side surfaces of the cavity, the passivation layer may be formed by depositing an oxide film or a nitride film.

상기 제1 반도체 칩의 캐버티에 형성되는 언더필층을 더 포함할 수 있다.
It may further include an underfill layer formed in the cavity of the first semiconductor chip.

본 발명에 따르면, 반도체 칩의 일면에 캐버티를 형성함으로써 그 위에 또 다른 반도체 칩이 자연스럽게 얼라인될 수 있으므로, 한번에 다량의 반도체 칩의 실장이 가능하게 된다. 이와 같이 복수의 반도체 칩을 적층하는 공정을 동시에 다량으로 진행할 수 있으므로 공정 시간 및 공정 비용을 절감할 수 있다.
According to the present invention, by forming a cavity on one surface of the semiconductor chip, another semiconductor chip can be naturally aligned thereon, so that a large amount of semiconductor chips can be mounted at a time. As described above, since the process of stacking a plurality of semiconductor chips can be simultaneously performed in large quantities, the process time and the process cost can be reduced.

도 1은 본 발명의 일 실시예에 의한 반도체 칩을 도시한 단면도.
도 2는 본 발명의 일 실시예에 의한 스택 패키지를 도시한 단면도.
도 3 내지 도 10은 각각 본 발명의 일 실시예에 따른 스택 패키지의 제조방법을 순차적으로 도시한 단면도.
도 11은 본 발명에 따른 반도체 패키지를 적용한 전자 장치의 시스템 블록도.
도 12는 본 발명에 따른 반도체 패키지를 포함하는 전자 장치의 예를 보여주는 블록도.1 is a cross-sectional view showing a semiconductor chip according to an embodiment of the present invention.
2 is a cross-sectional view showing a stack package according to an embodiment of the present invention.
3 to 10 are cross-sectional views sequentially illustrating a method of manufacturing a stack package according to an embodiment of the present invention, respectively.
11 is a system block diagram of an electronic device to which a semiconductor package according to the present invention is applied.
12 is a block diagram showing an example of an electronic device including a semiconductor package according to the present invention;

이하에서는, 본 발명에 의한 반도체 칩 및 이를 이용한 스택 패키지의 바람직한 실시예를 첨부 도면을 참고하여 설명한다.Hereinafter, a preferred embodiment of a semiconductor chip and a stack package using the same according to the present invention will be described with reference to the accompanying drawings.

도 1은 본 발명의 일 실시예에 따른 반도체 칩을 도시한 것이다.1 illustrates a semiconductor chip according to an embodiment of the present invention.

도시된 바와 같이, 본 실시예의 반도체 칩(10)은 칩 몸체(11), 관통전극(12), 범프(13)를 포함한다.As shown, the semiconductor chip 10 of the present embodiment includes a chip body 11, a through electrode 12, and a bump 13.

칩 몸체(11)는 평면상 대략 장방형으로 이루어지며, 제1면(11a)과 이에 대향하는 제2면(11b)을 갖는다. 칩 몸체(11)의 내부에는 메모리, 로직, 수동소자 등이 포함될 수 있다. 칩 몸체(11)의 제1면(11a)에는 인터포저(도시 생략) 등과 전기적으로 연결하기 위해 적어도 하나 이상의 본딩패드(도시 생략)가 형성된다. 칩 몸체(11)의 제2면(11b)에는 또 다른 반도체 칩의 적층 편리성을 위해 소정 깊이로 캐버티(15)가 형성된다. 즉, 반도체 칩(10)의 제1면(11a) 테두리에는 캐버티(15)의 측면이 울타리 형태로 상향 돌출 형성된다. 이때, 캐버티(15)의 측면을 포함한 칩 몸체(11)의 측면은 제1면(11a)으로부터 제2면(11b)으로 갈수록 즉, 도면상 상측 방향으로 갈수록 외측으로 벌어지도록 소정 각도로 경사면이 형성된다. 경사면이 형성된 칩 몸체의 측면은 그 위에 다른 반도체 칩(10)이 적층되는 것을 안내함으로써 얼라인 작업에 소모되는 시간을 단축할 수 있다. 캐버티(15)의 바닥면과 측면에는 패시베이션층(14)이 형성될 수 있으며, 패시베이션층(14)은 폴리머 예컨대 산화막 또는 질화막을 증착하여 구현할 수 있다.The chip body 11 has a substantially rectangular shape in plan view, and has a first surface 11a and a second surface 11b opposite thereto. The inside of the chip body 11 may include a memory, logic, passive elements, and the like. At least one bonding pad (not shown) is formed on the first surface 11a of the chip body 11 to be electrically connected to an interposer (not shown). The cavity 15 is formed on the second surface 11b of the chip body 11 to a predetermined depth for the convenience of stacking another semiconductor chip. That is, the side surface of the cavity 15 protrudes upward in a fence shape at the edge of the first surface 11a of the semiconductor chip 10. At this time, the side surface of the chip body 11 including the side surface of the cavity 15 is inclined at a predetermined angle so as to open outward from the first surface 11a to the second surface 11b, that is, toward the upper side in the drawing. Is formed. The side surface of the chip body on which the inclined surface is formed may reduce the time required for the alignment operation by guiding the stack of the other semiconductor chip 10 thereon. The passivation layer 14 may be formed on the bottom and side surfaces of the cavity 15, and the passivation layer 14 may be formed by depositing a polymer such as an oxide film or a nitride film.

관통전극(12)은 본딩패드와 연결되도록 칩 몸체(11)의 제1면(11a)으로부터 제2면(11b)을 관통 형성되어 내부 접속단자로서의 역할을 수행한다. 관통전극(12)으로는 도전성 물질, 예컨대 구리가 적용될 수 있다. 관통전극(12)은 칩 몸체(11)의 제2면 즉, 캐버티(15)의 바닥면으로부터 상측으로 소정량 돌출 형성될 수 있다.The through electrode 12 penetrates through the second surface 11b from the first surface 11a of the chip body 11 so as to be connected to the bonding pad, and serves as an internal connection terminal. A conductive material such as copper may be applied to the through electrode 12. The through electrode 12 may protrude a predetermined amount upward from the second surface of the chip body 11, that is, the bottom surface of the cavity 15.

범프(13)는 외부 접속단자로서의 역할을 수행하는 것으로, 칩 몸체의 제1면에 배치된 관통전극의 단부 상에 형성될 수 있다.
The bump 13 serves as an external connection terminal, and may be formed on an end portion of the through electrode disposed on the first surface of the chip body.

도 2는 본 발명의 일 실시예에 따른 스택 패키지를 도시한 것이다.2 illustrates a stack package according to an embodiment of the present invention.

도시된 바와 같이, 본 실시예의 스택 패키지는 적어도 하나 이상의 제1 반도체 칩과, 제1 반도체 칩 상에 적층되는 제2 반도체 칩(20)을 포함한다. 본 실시예에서 3개의 제1 반도체 칩을 적용한 것은 설명의 편의를 위한 것일 뿐, 적층되는 제1 반도체 칩의 개수는 그보다 많거나 또는 적어도 상관없다.As shown, the stack package of the present embodiment includes at least one first semiconductor chip and a second semiconductor chip 20 stacked on the first semiconductor chip. The application of the three first semiconductor chips in this embodiment is merely for convenience of description, and the number of the stacked first semiconductor chips is greater than or at least.

제1 반도체 칩(10)은 제1 칩 몸체(11), 제1 관통전극(12), 제1 범프(13)를 포함한다.The first semiconductor chip 10 includes a first chip body 11, a first through electrode 12, and a first bump 13.

제1 칩 몸체(11)는 평면상 대략 장방형으로 이루어지며, 제1면(11a)과 이에 대향하는 제2면(11b)을 갖는다. 제1 칩 몸체(11)의 내부에는 메모리, 로직, 수동소자 등이 포함될 수 있다. 제1 칩 몸체(11)의 제1면(11a)에는 인터포저(도시 생략) 등과 전기적으로 연결하기 위해 적어도 하나 이상의 본딩패드(도시 생략)가 형성된다. 제1 칩 몸체(11)의 제2면(11b)에는 또 다른 반도체 칩의 적층 편리성을 위해 소정 깊이로 캐버티(15)가 형성된다. 즉, 제1 반도체 칩(10)의 제1면(11a) 테두리에는 캐버티(15)의 측면이 울타리 형태로 상향 돌출 형성된다. 이때, 캐버티(15)의 측면을 포함한 제1 칩 몸체(11)의 측면은 제1면(11a)으로부터 제2면(11b)으로 갈수록 즉, 도면상 하부에서 상부 방향으로 갈수록 외측으로 벌어지도록 소정 각도로 경사면이 형성된다. 경사면이 형성된 제1 칩 몸체(11)의 측면은 그 위에 다른 반도체 칩이 적층되는 것을 안내함으로써 얼라인 작업에 소모되는 시간을 단축할 수 있다. 캐버티(15)의 바닥면과 측면에는 패시베이션층(14)이 형성될 수 있다.The first chip body 11 has a substantially rectangular shape in plan and has a first surface 11a and a second surface 11b opposite thereto. The inside of the first chip body 11 may include a memory, logic, passive elements, and the like. At least one bonding pad (not shown) is formed on the first surface 11a of the first chip body 11 to be electrically connected to an interposer (not shown). The cavity 15 is formed on the second surface 11b of the first chip body 11 at a predetermined depth for the convenience of stacking another semiconductor chip. That is, the side surface of the cavity 15 protrudes upward in a fence shape at the edge of the first surface 11a of the first semiconductor chip 10. At this time, the side surface of the first chip body 11 including the side surface of the cavity 15 is opened to the outside toward the second surface 11b from the first surface 11a, that is, from the lower side to the upper direction in the drawing. An inclined surface is formed at a predetermined angle. The side surface of the first chip body 11 on which the inclined surface is formed may guide the stacking of other semiconductor chips thereon, thereby reducing the time required for the alignment operation. The passivation layer 14 may be formed on the bottom and side surfaces of the cavity 15.

제1 관통전극(12)은 본딩패드와 연결되도록 제1 칩 몸체(11)의 제1면(11a)으로부터 제2면(1b)을 관통하도록 형성되어 내부 접속단자로서의 역할을 수행한다. 제1 관통전극(12)으로는 도전성 물질, 예컨대 구리가 적용될 수 있다. 제1 관통전극(12)은 제1 칩 몸체(11)의 제2면(11b) 즉, 캐버티(15)의 바닥면으로부터 상측으로 소정량 돌출 형성될 수 있다.The first through electrode 12 is formed to penetrate the second surface 1b from the first surface 11a of the first chip body 11 so as to be connected to the bonding pad, and serves as an internal connection terminal. A conductive material such as copper may be used as the first through electrode 12. The first through electrode 12 may protrude a predetermined amount upward from the second surface 11b of the first chip body 11, that is, the bottom surface of the cavity 15.

제1 범프(13)는 외부 접속단자로서의 역할을 수행하는 것으로, 제1 칩 몸체(11)의 제1면으로 노출된 제1 관통전극(12)의 단부 상에 형성될 수 있다.
The first bump 13 serves as an external connection terminal and may be formed on an end portion of the first through electrode 12 exposed to the first surface of the first chip body 11.

제2 반도체 칩(20)은 적층된 제1 반도체 칩들 중 최상단에 배치된 제1 반도체 칩의 캐버티에 안착되며, 제2 반도체 칩(20)에는 캐버티가 형성되지 않아도 무방하다.The second semiconductor chip 20 may be seated in a cavity of the first semiconductor chip disposed at the top of the stacked first semiconductor chips, and the cavity may not be formed in the second semiconductor chip 20.

제2 반도체 칩(20)은 제2 칩 몸체(21), 제2 관통전극(22) 및 제2 범프(23)를 포함한다.The second semiconductor chip 20 includes a second chip body 21, a second through electrode 22, and a second bump 23.

제2 칩 몸체(21)는 평면상 대략 장방형으로 이루어지며, 최상단에 배치된 제1 반도체 칩의 캐버티에 안착되는 제3면(21a)과 이에 대향하는 제4면(21b)을 갖는다. 제2 칩 몸체(21)의 내부에는 메모리, 로직, 수동소자 등이 포함될 수 있다. 제2 칩 몸체(21)의 제3면(21a)에는 인터포저(도시 생략) 등과 전기적으로 연결하기 위해 적어도 하나 이상의 본딩패드(도시 생략)가 형성된다. 제2 칩 몸체(21)의 측면은 제3면(21a)으로부터 제4면(21b)으로 갈수록 즉, 도면상 하부에서 상부 방향으로 갈수록 외측으로 벌어지도록 소정 각도로 경사면이 형성된다. 경사면을 구비한 제2 칩 몸체(21)는 그 하측에 위치한 제1 반도체 칩(10)의 캐버티(15)에 자연스럽게 얼라인될 수 있으므로 얼라인 작업에 소모되는 시간을 단축할 수 있다.The second chip body 21 has a substantially rectangular shape in plan view, and has a third surface 21a seated in the cavity of the first semiconductor chip disposed at the top and a fourth surface 21b opposite thereto. The second chip body 21 may include a memory, logic, a passive element, and the like. At least one bonding pad (not shown) is formed on the third surface 21a of the second chip body 21 to be electrically connected to an interposer (not shown). The inclined surface is formed at a predetermined angle so that the side surface of the second chip body 21 opens outward from the third surface 21a toward the fourth surface 21b, that is, from the lower side to the upper side in the drawing. Since the second chip body 21 having the inclined surface may be naturally aligned with the cavity 15 of the first semiconductor chip 10 positioned below the inclined surface, the time required for the alignment operation may be shortened.

제2 관통전극(22)은 본딩패드와 연결되도록 제2 칩 몸체(21)의 제3면(21a)으로부터 제4면(1b)을 관통하도록 형성되어 내부 접속단자로서의 역할을 수행하며, 본 실시예에서 제2 관통전극(22)은 제1 반도체 칩의 제1 관통전극과 전기적으로 연결될 수 있다. 제2 관통전극(22)으로는 도전성 물질, 예컨대 구리가 적용될 수 있다. 제2 관통전극(22)은 그 일단이 제2 범프(23)와 연결되는 한편 타단은 제2 칩 몸체(21) 내에 매립된다.The second through electrode 22 is formed to penetrate the fourth surface 1b from the third surface 21a of the second chip body 21 so as to be connected to the bonding pad, and serves as an internal connection terminal. In an example, the second through electrode 22 may be electrically connected to the first through electrode of the first semiconductor chip. As the second through electrode 22, a conductive material such as copper may be applied. One end of the second through electrode 22 is connected to the second bump 23 while the other end is embedded in the second chip body 21.

제2 범프(23)는 외부 접속단자로서의 역할을 수행하는 것으로, 제2 칩 몸체(21)의 제3면(21a)으로 노출된 제2 관통전극(22)의 단부 상에 형성될 수 있다.
The second bump 23 serves as an external connection terminal and may be formed on an end portion of the second through electrode 22 exposed to the third surface 21a of the second chip body 21.

도 3 내지 도 8은 본 실시예의 스택 패키지를 제조하는 과정을 도시한 것이다.3 to 8 illustrate a process of manufacturing the stack package of this embodiment.

도 3에는 제1 반도체 칩(10)이 준비된 상태가 도시되어 있다. 제1 반도체 칩(10)은 복수의 제1 관통전극(12)을 구비하며, 제1 관통전극(12)의 일단은 제1 반도체 칩(10)의 제1면(11a)으로 노출되어 있다. 노출된 제1 관통전극(12)의 단부에는 외부 접속단자로서 제1 범프(13)가 형성되어 있다.3 illustrates a state in which the first semiconductor chip 10 is prepared. The first semiconductor chip 10 includes a plurality of first through electrodes 12, and one end of the first through electrode 12 is exposed to the first surface 11a of the first semiconductor chip 10. The first bump 13 is formed at an end of the exposed first through electrode 12 as an external connection terminal.

도 4에는 준비된 제1 반도체 칩(10)의 제2면(11b)을 연마하여 제1 반도체 칩(10)의 두께를 감소시킨 상태가 도시되어 있다. 제1 반도체 칩(10)은 대략 20~500㎛의 두께로 연마된다.4 shows a state in which the thickness of the first semiconductor chip 10 is reduced by grinding the prepared second surface 11b of the first semiconductor chip 10. The first semiconductor chip 10 is polished to a thickness of approximately 20 to 500 μm.

도 5에는 연마된 제1 반도체 칩(10)의 제2면(11b)에 캐버티(15)를 형성하기 위해 포토레지스트(PR)를 도포한 상태가 도시되어 있다.FIG. 5 illustrates a state in which photoresist PR is applied to form the cavity 15 on the second surface 11b of the polished first semiconductor chip 10.

도 6에는 설정된 패턴을 따라 포토레지스트(PR)를 에칭하여 제1 관통전극(12)의 상단이 제1 반도체 칩(10)의 제2면으로부터 노출되도록 한 상태가 도시되어 있다.FIG. 6 illustrates a state in which the photoresist PR is etched along the set pattern so that the upper end of the first through electrode 12 is exposed from the second surface of the first semiconductor chip 10.

이때, 에칭방법으로는 드라이 에치(dry etch) 또는 웨트 에치(wet etch) 모두 가능하다. 이와 같은 에칭공정에 의해 제1 반도체 칩(10)의 제2면(11b)에는 소정 깊이로 캐버티(15)가 형성된다.In this case, as an etching method, both dry etch or wet etch can be performed. By such an etching process, the cavity 15 is formed on the second surface 11b of the first semiconductor chip 10 to a predetermined depth.

도 7에는 제1 반도체 칩(10)의 제2면으로 노출된 제1 관통전극(12)을 보호하기 위해 패시베이션층(14)을 형성한 상태가 도시되어 있다. 패시베이션층(14)은 폴리머가 적용될 수 있으며, 예컨대 산화막 또는 질화막이 증착되어 형성될 수 있다.FIG. 7 illustrates a state in which the passivation layer 14 is formed to protect the first through electrode 12 exposed to the second surface of the first semiconductor chip 10. As the passivation layer 14, a polymer may be applied, and for example, an oxide film or a nitride film may be deposited.

도 8에는 캐버티(15)의 측면을 포함하여 제1 칩 몸체(11)의 측면을 소정 각도의 경사면을 갖도록 소잉(sawing)한 상태가 도시되어 있다.8 illustrates a state in which the side surface of the first chip body 11 including the side surface of the cavity 15 is sawed to have an inclined surface at a predetermined angle.

도 9에는 제2 반도체 칩(20) 및 복수의 제1 반도체 칩(10)을 준비하고, 각각의 제1 반도체 칩(10)의 캐버티(15)에 언더필 부재(16)를 도포한 상태가 도시되어 있다.9 shows a state in which the second semiconductor chip 20 and the plurality of first semiconductor chips 10 are prepared, and the underfill member 16 is applied to the cavity 15 of each first semiconductor chip 10. Is shown.

이때, 캐버티(15)의 측면 및 제1 칩 몸체(11)의 측면은 제1면(11a)으로부터 제2면(11b)으로 갈수록 외측 방향으로 벌어지게 경사면이 형성되어 있다. 이에 따라, 각 반도체 칩의 상측에 또 다른 반도체 칩의 적층시 캐버티(15)의 측면에 의해 그 위에 적층되는 반도체 칩(10)이 안내됨으로써 얼라인 작업에 소요되는 시간을 단축할 수 있게 된다.At this time, the side surface of the cavity 15 and the side surface of the first chip body 11 is formed to be inclined toward the outer direction toward the second surface 11b from the first surface 11a. Accordingly, when the semiconductor chip 10 stacked on the semiconductor chip 10 is guided by the side of the cavity 15 when the semiconductor chip is stacked on the upper side of each semiconductor chip, the time required for the alignment operation can be shortened. .

도 10에는 복수의 제1 반도체 칩(10) 및 제2 반도체 칩(20)이 적층된 상태가 도시되어 있다. 각 제1 반도체 칩(10)의 캐버티(15)에 그 상측에 위치한 제1 반도체 칩(10)의 제1면(11a)이 안착되고, 제1 반도체 칩들 중 최상단에 배치된 제1 반도체 칩의 캐버티에 제2 반도체 칩(20)의 제3면이 안착된 상태에서, 열과 압력을 가하여 본딩함으로써 복수의 반도체 칩(10)이 적층된 스택 패키지의 제조가 완료된다.10 illustrates a state in which a plurality of first semiconductor chips 10 and second semiconductor chips 20 are stacked. The first surface 11a of the first semiconductor chip 10 positioned above the cavity 15 of each first semiconductor chip 10 is seated, and the first semiconductor chip disposed at the top of the first semiconductor chips 10. In the state where the third surface of the second semiconductor chip 20 is seated in the cavity of the wafer, manufacturing of the stack package in which the plurality of semiconductor chips 10 are stacked is completed by bonding with heat and pressure.

이때, 본 실시예의 스택 패키지는 최상단에 위치한 제2 반도체 칩(20)에 WLP(Wafer Level Package) 공정을 적용함으로써 별도의 인터포저 등이 사용되지 않을 수도 있다.
In this case, in the stack package of the present embodiment, a separate interposer may not be used by applying a wafer level package (WLP) process to the second semiconductor chip 20 positioned at the top.

상술한 반도체 패키지 기술은 다양한 종류의 반도체 소자들 및 이를 구비하는 패키지 모듈에 적용될 수 있다.The above-described semiconductor package technology can be applied to various kinds of semiconductor devices and a package module having the same.

도 11을 참조하면, 본 발명의 반도체 패키지는 전자 시스템(1000)에 적용될 수 있다. 전자 시스템(1000)은 제어기(1100), 입출력 장치(1200) 및 기억장치(1300)를 포함할 수 있다. 제어기(1100), 입출력 장치(1200) 및 기억장치(1300)는 데이터들이 이동하는 통로를 제공하는 버스(1500)를 통하여 결합될 수 있다.Referring to FIG. 11, the semiconductor package of the present invention can be applied to the electronic system 1000. The electronic system 1000 may include a controller 1100, an input / output device 1200, and a memory device 1300. The controller 1100, the input / output device 1200, and the memory device 1300 may be coupled through a bus 1500 that provides a path through which data moves.

예컨대, 제어기(1100)는 적어도 하나의 마이크로프로세서, 디지털 신호 프로세서, 마이크로컨트롤러, 그리고 이들과 유사한 기능을 수행할 수 있는 논리 소자들 중에서 적어도 어느 하나를 포함할 수 있다. 제어기(1100) 및 기억장치(1300)는 본 발명 실시예에 따른 반도체 패키지를 적어도 어느 하나를 포함할 수 있다. 입출력 장치(1200)는 키패드, 키보드 및 표시 장치(display device) 등에서 선택된 적어도 하나를 포함할 수 있다. 기억장치(1300)는 데이터 및/또는 제어기(1100)에 의해 실행되는 명령어 등을 저장할 수 있다.For example, the controller 1100 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar thereto. The controller 1100 and the memory device 1300 may include at least one semiconductor package according to the embodiment of the present invention. The input / output device 1200 may include at least one selected from a keypad, a keyboard, a display device, and the like. The memory device 1300 may store data and / or commands executed by the controller 1100.

기억장치(1300)는 디램과 같은 휘발성 기억 소자 및/또는 플래시 메모리와 같은 비휘발성 기억 소자를 포함할 수 있다. 예를 들면, 모바일 기기나 데스크 톱 컴퓨터와 같은 정보 처리 시스템에 플래시 메모리가 장착될 수 있다. 이러한 플래시 메모리는 반도체 디스크 장치(SSD)로 구성될 수 있다. 이 경우 전자 시스템(100)은 대용량의 데이터를 상기 플래시 메모리 시스템에 안정적으로 저장할 수 있다.The memory device 1300 may include a volatile memory device such as a DRAM and / or a nonvolatile memory device such as a flash memory. For example, a flash memory may be installed in an information processing system such as a mobile device or a desktop computer. Such a flash memory may consist of a semiconductor disk device (SSD). In this case, the electronic system 100 may stably store large amounts of data in the flash memory system.

전자 시스템(1000)은 통신 네트워크로 데이터를 전송하거나 통신 네트워크로부터 데이터를 수신하기 위한 인터페이스(1400)를 더 포함할 수 있다. 인터페이스(1400)는 유무선 형태일 수 있다. 예컨대, 인터페이스(1400)는 안테나 또는 유무선 트랜시버 등을 포함할 수 있다. 전자 시스템(1000)에는 응용 칩셋(Application Chipset), 입출력 장치 등이 더 제공될 수 있다.The electronic system 1000 may further include an interface 1400 for transmitting data to or receiving data from the communication network. The interface 1400 may be in a wired or wireless form. For example, the interface 1400 may include an antenna or a wired / wireless transceiver. The electronic system 1000 may further include an application chipset, an input / output device, and the like.

전자 시스템(1000)은 모바일 시스템, 개인용 컴퓨터, 산업용 컴퓨터 또는 다양한 기능을 수행하는 로직 시스템 등으로 구현될 수 있다. 예컨대, 모바일 시스템은 개인 휴대용 정보 단말기(PDA; Personal Digital Assistant), 휴대용 컴퓨터, 웹 타블렛(web tablet), 모바일폰(mobile phone), 스마트폰(smart phone), 무선폰(wireless phone), 랩톱(laptop) 컴퓨터, 메모리 카드, 디지털 뮤직 시스템(digital music system) 그리고 정보 전송/수신 시스템 중 어느 하나일 수 있다.The electronic system 1000 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, a mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a smart phone, a wireless phone, a laptop ( laptop) may be any one of a computer, a memory card, a digital music system, and an information transmission / reception system.

전자 시스템(1000)이 무선 통신을 수행할 수 있는 장비인 경우에, 전자 시스템(1000)은 CDMA(Code Division Multiple Access), GSM(Global System for Mobile communication), NADC(North American Digital Cellular), E-TDMA(Enhanced-Time Division Multiple Access), WCDMA(Wideband Code Division Multiple Access), CDMA2000, LTE(Long Term Evolution), Wibro(Wireless Broadband Internet)과 같은 통신 시스템에서 사용될 수 있다.When the electronic system 1000 is a device capable of performing wireless communication, the electronic system 1000 may include Code Division Multiple Access (CDMA), Global System for Mobile communication (GSM), North American Digital Cellular (NADC), and E. -Can be used in communication systems such as Enhanced-Time Division Multiple Access (TDMA), Wideband Code Division Multiple Access (WCDMA), CDMA2000, Long Term Evolution (LTE), and Wireless Broadband Internet (Wibro).

도 12를 참조하면, 상술한 반도체 패키지는 메모리 카드(2000)의 형태로 제공될 수 있다. 일례로, 메모리 카드(2000)는 비휘발성 기억 소자와 같은 메모리(2100) 및 메모리 제어기(2200)를 포함할 수 있다. 메모리(2100) 및 메모리 제어기(2200)는 데이터를 저장하거나 저장된 데이터를 판독할 수 있다.Referring to FIG. 12, the semiconductor package described above may be provided in the form of a memory card 2000. For example, the memory card 2000 may include a memory 2100 such as a nonvolatile memory device and a memory controller 2200. The memory 2100 and the memory controller 2200 may store data or read stored data.

메모리(2100)는 본 발명에 따른 반도체 패키지 기술이 적용된 비휘발성 기억 소자들 중에서 적어도 어느 하나를 포함할 수 있다. 메모리 제어기(2200)는 호스트(2300)의 판독/쓰기 요청에 응답하여 저장된 데이터를 독출하거나, 데이터를 저장하도록 메모리(2100)를 제어할 수 있다.
The memory 2100 may include at least one of the nonvolatile memory elements to which the semiconductor package technology according to the present invention is applied. The memory controller 2200 may control the memory 2100 to read stored data or store data in response to a read / write request of the host 2300.

10, 20 ; 반도체 칩 11, 21 ; 칩 몸체
12, 22 ; 관통전극 13, 23 ; 범프
14 ; 패시베이션층 15 ; 캐버티
16 ; 언더필 부재 100 ; 스택 패키지10, 20; Semiconductor chips 11 and 21; Chip body
12, 22; Through electrodes 13 and 23; Bump
14; Passivation layer 15; Cavities
16; Underfill member 100; Stack package

Claims (12)

제1면 및 이에 대향하는 제2면을 가지며, 상기 제2면에 캐버티가 형성된 칩 몸체;
상기 칩 몸체 내에 상기 제1면과 제2면을 관통하도록 형성된 관통전극;
을 포함하는 반도체 칩.A chip body having a first surface and a second surface opposite thereto, the cavity having a cavity formed on the second surface;
A through electrode formed to penetrate the first and second surfaces of the chip body;
Semiconductor chip comprising a. 제1항에 있어서,
상기 캐버티의 측면을 포함한 칩 몸체의 측면은 상기 제1면으로부터 제2면으로 갈수록 외측으로 벌어지는 경사면을 갖는 것을 특징으로 하는 반도체 칩.The method of claim 1,
And a side surface of the chip body including the side surface of the cavity has an inclined surface that opens outwardly from the first surface to the second surface. 제1항에 있어서,
상기 제1면에 배치된 관통전극의 단부 상에 형성된 범프를 더 포함하는 것을 특징으로 하는 반도체 칩.The method of claim 1,
And a bump formed on an end portion of the through electrode disposed on the first surface. 제1항에 있어서,
상기 캐버티의 바닥면과 측면에 형성된 패시베이션층을 더 포함하는 것을 특징으로 하는 반도체 칩.The method of claim 1,
The semiconductor chip further comprises a passivation layer formed on the bottom and side surfaces of the cavity. 제4항에 있어서,
상기 패시베이션층은 산화막 또는 질화막이 증착되어 형성된 것을 특징으로 하는 반도체 칩.5. The method of claim 4,
The passivation layer is a semiconductor chip, characterized in that formed by depositing an oxide film or nitride film. 제1면 및 이에 대향하는 제2면을 가지며 상기 제2면에 캐버티가 형성된 제1 칩 몸체, 상기 제1 칩 몸체 내에 상기 제1면과 제2면을 관통하도록 형성된 제1 관통전극을 구비한 적어도 하나 이상의 제1 반도체 칩;
상기 적층된 제1 반도체 칩들 중 최상부에 배치된 제1 반도체 칩의 캐버티에 삽입되는 제3면 및 이에 대향하는 제4면을 갖는 제2 칩 몸체, 상기 제2 칩 몸체 내에 상기 제3면과 제4면을 관통하도록 형성되어 상기 제1 관통전극과 전기적으로 연결되는 제2 관통전극을 구비한 제2 반도체 칩;
을 포함하는 스택 패키지.A first chip body having a first surface and a second surface opposite thereto and having a cavity formed on the second surface, and a first through electrode formed to penetrate the first surface and the second surface in the first chip body; At least one first semiconductor chip;
A second chip body having a third surface inserted into a cavity of a first semiconductor chip disposed on a top of the stacked first semiconductor chips and a fourth surface opposite thereto, the third surface in the second chip body; A second semiconductor chip formed to penetrate a fourth surface and having a second through electrode electrically connected to the first through electrode;
≪ / RTI > 제6항에 있어서,
상기 캐버티의 측면을 포함한 제1 및 제2 칩 몸체의 측면은 하부로부터 상부로 갈수록 외측으로 벌어지는 경사면을 갖는 것을 특징으로 하는 스택 패키지.The method according to claim 6,
Side surfaces of the first and second chip body including the side of the cavity has an inclined surface that extends outwardly from the bottom to the top. 제6항에 있어서,
상기 제1면에 배치된 제1 관통전극의 단부 상에 형성된 제1 범프를 더 포함하는 것을 특징으로 하는 스택 패키지.The method according to claim 6,
And a first bump formed on an end of the first through electrode disposed on the first surface. 제6항에 있어서,
상기 제3면에 배치된 제2 관통전극의 단부 상에 형성된 제2 범프를 더 포함하는 것을 특징으로 하는 스택 패키지.The method according to claim 6,
And a second bump formed on an end of the second through electrode disposed on the third surface. 제6항에 있어서,
상기 캐버티의 바닥면과 측면에 형성된 패시베이션층을 더 포함하는 것을 특징으로 하는 스택 패키지.The method according to claim 6,
And a passivation layer formed on the bottom and side surfaces of the cavity. 제10항에 있어서,
상기 패시베이션층은 산화막 또는 질화막이 증착되어 형성된 것을 특징으로 하는 스택 패키지.11. The method of claim 10,
The passivation layer is a stack package, characterized in that formed by depositing an oxide film or nitride film. 제6항에 있어서,
상기 제1 반도체 칩의 캐버티에 형성되는 언더필층을 더 포함하는 것을 특징으로 하는 스택 패키지.The method according to claim 6,
The stack package of claim 1, further comprising an underfill layer formed in the cavity of the first semiconductor chip.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170140985A (en) * 2016-06-14 2017-12-22 삼성전자주식회사 Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170140985A (en) * 2016-06-14 2017-12-22 삼성전자주식회사 Semiconductor package

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