KR20140041112A - Liquid crystal display panel and method fo manufacturing the same - Google Patents

Abstract

A liquid crystal display panel according to an embodiment of the present invention includes: a gate line and a data line which intersect to define a pixel area; a thin film transistor which is connected to the gate line and the data line; a plurality of pixel electrodes which are formed on a drain electrode of the thin film transistor; a common electrode which is alternately arranged with the pixel electrodes; and a protection layer which is formed between the pixel electrode and the common electrode. The pixel electrode and the common electrode are formed in one process.

Description

Technical Field [0001] The present invention relates to a liquid crystal display panel and a manufacturing method thereof,

An embodiment relates to a liquid crystal display panel.

The embodiment relates to a method of manufacturing a liquid crystal display panel.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. A flat panel display device including a thin liquid crystal display (LCD), a plasma display (PDP) or an organic electroluminescent device (OLED) which is thinner and lighter than a conventional cathode ray tube display (CRT) has been actively researched and commercialized . Of these, liquid crystal display devices are widely used today because of their advantages of miniaturization, light weight, thinness, and low power driving.

One of the liquid crystal display devices currently in use is a twisted nematic (TN) liquid crystal display device. In the twisted nematic method, electrodes are provided on two substrates, liquid crystal directors are arranged so as to be twisted by 90 °, and a liquid crystal director is driven by applying a voltage to the electrodes. However, the TN type liquid crystal display device has a disadvantage that the viewing angle is narrow.

In order to solve the disadvantage that the viewing angle of the TN type liquid crystal display device is narrow, studies on a liquid crystal display device adopting a new method are actively conducted. In this way, in-plane switching (IPS) fringe field switching).

1 is a diagram illustrating a driving principle of a conventional IPS liquid crystal display device. Fig. 1 (a) shows the operation of the liquid crystal in the off state and Fig. 1 (b) shows the operation of the liquid crystal in the on state.

Referring to FIG. 1, an IPS liquid crystal display includes a first substrate 301, a second substrate 302, and a liquid crystal layer 306. The first substrate 301 and the second substrate 302 are opposed to each other and the liquid crystal layer 306 composed of the liquid crystals 307 is interposed between the first substrate 301 and the second substrate 302. [ . A plurality of pixel electrodes 341 and a plurality of common electrodes 343 are formed on the first substrate 301. The liquid crystal layer 307 is displaced by an electric field caused by a potential difference applied to the plurality of pixel electrodes 341 and the plurality of common electrodes 343 to display an image.

1 (a), there is no potential difference between the pixel electrode 341 and the common electrode 343, and the liquid crystal 307 is arranged in the front-back direction. The light from the backlight (not shown) is blocked by the liquid crystal 307 arranged in the forward and backward directions in the normally black mode, and an image of black is displayed. 1B, the pixel electrode 341 and the common electrode 343 are electrically connected to each other by a potential difference of different magnitude, and are electrically connected to the pixel electrode 341 and the common electrode 343, An electric field is generated in the direction of the arrow 308. The liquid crystal 307 is arranged in the left-right direction by the electric field in the direction of the arrow 308. [ In the normally black mode, light from a backlight (not shown) is transmitted by the liquid crystal 307 arranged in the left-right direction and an image of white is displayed. In the case of the IPS type liquid crystal display device, although the viewing angle is wide, there is a problem of luminance, and a fringe field switching (FFS) method has been devised.

2 is a diagram illustrating a driving principle of a conventional FFS type liquid crystal display device. 2 (a) shows the operation of the liquid crystal in the off state, and Fig. 2 (b) shows the operation of the liquid crystal in the on state.

Referring to FIG. 2, the FFS type liquid crystal display device is substantially the same as the IPS mode, except that the pixel electrode and the common electrode are formed on different layers. Therefore, the same reference numerals are assigned to the same components as those in FIG. 1, and a detailed description thereof will be omitted.

The FFS type liquid crystal display device of FIG. 2 further includes an insulating film 305 formed on the first substrate 301. A common electrode 343 is formed on the first substrate 301 and a pixel electrode 341 is formed on the insulating film 305. In the off state in FIG. 2A, there is no potential difference between the pixel electrode 341 and the common electrode 343, and the liquid crystal 307 is arranged in the front-back direction. In the normally black mode, the light from the backlight (not shown) is blocked by the liquid crystal 307 arranged in the front-rear direction, and a black image is displayed. An electric field is generated in the direction of an arrow 308 by a potential difference applied to the pixel electrode 341 and the common electrode 343 in an ON state in FIG. The liquid crystal 307 is arranged in the left-right direction by the electric field in the direction of the arrow 308. [ In the normally black mode, light from a backlight (not shown) is transmitted by the liquid crystal 307 arranged in the left-right direction and an image of white is displayed. In the case of the FFS method, the common electrode 343 and the pixel electrode 341 are arranged in different layers to generate a horizontal electric field as well as a vertical electric field. Thus, the liquid crystal can be arranged more precisely and the IPS The luminance reduction is less likely to occur. The positions of the pixel electrode 341 and the common electrode 343 may be changed. For example, a pixel electrode may be formed on the first substrate 301, and a common electrode may be formed on the insulating film 305.

In the FFS type liquid crystal display, the smaller the distance between the plurality of pixel electrodes 341 is, the higher the operation efficiency of the liquid crystal 307 is. However, there is a problem that the interval between the pixel electrodes 341 can not be further reduced due to process reasons such as mask tolerance due to the diffraction characteristics of light, and the transmittance can not be improved.

Embodiments provide a liquid crystal display panel in which transmittance is improved by increasing the operation efficiency of a liquid crystal.

The embodiment provides a method of manufacturing a liquid crystal display panel that can simplify the process.

A liquid crystal display panel according to an embodiment includes a gate line and a data line formed to intersect with each other to define a pixel region; A thin film transistor connected to the gate line and the data line; A plurality of pixel electrodes formed on the drain electrode of the thin film transistor; A common electrode formed alternately with the plurality of pixel electrodes; And a protective layer formed between the pixel electrode and the common electrode, wherein the pixel electrode and the common electrode are formed in a single process.

A method of manufacturing a liquid crystal display panel according to an embodiment includes forming a gate line on a substrate and a gate electrode extending to the gate line; Forming a gate insulating film and a semiconductor layer on the substrate on which the gate line is formed; Forming a data line, a source electrode, and a drain electrode on the gate insulating film; Forming a protective layer on the gate insulating layer on which the data line, the source electrode, and the drain electrode are formed; Forming a plurality of pixel contact holes in the passivation layer; And forming a plurality of pixel electrodes and a common electrode by applying a transparent conductive material onto the pixel contact holes and the protective layer.

The liquid crystal display panel according to the embodiment may improve the operation efficiency of the liquid crystal by improving the transmissivity by reducing the interval between the pixel electrode and the common electrode by forming the pixel electrode and the common electrode in different layers.

The liquid crystal display panel according to the embodiment has the protective layer formed as a double layer having different etch rates to facilitate the separation of the pixel electrode and the common electrode formed on different layers to prevent pixel defects.

The method of manufacturing a liquid crystal display panel according to an embodiment of the present invention simplifies the manufacturing process of a liquid crystal display panel by simultaneously forming a pixel electrode and a common electrode through a contact hole.

1 is a diagram illustrating a driving principle of a conventional IPS liquid crystal display device.
2 is a diagram illustrating a driving principle of a conventional FFS type liquid crystal display device.
3 is a plan view of a thin film transistor substrate of a liquid crystal display panel according to a first embodiment of the present invention.
4 is a cross-sectional view of the thin film transistor substrate of the liquid crystal display panel according to the first embodiment of the present invention taken along line A-A ', line B-B', and line C-C '.
5 is a view illustrating a method of manufacturing a thin film transistor substrate of a liquid crystal display panel according to a first embodiment of the present invention.
6 is a cross-sectional view of the thin film transistor substrate of the liquid crystal display panel according to the second embodiment of the present invention taken along line A-A ', line B-B', and line C-C '.
7 is a graph showing the transmittance of the liquid crystal display panel according to the second embodiment.
8 is a view illustrating a method of manufacturing a thin film transistor substrate of a liquid crystal display panel according to a second embodiment of the present invention.
9 is a plan view of a thin film transistor substrate of a liquid crystal display panel according to a third embodiment of the present invention.
10 is a cross-sectional view of a thin film transistor substrate of a liquid crystal display panel according to a third embodiment of the present invention, taken along line A-A ', line B-B', and line C-C '.
11 is a view illustrating a method of manufacturing a thin film transistor substrate of a liquid crystal display panel according to a third embodiment of the present invention.
12 is a plan view of a thin film transistor substrate of a liquid crystal display panel according to a fourth embodiment of the present invention.
FIG. 13 is a cross-sectional view of a thin film transistor substrate of a liquid crystal display panel according to a fourth embodiment of the present invention taken along AA ', BB', and CC 'directions.

A liquid crystal display panel according to an embodiment includes a gate line and a data line formed to intersect with each other to define a pixel region; A thin film transistor connected to the gate line and the data line; A plurality of pixel electrodes formed on the drain electrode of the thin film transistor; A common electrode formed alternately with the plurality of pixel electrodes; And a protective layer formed between the pixel electrode and the common electrode, wherein the pixel electrode and the common electrode are formed in a single process.

The plurality of pixel electrodes may be formed on the drain electrode exposed by the plurality of pixel contact holes passing through the passivation layer.

The protective layer may include a first protective layer and a second protective layer having different etching rates.

The first passivation layer and the second passivation layer are sequentially stacked, and the first passivation layer may have a higher etch rate than the second passivation layer.

The pixel contact hole may have a slope in a direction from the second passivation layer toward the first passivation layer.

The first protective layer and the second protective layer can control the mixing ratio of the deposition gas used for forming the protective layer to have different etch rates.

The drain electrode may be formed long in the pixel region along the gate line direction.

And a common line formed in a direction parallel to the gate line, wherein the common electrode comprises: a horizontal portion overlapping the common line; And a plurality of vertical portions connected to the horizontal portion and formed alternating with the plurality of pixel electrodes.

The horizontal portion may be electrically connected to the common line through a common contact hole.

And a lower pixel electrode formed on the pixel region to connect the drain electrode and the plurality of pixel electrodes.

A method of manufacturing a liquid crystal display panel according to an embodiment includes forming a gate line on a substrate and a gate electrode extending to the gate line; Forming a gate insulating film and a semiconductor layer on the substrate on which the gate line is formed; Forming a data line, a source electrode, and a drain electrode on the gate insulating film; Forming a protective layer on the gate insulating layer on which the data line, the source electrode, and the drain electrode are formed; Forming a plurality of pixel contact holes in the passivation layer; And forming a plurality of pixel electrodes and a common electrode by applying a transparent conductive material onto the pixel contact holes and the protective layer.

3 is a plan view of a thin film transistor substrate of a liquid crystal display panel according to a first embodiment of the present invention.

4 is a cross-sectional view of the thin film transistor substrate of the liquid crystal display panel according to the first embodiment of the present invention taken along line A-A ', line B-B', and line C-C '.

3 and 4, a thin film transistor substrate of a liquid crystal display panel according to a first embodiment of the present invention includes a plurality of gate lines 10 on a substrate 1 and a plurality of gate lines 10 parallel to the plurality of gate lines 10 A common line 20 is formed. The common line 20 may be formed in an area adjacent to an adjacent gate line. And the gate electrode 11 may be formed to extend to the gate line 10. [ The gate electrode 11 may be formed integrally with the gate line 10.

A gate insulating film 3 may be formed on the gate line 10 and the common line 20. A semiconductor layer 35 may be formed on the thin film transistor region on the gate insulating film 3. The semiconductor layer 35 may include a channel region and source and drain regions formed on both sides of the channel region.

A plurality of data lines 30 may be formed on the gate insulating layer 3 in a direction crossing the gate lines 10. [ An intersection pixel region of the plurality of gate lines 1 and the plurality of data lines 30 may be defined. A source electrode 31 extending from the data line 30 may be formed on the source region. The source electrode 31 may be formed integrally with the data line 30. A drain electrode 33 may be formed on the drain region. The drain electrode 33 may extend from the drain region to the adjacent data line. The drain electrode 33 may be formed in a direction parallel to the gate line 10 in a region adjacent to the gate line 10.

The gate electrode 11, the source electrode 31, the drain electrode 33 and the semiconductor layer 35 constitute a thin film transistor T.

A protective layer 5 may be formed on the data line 30. A pixel contact hole 51 may be formed in the protection layer 5 of the pixel region and a common contact hole 53 may be formed in the protection layer 5 of a part of the common line 20. [ The pixel contact hole 51 may include a first pixel contact hole 51a, a second pixel contact hole 51b, and a third pixel contact hole 51c. The pixel contact hole 51 may be formed in a direction parallel to the data line 30. [ The first pixel contact hole 51a, the second pixel contact hole 51b and the third pixel contact hole 51c may be spaced apart from each other and may be formed in a direction parallel to the data line 30.

The pixel contact hole 51 may expose the drain electrode 33 or the gate insulating film 3 through the protective layer 5. [ The drain electrode 33 is exposed through the pixel contact hole 51 in the region where the pixel contact hole 51 overlaps with the drain electrode 33 and the remaining region is exposed through the pixel contact hole 51 The gate insulating film 3 can be exposed.

The common contact hole 53 may expose the common line 20 through the protective layer 5 and the gate insulating film 3. [

A plurality of pixel electrodes 41 may be formed in the pixel region. The pixel electrode 41 may extend along a direction parallel to the data line 30. The plurality of pixel electrodes 41 may be spaced apart from each other. One side region of the plurality of pixel electrodes 41 may be electrically connected to the drain electrode 33 in contact therewith. The plurality of pixel electrodes 41 may be formed on the pixel contact holes 51. The first pixel electrode 41a may be formed on the drain electrode 33 exposed by the first pixel contact hole 51a and the gate insulating film 3 and the second pixel electrode 41b may be formed on the second The third pixel electrode 41c may be formed on the drain electrode 33 exposed by the pixel contact hole 51b and on the gate insulating film 3 and the third pixel electrode 41c may be exposed by the third pixel contact hole 51c The drain electrode 33 and the gate insulating film 3, respectively. A part of the pixel electrode 41 may be electrically connected to the drain electrode 33 and the remaining part of the pixel electrode 41 may be formed on the gate insulating layer 3.

A common electrode 43 may be formed in the pixel region. The common electrode 43 may include a plurality of vertical portions 44 and a horizontal portion 45. One end of the plurality of vertical portions 44 may be connected to the horizontal portion 45. The plurality of vertical portions 44 and the horizontal portions 45 may be integrally formed.

The plurality of vertical portions 44 may be formed on the protective layer 5. The plurality of vertical portions 44 may be formed on the protective layer 5 between each pixel contact hole 51. [ The vertical portion 44 may include first to third vertical portions 44a to 44c. The first vertical portion 44a may be formed between the first pixel contact hole 51a and the second pixel contact hole 51b. The second vertical portion 44b may be formed between the second pixel contact hole 51b and the third pixel contact hole 51c. The third vertical portion 44c may be formed on the passivation layer 5 adjacent to the third pixel contact hole 51c. The plurality of vertical portions 44 may be formed alternately with the plurality of pixel electrodes 41.

The plurality of vertical portions 44 and the plurality of pixel electrodes 41 may be formed on different layers to reduce a distance between the plurality of vertical portions 44 and the plurality of pixel electrodes 41, The efficiency can be increased and the transmittance can be improved.

The horizontal portion 45 may be formed in a direction parallel to the common line 20. The horizontal portion 45 may be electrically connected to the common line 20 through the common contact hole 53.

5 is a view illustrating a method of manufacturing a thin film transistor substrate of a liquid crystal display panel according to a first embodiment of the present invention.

Referring to FIG. 5A, the thin film transistor substrate of the liquid crystal display panel according to the first embodiment may have a gate line 10, a gate electrode 11, and a common line 20 formed on a substrate 1.

The gate line 10 may be electrically connected to the gate electrode 11. The gate line 10 may be formed integrally with the gate electrode 11.

The gate line 10, the gate electrode 11, and the common line 20 may be formed of a gate metal. The gate metal may be at least one selected from the group consisting of Ti, Cr, Ni, Al, Pt, Au, W, Cu, Group. ≪ / RTI >

The gate insulating film 3 may be formed on the substrate 1 on which the gate line 10, the gate electrode 11 and the common line 20 are formed. The gate insulating layer 3 is required to have an insulating property as a layer for electrically isolating the gate line 10, the gate electrode 11 and the common line 20 from other wirings and electrodes, and a silicon nitride (SiNx) An inorganic insulating material such as silicon oxide (SiOx), or an organic insulating material such as BCB (benzocyclobutene).

Referring to FIG. 5B, a semiconductor layer 35 may be formed on the thin film transistor region of the gate insulating film 3. FIG. The semiconductor layer 35 may include a channel region and source and drain regions formed on both sides of the channel region.

The data line 30, the source electrode 31 and the drain electrode 33 may be formed on the gate insulating film 3 on which the semiconductor layer 35 is formed. The data line 30 may be formed integrally with the source electrode 31. The source electrode 31 may be formed on the source region of the semiconductor layer 35 and the drain electrode 33 may be formed on the drain region of the semiconductor layer 35.

The data line 3, the source electrode 31, and the drain electrode 33 may be formed of data metal. The data metal may be at least one selected from the group consisting of Ti, Cr, Ni, Al, Pt, Au, W, Cu, Group. ≪ / RTI >

Referring to FIG. 5C, a protective layer 5 may be formed on the gate insulating layer 3 on which the data line 3, the source electrode 31, and the drain electrode 33 are formed. The protective layer 5 is a layer for electrically isolating the data line 3, the source electrode 31 and the drain electrode 33 from the other wirings and the electrodes and is required to have an insulating property such as silicon nitride (SiNx) An inorganic insulating material such as silicon oxide (SiOx), or an organic insulating material such as BCB (benzocyclobutene).

Referring to FIG. 5D, a pixel contact hole 51 and a common contact hole 53 may be formed in the passivation layer 5.

The pixel contact hole 51 may expose the drain electrode 33 or the gate insulating layer 3 through the passivation layer 5. A region of the pixel contact hole 51 which overlaps with the drain electrode 33 may expose the drain electrode 33 and the remaining region may expose the gate insulating layer 3. The pixel contact hole 51 may include first through third pixel contact holes 51a through 51c. The first through third pixel contact holes 51a through 51c may be spaced apart from each other.

The common contact hole 53 may expose the common line 20 through the protective layer 5 and the gate insulating layer 3.

Referring to FIG. 5E, the pixel electrode 41 may be formed on the drain electrode 33 and the gate insulating film 3 where the pixel contact hole 51 is formed. The first pixel electrode 41a may be formed on the drain electrode 33 and the gate insulating film 3 exposed by the first pixel contact hole 51a and exposed by the second pixel contact hole 51b. The second pixel electrode 41b may be formed on the drain electrode 33 and the gate insulating film 3 and the drain electrode 33 exposed by the third pixel contact hole 51c and the gate insulating film 3, a third pixel electrode 41c may be formed. A portion of the pixel electrode 41 may be electrically connected to the drain electrode 33.

A common electrode 43 may be formed in the pixel region. The common electrode 43 may include a plurality of vertical portions 44 and horizontal portions 45.

A plurality of vertical portions 44 may be formed on the passivation layer 5 located between the pixel contact holes 51. The vertical portion 44 may include first to third vertical portions 44a to 44c. The first vertical portion 44a may be formed between the first pixel contact hole 51a and the second pixel contact hole 51b. The second vertical portion 44b may be formed between the second pixel contact hole 51b and the third pixel contact hole 51c. The second vertical portion 44c may be formed on the passivation layer 5 adjacent to the third pixel contact hole 51c. The plurality of vertical portions 44 may be formed alternately with the plurality of pixel electrodes 41.

The horizontal portion 45 is formed on the common contact hole 53 and is electrically connected to the common line 20. [

The pixel electrode 41 and the common electrode 45 may be formed of a transparent conductive material. The pixel electrode 41 and the common electrode 45 may be formed of ITO or ITZO material.

The pixel electrode 41 and the common electrode 45 may be formed in the same process. The pixel electrode 41 and the common electrode 45 can be formed in the same process so that the mask can be reduced, thereby reducing manufacturing cost.

The pixel electrode 41 may be formed in the same process as the vertical portion 44. When the transparent conductive material is applied on the protection layer 5 of the pixel region, the vertical portion 44 is formed on the protection layer 5 and the pixel contact hole 51 is formed in the region where the pixel contact hole 51 is formed. The pixel electrode 41 may be formed on the pixel electrodes 41 and 51. The pixel electrodes 41 and the vertical portions 44 can be formed on different layers using the pixel contact holes 51 and the interval between the pixel electrodes 41 and the vertical portions 44 can be reduced. In other words, the interval between the pixel electrode 41 and the common electrode 45 can be reduced. The gap between the pixel electrode 41 and the common electrode 45 is reduced to improve the operation efficiency of the liquid crystal, thereby improving the image quality by improving the transmittance.

6 is a cross-sectional view of the thin film transistor substrate of the liquid crystal display panel according to the second embodiment of the present invention taken along line A-A ', line B-B', and line C-C '.

The thin film transistor substrate of the liquid crystal display panel according to the second embodiment is the same as the thin film transistor substrate of the liquid crystal display panel according to the first embodiment except that it has a plurality of protective layers. Therefore, in describing the second embodiment, detailed description of the same portions as those of the first embodiment will be omitted.

6, a thin film transistor substrate of a liquid crystal display panel according to a second embodiment of the present invention includes a substrate 101, a plurality of gate lines 110, and a plurality of gate lines 110, A line 120 is formed. The common line 120 may be formed in an area adjacent to an adjacent gate line. And a gate electrode 111 may be formed to extend to the gate line 110.

A gate insulating layer 103 may be formed on the gate line 110 and the common line 120. A semiconductor layer 135 may be formed on the thin film transistor region on the gate insulating layer 103. The semiconductor layer 135 may include a channel region and source and drain regions formed on both sides of the channel region.

A source electrode 131 extending from the data line may be formed on the source region. The source electrode 131 may be formed integrally with the data line 130. A drain electrode 133 may be formed on the drain region. The drain electrode 133 may extend from the drain region to the adjacent data line. The drain electrode 133 may be formed in a direction parallel to the gate line 110 in a region adjacent to the gate line 110.

The gate electrode 111, the source electrode 131, the drain electrode 133 and the semiconductor layer 135 constitute a thin film transistor T.

A protective layer 105 may be formed on the gate insulating layer 103 on which the source electrode 131 and the drain electrode 133 are formed. The protective layer 105 may include a first protective layer 105a and a second protective layer 105b. The first passivation layer 105a and the second passivation layer 105b may be sequentially stacked. The first passivation layer 105a and the second passivation layer 105b may have different etch rates (ER). The first passivation layer 105a and the second passivation layer 105b may be formed of materials having different etching rates. The protective layer 105 may be applied by a chemical vapor deposition (CVD) method. In the chemical vapor deposition method, a deposition gas may be introduced. The deposition gas may be a mixed gas of N2 / SiH4, NH3 / SiH4 or SiH4 / N2O. The first passivation layer 105a and the second passivation layer 105b having different etching rates can be formed by controlling the composition ratio of the deposition gas used when the passivation layer 105 is deposited. The etch rate of the first passivation layer 105a may be higher than the etch rate of the second passivation layer 105b.

A pixel contact hole 151 may be formed in the protection layer 105 of the pixel region and a common contact hole 153 may be formed in the protection layer 105 of a part of the common line 20. [

The etching rate of the first passivation layer 105a is higher than the etching rate of the second passivation layer 105b when the pixel contact hole 151 is formed so that the first passivation layer 105a has a higher etching rate than the second passivation layer 105b A reverse taper phenomenon occurs in which the etched surface has an inclination.

A plurality of pixel electrodes 141 may be formed in the pixel region. One side of the plurality of pixel electrodes 141 may be electrically connected to the drain electrode 133. The plurality of pixel electrodes 141 may be formed on the pixel contact holes 151. The first pixel electrode 141a may be formed in the first pixel contact hole 151a and the second pixel electrode 141b may be formed in the second pixel contact hole 151b. The electrode 141c may be formed in the third pixel contact hole 151c. A part of the pixel electrode 141 may be electrically connected to the drain electrode 133 and the remaining part of the pixel electrode 141 may be formed on the gate insulating layer 103.

A common electrode 143 may be formed in the pixel region. The common electrode 143 may include a plurality of vertical portions 144 and a horizontal portion 145. One end of the plurality of vertical portions 144 may be connected to the horizontal portion 145. The plurality of vertical portions 144 and the horizontal portions 145 may be integrally formed.

The plurality of vertical portions 144 may be formed on the passivation layer 105. The plurality of vertical portions 144 may be formed on the second passivation layer 105b. The plurality of vertical portions 144 may be formed on the passivation layer 105 between each pixel contact hole 151. The vertical portion 144 may include first to third vertical portions 144a to 144c. The first vertical portion 144a may be formed between the first pixel contact hole 151a and the second pixel contact hole 151b. The second vertical portion 144b may be formed between the second pixel contact hole 151b and the third pixel contact hole 151c. The third vertical portion 144c may be formed on the passivation layer 105 adjacent to the third pixel contact hole 151c. The plurality of vertical portions 144 may be formed alternately with the plurality of pixel electrodes 141.

A reverse taper phenomenon occurs when the pixel contact hole 151 is formed through the first passivation layer 105a and the second passivation layer 105b having different etch rates, The separation can be facilitated. Since the transparent conductive material forming the pixel electrode 141 and the common electrode vertical portion 144 has high viscosity and can be electrically connected even if they are formed on different layers, an etching surface having an inclination due to the reverse taper phenomenon is formed So that the pixel electrode 141 and the vertical part 144 are efficiently separated from each other.

The vertical part 144 and the pixel electrode 141 are formed on different layers and the interval between the vertical part 144 and the pixel electrode 141 can be reduced to increase the operation efficiency of the liquid crystal, There is an effect of improvement.

7 is a graph showing the transmittance of the liquid crystal display panel according to the second embodiment.

7 is a graph showing the transmittance according to the voltage change when the distance between the pixel electrode and the vertical portion of the liquid crystal display device according to the second embodiment is 4 m, Is a graph of transmittance according to a voltage change when the distance between the pixel electrode and the vertical part of the device is 8 mu m, and FIG. 3B is a graph showing the transmittance of the pixel electrode in the FFS mode, 4 is a graph showing the transmittance according to the voltage change in the IPS mode according to the prior art, and Fig. 5 is a graph showing the transmittance according to the conventional technique when the common electrode in the FFS mode according to the related art is formed on the upper layer of the pixel electrode And the transmittance according to the voltage change in the structure.

Referring to the graph, it can be seen that the total transmittance of the liquid crystal display according to the second embodiment is higher than that according to the related art. In the liquid crystal display device according to the second embodiment, when the distance between the pixel electrode and the vertical part is 4 mu m, the transmittance at the full range voltage is higher than that of the prior art, so that the image quality is improved as compared with the prior art.

8 is a view illustrating a method of manufacturing a thin film transistor substrate of a liquid crystal display panel according to a second embodiment of the present invention.

Referring to FIG. 8A, the thin film transistor substrate of the liquid crystal display panel according to the second embodiment may have a gate line 110, a gate electrode 111, and a common line 120 formed on a substrate 101. The gate insulating film 103 may be formed on the substrate 101 on which the gate line 110, the gate electrode 111 and the common line 120 are formed.

Referring to FIG. 8B, a semiconductor layer 135 may be formed on the thin film transistor region of the gate insulating layer 103. The semiconductor layer 135 may include a channel region and source and drain regions formed on both sides of the channel region.

A data line 130, a source electrode 131 and a drain electrode 133 may be formed on the gate insulating layer 103 on which the semiconductor layer 135 is formed.

Referring to FIG. 8C, a protective layer 105 may be formed on the gate insulating layer 103 on which the data line 103, the source electrode 131, and the drain electrode 133 are formed. The protective layer 105 may include a first protective layer 105a and a second protective layer 105b. The first passivation layer 105a and the second passivation layer 105b may be sequentially stacked on the gate insulating layer 103 on which the data line 103, the source electrode 131 and the drain electrode 133 are formed . The first passivation layer 105a and the second passivation layer 105b may have different etch rates. After the first passivation layer 105a is formed, a second passivation layer 105b having an etch rate different from that of the first passivation layer 105a may be formed. Alternatively, when the protective layer 105 is deposited by an image vapor deposition method, a first protective layer 105a and a second protective layer 105b having different etching rates are formed by controlling a composition ratio of a deposition gas used for deposition can do. The etch rate of the first passivation layer 105a may be higher than the etch rate of the second passivation layer 105b.

Referring to FIG. 8D, a pixel contact hole 151 and a common contact hole 153 may be formed in the passivation layer 105.

The pixel contact hole 151 may expose the drain electrode 133 or the gate insulating layer 103 through the passivation layer 105. A region of the pixel contact hole 151 overlapping the drain electrode 133 may expose the drain electrode 133 and the remaining region may expose the gate insulating layer 103. The pixel contact hole 151 may include first to third pixel contact holes 151a to 151c. The first through third pixel contact holes 151a through 151c may be spaced apart from each other.

The etching rate of the first passivation layer 105a is higher than the etching rate of the second passivation layer 105b when the pixel contact hole 151 is formed so that the first passivation layer 105a has a higher etching rate than the second passivation layer 105b A reverse taper phenomenon occurs in which the etched surface has an inclination.

The common contact hole 153 may expose the common line 120 through the passivation layer 105 and the gate insulating layer 103.

Referring to FIG. 8E, the pixel electrode 141 may be formed on the drain electrode 133 and the gate insulating layer 103 where the pixel contact hole 151 is formed. The first pixel electrode 141a may be formed on the drain electrode 133 and the gate insulating film 103 exposed by the first pixel contact hole 151a and may be exposed by the second pixel contact hole 151b. A second pixel electrode 141b may be formed on the drain electrode 133 and the gate insulating film 103 and the drain electrode 133 and the gate insulating film exposed by the third pixel contact hole 151c The third pixel electrode 141c may be formed on the second pixel electrode 103. [ A portion of the pixel electrode 141 may be electrically connected to the drain electrode 133.

A common electrode 143 may be formed in the pixel region. The common electrode 143 may include a plurality of vertical portions 144 and a horizontal portion 145.

A plurality of vertical portions 144 may be formed on the passivation layer 105 located between the pixel contact holes 151. The vertical portion 144 may include first to third vertical portions 144a to 144c. The first vertical portion 144a may be formed between the first pixel contact hole 151a and the second pixel contact hole 151b. The second vertical portion 144b may be formed between the second pixel contact hole 151b and the third pixel contact hole 151c. The second vertical portion 144c may be formed on the passivation layer 105 adjacent to the third pixel contact hole 151c. The plurality of vertical portions 144 may be formed alternately with the plurality of pixel electrodes 141.

The horizontal portion 145 is formed on the common contact hole 153 and is electrically connected to the common line 220.

The pixel electrode 141 and the common electrode 145 may be formed by the same process. The pixel electrode 141 and the common electrode 145 can be formed in the same process so that the mask can be reduced, thereby reducing manufacturing cost.

The pixel electrode 141 may be formed in the same process as the vertical portion 144. When the transparent conductive material is applied on the protection layer 105 of the pixel region, the vertical portion 144 is formed on the protection layer and the pixel electrode 141 is formed in the region where the pixel contact hole 151 is formed. have. A reverse taper phenomenon occurs when the pixel contact hole 151 is formed through the first passivation layer 105a and the second passivation layer 105b having different etch rates, The separation can be facilitated.

9 is a plan view of a thin film transistor substrate of a liquid crystal display panel according to a third embodiment of the present invention.

10 is a cross-sectional view of a thin film transistor substrate of a liquid crystal display panel according to a third embodiment of the present invention, taken along line A-A ', line B-B', and line C-C '.

The thin film transistor substrate of the liquid crystal display panel according to the third embodiment is the same as the thin film transistor substrate except that the lower pixel electrode is added as compared with the second embodiment. Therefore, in describing the third embodiment, a detailed description of parts common to the second embodiment will be omitted.

9 and 10, the thin film transistor substrate of the liquid crystal display panel according to the third embodiment includes a plurality of gate lines 210 on a substrate 201, and a plurality of gate lines 210 parallel to the plurality of gate lines 210 22 are formed. A gate electrode 211 may be formed to extend to the gate line 210.

A gate insulating layer 203 may be formed on the gate line 210 and the common line 220. A semiconductor layer 235 may be formed on the thin film transistor region on the gate insulating layer 203. The semiconductor layer 235 may include a channel region and source and drain regions formed on both sides of the channel region.

A plurality of data lines 230 may be formed on the gate insulating layer 203 in a direction crossing the gate lines 210. An intersection pixel region of the plurality of gate lines 201 and the plurality of data lines 230 may be defined. A source electrode 231 extending from the data line 230 may be formed on the source region. A drain electrode 233 may be formed on the drain region.

The gate electrode 211, the source electrode 231, the drain electrode 233 and the semiconductor layer 235 constitute a thin film transistor T.

The lower pixel electrode 240 may be formed in the pixel region. The lower pixel electrode 240 may be overlapped with a portion of the drain electrode 233. A portion of the lower pixel electrode 240 may be formed in contact with the drain electrode 233. A portion of the lower pixel electrode 240 may be electrically connected to the drain electrode 233.

A protective layer 205 may be formed on the data line 230. The passivation layer 205 may include a first passivation layer 205a and a second passivation layer 205b having different etching rates.

A pixel contact hole 251 may be formed in the protection layer 205 of the pixel region and a common contact hole 253 may be formed in the protection layer 205 of a part of the common line 220. The pixel contact hole 251 may include a first pixel contact hole 251a, a second pixel contact hole 251b, and a third pixel contact hole 251c. The pixel contact hole 251 may be formed along a direction parallel to the data line 230. The first, second, and third pixel contact holes 251a, 251b, and 251c may be spaced apart from each other and may extend along a direction parallel to the data line 230.

The pixel contact hole 251 may expose the lower pixel electrode 240 through the passivation layer 205. The pixel electrode 241 may be formed on the lower pixel electrode 240 exposed by the pixel contact hole 251. The lower pixel electrode 240 may be electrically connected to the pixel electrode 241. The pixel electrode 241 may include first to third pixel electrodes 241a to 241c. The first pixel electrode 241 a may be formed on the lower pixel electrode 240 exposed by the first pixel contact hole 251. The second pixel electrode 241b may be formed on the lower pixel electrode 240 exposed by the second pixel contact hole 251b. The third pixel electrode 241c may be formed on the lower pixel electrode 240 exposed by the third pixel contact hole 251c.

A common electrode 243 may be formed in the pixel region. The common electrode 243 may include a plurality of vertical portions 244 and a horizontal portion 245. One end of the plurality of vertical portions 244 may be connected to the horizontal portion 245. The plurality of vertical portions 244 and the horizontal portion 245 may be integrally formed.

The plurality of vertical portions 244 may be formed on the passivation layer 205. The plurality of vertical portions 244 may be formed on the passivation layer 205 between each pixel contact hole 251. The vertical portion 244 may include first through third vertical portions 244a through 244c. The first vertical portion 244a may be formed between the first pixel contact hole 251a and the second pixel contact hole 251b. The second vertical portion 244b may be formed between the second pixel contact hole 251b and the third pixel contact hole 251c. The third vertical portion 244c may be formed on the passivation layer 205 adjacent to the third pixel contact hole 251c. The plurality of vertical portions 244 may be formed alternately with the plurality of pixel electrodes 241.

The plurality of vertical portions 244 are formed to overlap with the lower pixel electrode 240 with the protective layer 205 interposed therebetween. The plurality of vertical portions 244 and the lower pixel electrode 240 are overlapped to form a storage capacitor. The charge capacities of the charges applied to the pixel electrodes 241 are increased by the storage capacitors of the plurality of vertical portions 244 and the lower pixel electrodes 240 to smooth the maintenance of the voltage, have.

The common contact hole 253 may expose the common line 220 through the passivation layer 205 and the gate insulating layer 203.

The horizontal portion 245 may be formed in a direction parallel to the common line 220. The horizontal portion 425 may be electrically connected to the common line 220 through the common contact hole 253.

11 is a view illustrating a method of manufacturing a thin film transistor substrate of a liquid crystal display panel according to a third embodiment of the present invention.

Referring to FIG. 11A, the thin film transistor substrate of the liquid crystal display panel according to the third embodiment may have a gate line 210, a gate electrode 211, and a common line 220 formed on a substrate 201. The gate insulating layer 203 may be formed on the substrate 201 on which the gate line 210, the gate electrode 211 and the common line 220 are formed.

Referring to FIG. 11B, a semiconductor layer 235 may be formed on the thin film transistor region of the gate insulating layer 203. The semiconductor layer 235 may include a channel region and source and drain regions formed on both sides of the channel region.

A data line 230, a source electrode 231 and a drain electrode 233 may be formed on the gate insulating layer 203 on which the semiconductor layer 235 is formed.

The lower pixel electrode 240 may be formed in the pixel region on the gate insulating layer 203 on which the drain electrode 233 is formed. A portion of the lower pixel electrode 240 may overlap with the drain electrode 233. A portion of the lower pixel electrode 240 may be in contact with the drain electrode 233 to be electrically connected. The lower pixel electrode 240 may be formed of a transparent conductive material. The lower pixel electrode 240 may be formed of ITO, IZO or ITZO material.

Referring to FIG. 11C, the data line 203 and the source electrode 231 are formed. A protective layer 205 may be formed on the gate insulating layer 203 on which the drain electrode 233 and the lower pixel electrode 240 are formed. The passivation layer 205 may include a first passivation layer 205a and a second passivation layer 205b. The first passivation layer 205a and the second passivation layer 205b are formed on the gate insulating layer 203 on which the data line 203, the source electrode 231, the drain electrode 133 and the lower pixel electrode 240 are formed. As shown in FIG. The first passivation layer 205a and the second passivation layer 205b may have different etch rates. After the first passivation layer 205a is formed, a second passivation layer 205b having an etch rate different from that of the first passivation layer 205a may be formed. Alternatively, when the protective layer 205 is deposited by an image vapor deposition method, a first protective layer 205a and a second protective layer 205b having different etching rates are formed by controlling a composition ratio of a deposition gas used for deposition can do. The etch rate of the first passivation layer 205a may be higher than the etch rate of the second passivation layer 205b.

Referring to FIG. 11D, a pixel contact hole 251 and a common contact hole 253 may be formed in the passivation layer 205.

The pixel contact hole 251 may expose the lower pixel electrode 240 through the passivation layer 205. The pixel contact hole 251 may include first through third pixel contact holes 251a through 251c. The first through third pixel contact holes 251a through 251c may be spaced apart from each other.

The etch rate of the first passivation layer 205a is higher than the etch rate of the second passivation layer 205b when the pixel contact hole 251 is formed so that the first passivation layer 205a is higher than the second passivation layer 205b A reverse taper phenomenon occurs in which the etched surface has an inclination.

The common contact hole 253 may expose the common line 220 through the passivation layer 205 and the gate insulating layer 203.

Referring to FIG. 11E, a pixel electrode 241 may be formed on the lower pixel electrode 240 on which the pixel contact hole 251 is formed. The first pixel electrode 241a may be formed on the lower pixel electrode 240 exposed by the first pixel contact hole 251a and the first pixel electrode 241a may be formed on the lower pixel electrode 240 exposed by the second pixel contact hole 251b. The second pixel electrode 241b may be formed on the lower pixel electrode 240 and the third pixel electrode 241c may be formed on the lower pixel electrode 240 exposed by the third pixel contact hole 251c . The pixel electrode 241 may be electrically connected to the lower pixel electrode 240.

A common electrode 243 may be formed in the pixel region. The common electrode 243 may include a plurality of vertical portions 244 and a horizontal portion 245.

A plurality of vertical portions 244 may be formed on the passivation layer 205 located between the pixel contact holes 251. The vertical portion 244 may include first through third vertical portions 244a through 244c. The first vertical portion 244a may be formed between the first pixel contact hole 251a and the second pixel contact hole 251b. The second vertical portion 244b may be formed between the second pixel contact hole 251b and the third pixel contact hole 251c. The second vertical portion 244c may be formed on the passivation layer 205 adjacent to the third pixel contact hole 251c. The plurality of vertical portions 244 may be formed alternately with the plurality of pixel electrodes 241. The plurality of vertical portions 244 are formed to overlap with the lower pixel electrode 240 with the protective layer 205 interposed therebetween. The plurality of vertical portions 244 and the lower pixel electrode 240 are overlapped to form a storage capacitor.

The horizontal portion 245 is formed on the common contact hole 253 and is electrically connected to the common line 220.

The pixel electrode 241 may be formed in the same process as the vertical portion 244. When the transparent conductive material is applied on the protection layer 205 of the pixel region, the vertical portion 244 is formed on the protection layer and the pixel electrode 241 is formed in the region where the pixel contact hole 251 is formed. have. A reverse taper phenomenon occurs when the pixel contact hole 251 is formed through the first passivation layer 205a and the second passivation layer 205b having different etch rates to form a plurality of pixel electrodes 241 and a vertical portion 244 The separation can be facilitated.

12 is a plan view of a thin film transistor substrate of a liquid crystal display panel according to a fourth embodiment of the present invention.

FIG. 13 is a cross-sectional view of a thin film transistor substrate of a liquid crystal display panel according to a fourth embodiment of the present invention taken along the line A-A ', the line B-B', and the line C-C '.

The thin film transistor substrate of the liquid crystal display panel according to the fourth embodiment is the same as the thin film transistor substrate of the first embodiment except that the common electrode is formed on the entire surface of the protective layer. Therefore, in the description of the fourth embodiment, detailed description of the parts common to the first embodiment will be omitted.

12 and 13, the thin film transistor substrate of the liquid crystal display panel according to the fourth embodiment includes a plurality of gate lines 310 formed on a substrate 301, a gate electrode 311 extending to the gate lines, Can be formed.

A gate insulating layer 303 may be formed on the gate line 310. A semiconductor layer 335 may be formed on the thin film transistor region on the gate insulating film 303.

The semiconductor layer 235 may include a channel region and source and drain regions formed on both sides of the channel region.

A plurality of data lines 330 may be formed on the gate insulating layer 303 in a direction crossing the gate lines 310. An intersection pixel region of the plurality of gate lines 301 and the plurality of data lines 330 may be defined. A source electrode 331 extending from the data line 330 may be formed on the source region. A drain electrode 333 may be formed on the drain region.

The gate electrode 311, the source electrode 331, the drain electrode 333 and the semiconductor layer 335 constitute a thin film transistor T.

A protective layer 305 may be formed on the data line 330.

A plurality of pixel contact holes 351 may be formed in the passivation layer 305 of the pixel region.

The pixel contact hole 351 may include a first pixel contact hole 351a, a second pixel contact hole 351b, and a third pixel contact hole 351c. The pixel contact hole 351 may be formed along a direction parallel to the data line 330. The first pixel contact hole 351a, the second pixel contact hole 351b, and the third pixel contact hole 351c may be spaced apart from each other and may extend along a direction parallel to the data line 330.

The pixel contact hole 351 may expose the drain electrode 333 through the passivation layer 305. The pixel electrode 341 may be formed on the drain electrode 333 exposed by the pixel contact hole 351. [ The pixel electrode 341 may be electrically connected to the drain electrode 333. The pixel electrode 341 may include first to third pixel electrodes 341a to 341c. The first pixel electrode 341a may be formed on the drain electrode 333 exposed by the first pixel contact hole 351a. The second pixel electrode 341b may be formed on the drain electrode 333 exposed by the second pixel contact hole 351b. The third pixel electrode 341c may be formed on the drain electrode 333 exposed by the third pixel contact hole 351c.

A common electrode 343 may be formed on the entire region of the passivation layer 305. The common electrode 343 may be formed in the entire region excluding the pixel contact hole 351. The common electrode 343 may be formed in the entire region of the protective layer 305 to apply a common voltage to the common electrode 343 at the edge of the liquid crystal display panel to drive the liquid crystal display device. A common voltage can be applied only to the common electrode 343, and a separate common line can be omitted. There is an effect that the aperture ratio of the liquid crystal display panel can be whitened by omitting formation of the common line formed of the gate metal.

1, 101, 201, 301: substrate 3, 103, 203, 303:
5,105,205,305: Protective layer 10,110,210,310: Gate line
11, 111, 211, 311: gate electrodes 20, 120, 220,
30, 130, 230, 330: Data line 31, 131, 231, 331:
33, 133, 233, 333: drain electrode 35, 135, 235, 335:
41, 141, 241, 341: pixel electrodes 43, 143, 243, 343:
51, 151, 251, 351: Pixel contact holes 53, 153, 253, 353:

Claims (22)

A gate line and a data line formed to intersect with each other to define a pixel region;
A thin film transistor connected to the gate line and the data line;
A plurality of pixel electrodes formed on the drain electrode of the thin film transistor;
A common electrode alternately formed with the plurality of pixel electrodes; And
A protective layer formed between the pixel electrode and the common electrode,
The pixel electrode and the common electrode are formed in one process. The method of claim 1,
And the plurality of pixel electrodes are formed on the drain electrode exposed by the plurality of pixel contact holes penetrating the protective layer. 3. The method of claim 2,
Wherein the protective layer comprises a first protective layer and a second protective layer having different etching rates. The method of claim 3,
Wherein the first protective layer and the second protective layer are sequentially stacked,
Wherein the first protective layer has a higher etch rate than the second protective layer. 5. The method of claim 4,
Wherein the pixel contact hole has a slope in a direction from the second passivation layer toward the first passivation layer. The method of claim 3,
The first protective layer and the second protective layer is a liquid crystal display panel for controlling the mixing ratio of the deposition gas used when forming the protective layer to have a different etching rate. The method of claim 1,
The drain electrode is formed in the pixel area along the gate line direction. The method of claim 1,
And a common line formed in a direction parallel to the gate line,
Wherein the common electrode comprises:
A horizontal portion overlapping the common line; And
And a plurality of vertical parts connected to the horizontal part and alternately formed with the plurality of pixel electrodes. 9. The method of claim 8,
And the horizontal portion is electrically connected to the common line through a common contact hole. The method of claim 1,
And a lower pixel electrode formed on the pixel area to connect the drain electrode and the plurality of pixel electrodes. 3. The method of claim 2,
Wherein the common electrode is formed in the entire region of the protective layer except for the pixel contact hole. Forming a gate line on the substrate and a gate electrode extending to the gate line;
Forming a gate insulating film and a semiconductor layer on the substrate on which the gate line is formed;
Forming a data line, a source electrode and a drain electrode on the gate insulating film;
Forming a protective layer on the gate insulating layer on which the data line, the source electrode and the drain electrode are formed;
Forming a plurality of pixel contact holes in the protective layer; And
Forming a plurality of pixel electrodes and a common electrode by applying a transparent conductive material on the pixel contact hole and the protective layer. 13. The method of claim 12,
And the plurality of pixel electrodes are formed on the drain electrode exposed by the plurality of pixel contact holes penetrating the protective layer. 13. The method of claim 12,
The step of forming the protective layer may include:
And sequentially forming a first protective layer and a second protective layer having different etching rates. 15. The method of claim 14,
Wherein the first passivation layer has a higher etch rate than the second passivation layer. 16. The method of claim 15,
Wherein the pixel contact hole has a slope from the second passivation layer to the first passivation layer. 15. The method of claim 14,
The protective layer is formed by chemical vapor deposition,
Wherein the first protective layer and the second protective layer adjust deposition gas mixture ratios to have different etch rates. 13. The method of claim 12,
The drain electrode is formed in the pixel area along the gate line direction. 13. The method of claim 12,
Forming a common line parallel to the gate line with the gate line,
Wherein the common electrode comprises:
A horizontal portion overlapping the common line; And
A method of manufacturing a liquid crystal display panel including a plurality of vertical parts connected to the horizontal part and alternately formed with the plurality of pixel electrodes. 20. The method of claim 19,
Forming a common contact hole together with the pixel contact hole,
And the horizontal portion is electrically connected to the common line through a common contact hole. 13. The method of claim 12,
After forming a data line, a source electrode and a drain electrode on the gate insulating film, forming a lower pixel electrode in the pixel region to connect the drain electrode and the plurality of pixel electrodes further comprising the step of forming a liquid crystal display panel. . 14. The method of claim 13,
Wherein the common electrode is formed in the entire region of the protective layer except for the pixel contact hole.

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