KR20140039540A - Semiconductor package and method of forming the same - Google Patents

Abstract

Provided are a semiconductor package and a manufacturing method thereof. The semiconductor package comprises a package substrate; a semiconductor chip which is separated from the package substrate at constant intervals; and a remaining adhesive unit which is positioned between the package substrate and the semiconductor chip. The method for manufacturing the semiconductor package comprises forming adhesive units by using a dispensing process and/or a roll-to-roll process. The adhesive units temporarily bonds the semiconductor chip and the substrate to reduce time for positioning the semiconductor chip above the substrate. The semiconductor chip is positioned to be distant from the substrate at constant intervals by the adhesive units. The remaining adhesive unit can be formed by the adhesive units through a reflow process. According to the present invention, the method for manufacturing a semiconductor package can shorten the total processing time (TAT).

Description

Semiconductor package and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor, and more particularly, to a semiconductor package and a manufacturing method thereof.

BACKGROUND OF THE INVENTION In accordance with the high density and high integration of semiconductor integrated circuits used in electronic devices, the pinning and narrow pitch of electrode terminals of semiconductor chips are rapidly progressing. The semiconductor device generally has an electrical connection structure such as solder balls or bumps in order to be electrically connected to other semiconductor devices or printed circuit boards. In the method of manufacturing a semiconductor package, a more reliable and simple flip chip bonding mounting method has been studied in various ways.

An object of the present invention is to provide a reliable semiconductor package.

Another object of the present invention is to provide a method of manufacturing a semiconductor package with a shortened total processing time (TAT).

The present invention relates to a semiconductor package and a manufacturing method thereof. In an embodiment, the semiconductor package may include a package substrate, a semiconductor chip mounted on the package substrate, a bump interposed between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate, and the package. An underfill film filled between the substrate and the semiconductor chip, and the remaining adhesive portion provided in the underfill film.

According to one embodiment, the remaining adhesive portion may have a particle shape.

In example embodiments, the remaining adhesive part may have a height equal to or lower than a distance between the substrate and the semiconductor chip.

In example embodiments, the semiconductor chip may be spaced apart from the package substrate at regular intervals.

According to an embodiment, a method of manufacturing a semiconductor package may include providing a substrate, forming adhesive parts on the substrate, and fixing a semiconductor chip including bumps to the substrate by the adhesive parts on the substrate. And reflowing the bumps to electrically connect the semiconductor chip to the substrate, and filling the gap between the substrate and the semiconductor chip to form an underfill film.

According to an embodiment, the method may include removing some of the adhesive parts by the reflow to form a residual adhesive part.

According to one embodiment, forming the adhesive portions may include applying an adhesive solution to a printing roll surface to form an adhesive dot, and transferring the adhesive dot on the printing roll surface onto the package substrate. .

According to one embodiment, forming the adhesive portions may include applying an adhesive to have a pattern on the substrate by a dispenser.

According to an embodiment, providing the substrate may further include loading the substrate on a carrier, and may further include separating the substrate from the carrier after forming the underfilling film.

The semiconductor package according to the present invention may include a substrate, a semiconductor chip spaced apart from the substrate at regular intervals, and a residual adhesive portion provided between the substrate and the semiconductor chip. Thus, the reliability of the semiconductor package can be improved.

The method of manufacturing a semiconductor package according to the present invention may form adhesive parts on a substrate. The adhesive parts may temporarily bond and fix the semiconductor chip and the substrate to shorten the time for mounting the semiconductor chip on the substrate. Accordingly, the total processing time TAT may be shortened in the semiconductor package manufacturing process. By the adhesive parts, the semiconductor chip may be mounted at regular intervals from the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding and assistance of the invention, reference is made to the following description, taken together with the accompanying drawings,
1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.
8 illustrates an example of a package module including a semiconductor package to which the technology of the present invention is applied.
9 is a block diagram illustrating an example of an electronic device including a semiconductor package to which the technology of the present invention is applied.
10 is a block diagram illustrating an example of a memory system including a semiconductor package to which the technology of the present invention is applied.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof. Those of ordinary skill in the art will understand that the concepts of the present invention may be practiced in any suitable environment.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

When a film (or layer) is referred to herein as being on another film (or layer) or substrate it may be formed directly on another film (or layer) or substrate, or a third film Or layer) may be interposed.

 Although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., it is to be understood that these regions, do. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. Like numbers refer to like elements throughout the specification.

The terms used in the embodiments of the present invention may be construed as commonly known to those skilled in the art unless otherwise defined.

<Example of Semiconductor Package>

1 is a plan view showing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor package 1 may include a package substrate 100, a semiconductor chip 200, and a bump 250. The semiconductor package 1 may be a flip chip package in which the semiconductor chip 200 is face down mounted on the package substrate 100. The underfill layer 300 may be filled between the package substrate 100 and the semiconductor chip 200, and may include a residual adhesive part 450. The semiconductor package 1 may be molded by the molding layer 350.

The package substrate 100 may be a printed circuit package substrate (PCB) having a pattern or a wafer level substrate. The package substrate 100 may include a base substrate 110, an inner pad 120, an insulating layer 130, a through via 140, and / or an external connection terminal 150. The base substrate 110 may include an upper surface 110a and a lower surface 110b that face each other. The base substrate 110 may include silicon, reinforced fiberglass, or epoxy resin. The inner pad 120 may contact the upper surface 110a of the base substrate 110 and include a conductive material. The insulating layer 130 may expose a portion of the inner pad 120. The package substrate 100 may include a through via 140 to reduce the overall size (eg, height) of the semiconductor package 1 and to increase the signal speed. The through via 140 may be provided through the base substrate 110 from the top surface 110a to the bottom surface 110b of the base substrate 100. The through via 140 may include a conductive material (eg, W, Ti, Ni, Cu, Au, Ti / Cu, Ti / Ni, and / or alloys thereof). The through via 140 may electrically connect the inner pad 120 to the external connection terminal 150 on the bottom surface 110b of the base substrate 110. The external connection terminal 150 may include an external pad 151 and / or a solder ball 153 on the external pad 151. The external pad 151 and the solder ball 153 may include a conductive material. The external connection terminal 150 may electrically connect the semiconductor package 1 to an external electric device such as a motherboard.

The semiconductor chip 200 may be a memory or a non-memory chip. The semiconductor chip 200 may include a semiconductor substrate 210, a chip pad 220, and a chip insulating film 230. The semiconductor substrate 210 may be a substrate such as a silicon wafer and / or a SOI wafer. The semiconductor substrate 210 may include integrated circuits such as memory circuits, logic circuits, or a combination thereof. The chip pad 220 may be provided on the semiconductor substrate 210. The chip pad 220 may include a metal material such as copper (Cu) and / or aluminum (Al). The chip insulating layer 230 may be provided on the semiconductor substrate 210. The chip insulating layer 230 may include a pattern exposing a portion of the chip pad 220. The chip insulating layer 230 may include a resin such as photosensitive polyimide (PSPI).

A bump 250 may be interposed between the package substrate 100 and the semiconductor chip 200. The bump 250 may contact the inner pad 120 of the package substrate 100 and the chip pad 220 of the semiconductor chip 200. The bump 250 may have a pillar and / or solder ball shape. The bump 250 may include a conductive material. For example, bump 250 may comprise at least one of copper, lead, tin, indium, bismuth, antimony, silver, and / or alloys thereof. The bump 250 may electrically connect the semiconductor chip 200 to the package substrate 100. For example, the bump 250 may be evenly distributed on the front surface of the package substrate 100 to increase the input / output (I / O) density. As another example, the bump 250 may be arranged at an edge or a center of the package substrate 100. The semiconductor package 1 may have a fine pitch by having the bump 250, have improved mechanical and / or thermal reliability, and may facilitate an easy assembly process (eg, packaging).

The underfill film 300 may be filled between the package substrate 100 and the semiconductor chip 200. The underfill film 300 may be formed of a resin (eg, an epoxy molding compound (EMC)). The underfill layer 300 may protect the package substrate 100 and / or the bumps 250 from a chemical / physical external environment.

The remaining adhesive part 450 may be provided in the underfilling film 300. The remaining adhesive part 450 may include a polymer material (eg, an epoxy resin). The remaining adhesive part 450 may further include a filler. The filler has a grain shape and may serve to adjust the density of the adhesive portion and the like. The remaining adhesive part 450 may have various shapes. For example, the first residual adhesive part 451 may have a particle shape. As another example, the second remaining adhesive part 452 may be in contact with the package substrate 100 and the semiconductor chip 200. The second remaining adhesive part 452 may have the same height as the gap d between the package substrate 100 and the semiconductor chip 200. As another example, the third remaining adhesive portion 453 may be provided on the package substrate 100 to contact the package substrate 100. The third residual adhesive portion 453 may have a first surface 453a and a second surface 453b facing each other. The first surface 453a may be in contact with the package substrate 100, and the second surface 453b may be in contact with the underfill film 300. The fourth remaining adhesive part 454 may be disposed to contact the semiconductor chip 200. The fourth remaining adhesive part 454 includes a third surface 454a in contact with the semiconductor chip 200 and a fourth surface 454b opposite to the third surface 454a and in contact with the underfill film 300. can do. The third remaining adhesive portion 453 and the fourth remaining adhesive portion 454 may have a height smaller than the gap d between the package substrate 100 and the semiconductor chip 200.

<Example of Manufacturing Method of Semiconductor Package>

2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention. Hereinafter, descriptions overlapping with those of FIG. 1 will be omitted.

Referring to FIG. 2, a package substrate 100 may be provided. The base substrate 110 may have an upper surface 110a and a lower surface 110b facing each other. The inner pad 120 may be formed on the top surface 110a of the base substrate 110. The external connection terminal 150 including the external pad 151 and / or the solder ball 153 may be formed on the bottom surface 110b of the base substrate 110. The through via 140 may be formed to penetrate the upper surface 110a and the lower surface 110b of the base substrate 110 to electrically connect the inner pad 120 to the external connection terminal 150. The formation of the through via 140 may include forming a through hole and filling the inside of the through hole. The through hole may be formed by dry etching, wet etching and / or laser processing. The interior of the through hole may be filled with a conductive material (eg, W, Ti, Ni, Cu, Au, Ti / Cu, Ti / Ni and / or alloys thereof). Filling of the through-holes can be carried out by sputtering, chemical vapor deposition and / or electroplating.

Referring to FIG. 3, the package substrate 100 may be loaded on the carrier 500. As an example, the wafer-level package substrate 100 may be attached onto the carrier 500. Alternatively, as another embodiment, the package substrate 100 may be cut and separated into chip sized package substrates 100, and then the respective package substrates 100 may be attached onto the carrier 500. . In this case, each of the chip sized package substrate 100 may be disposed on the carrier 500 at a predetermined interval spaced according to the size of the semiconductor package 1 to be manufactured. The carrier 500 may include at least one of a metal material, a ceramic material, and / or an organic material. The carrier pad 510 may be formed between the package substrate 100 and the carrier 500. The carrier pad 510 may support the package substrate 100 and may mitigate an impact applied to the package substrate 100. The carrier pad 510 may include an ultraviolet curable resin (UV resin) or a thermoplastic resin. When the package substrate 100 is a printed circuit package substrate, the package substrate 100 may not be loaded on the carrier 500.

4A and 4B, adhesive parts 400 may be formed on the package substrate 100. The adhesive parts 400 may be formed to be spaced apart from each other. The adhesive parts 400 may be formed between the inner pads 120 on the package substrate 100 and / or between the inner pads 120 and the ends of the substrate. The adhesive parts 400 may be formed to contact the insulating layer 130. For example, the adhesive parts 400 may be formed by a roll to roll process, as shown in FIG. 4A. Adhesive dots 410 may be provided on the surface of the printing roll 600. Adhesive solution can be prepared. The adhesive solution may comprise a polymeric material. The prepared adhesive solution may be applied to the surface of the printing roll 600 to have a dot pattern. The adhesive dot 410 formed on the surface of the printing roll 600 may be transferred onto the package substrate 100. The adhesive parts 400 may be formed by drying and / or heating the adhesive dot 410 transferred onto the package substrate 100 by a heat treatment process. As another example, the adhesive parts 400 may be formed to have a dot pattern by a dispensing process, as shown in FIG. 4B. For example, the dispenser 700 may discharge the adhesive 420 between the inner pads 120.

Referring to FIG. 5, the semiconductor chip 200 may be disposed on the package substrate 100. The bump 250 of the semiconductor chip 200 may be disposed on a position corresponding to the inner pad 120 of the package substrate 100. The chip insulating layer 230 may be formed on the semiconductor substrate 210 having the chip pads 220. The chip pad 220 may be formed on the semiconductor substrate 210 by deposition and / or plating. The chip pad 220 may be formed from a metal material such as copper (Cu) or aluminum (Al). The chip insulating layer 230 may be formed on the semiconductor substrate 210 to expose a portion of the chip pad 220. The chip insulating layer 230 may include an insulating material (eg, nitride, oxide, polyimide, etc.). The bump 250 may be formed on the chip pad 220. The bump 250 may be formed to have a pillar and / or solder ball shape. The bump 250 may be formed from aluminum (Ag), nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), and / or combinations thereof. Since the semiconductor chip 200 faces down so that the bump 250 faces the package substrate 100, the bump 250 may be positioned on the inner pad 120 of the package substrate 100. The semiconductor chip 200 may be temporarily fixed to the substrate 100 at room temperature (eg, about 25 ° C.) by the adhesive parts 400. The process of fixing the semiconductor chip 200 on the substrate 100 by heat treatment (eg, heat treatment at about 220 ° C.) may be omitted, thereby reducing the time required for mounting the semiconductor chip 200. Accordingly, the total turn around time (TAT) required for manufacturing the semiconductor package 1 can be reduced. The total processing time means the time required for processing after the wafer is loaded. The semiconductor chip 200 is fixed by the adhesive parts 400 and may be disposed to have a predetermined distance d from the package substrate 100.

Referring to FIG. 6, the semiconductor chip 200 may be coupled to the package substrate 100 through the bump 250. By reflowing the bump 250 of the semiconductor chip 200, the bump 250 may be bonded to the inner pad 120 of the package substrate 100. The reflow may proceed by applying temperature and / or pressure to melt a portion of the bump 250. For example, when the bump 250 is reflowed at a temperature higher than the melting point of the bump 250 (eg, 250 ° C. or more), the solder ball may change into a liquid phase. As the bumps 250 are melted, the bumps 250 may be bonded to the inner pads 120 of the package substrate 100.

Some of the adhesive parts 400 may be removed in the reflow process. The remaining adhesive part 450 may be formed from the adhesive parts 400 remaining without being removed. For example, the first residual adhesive part 451 may be formed to have a particle shape. As another example, the second to fourth remaining adhesive parts 452, 453, and 454 may be formed to contact the upper surface 200a of the package substrate 100 and / or the lower surface 200b of the semiconductor chip 200. The remaining adhesive part 450 may be formed to have a height equal to or lower than a distance d between the package substrate 100 and the semiconductor chip 200.

Referring to FIG. 7, an underfilling layer 300 may be formed between the package substrate 100 and the semiconductor chip 200. The underfill film 300 may be formed by filling a polymer (eg, an epoxy molding compound (EMC)) between the package substrate 100 and the semiconductor chip 200. The underfill film 300 may be formed to include the remaining adhesive part 450 therein. The carrier 500 may relieve physical stress applied to the package substrate 100 at the wafer level in the process of forming the underfill film 300. A molding film 350 may be selectively formed to surround the package substrate 100 and / or the semiconductor chip 200.

Referring back to FIG. 1, the package substrate 100 may be separated from the carrier 500. When the package substrate 100 is not loaded on the carrier 500, the separation process may also be omitted. The carrier pad 510 may easily separate the package substrate 100 from the carrier 500. The semiconductor package 1 of the present invention can be completed by Example 1 of the method for manufacturing a semiconductor package.

<Application example>

8 is a diagram illustrating an example of a package module including a semiconductor package according to an embodiment of the present invention. 9 is a block diagram illustrating an example of an electronic device including a semiconductor package according to an embodiment of the present disclosure. 10 is a block diagram illustrating an example of a memory system including a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 8, the package module 1200 may be provided in the form of a semiconductor integrated circuit chip 1220 and a quad flat package (QFP) packaged semiconductor integrated circuit chip 1230. The semiconductor devices 1220 and 1230 may include a semiconductor package 1 according to embodiments of the present invention. The package module 1200 may be connected to an external electronic device through an external connection terminal 1240 provided at one side of the substrate 1210.

9, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a storage device 1330. The controller 1310, the input / output device 1320, and the storage device 1330 may be coupled through a bus 1350. [ The bus 1350 may be a path through which data flows. For example, the controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing the same functions. The controller 1310 and the memory device 1330 may include a semiconductor package 1 according to embodiments of the present invention. The input / output device 1320 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 1330 is a device for storing data. The storage device 1330 may store data and / or instructions that may be executed by the controller 1310. The storage device 1330 may include a volatile storage element and / or a non-volatile storage element. Alternatively, the storage device 1330 may be formed of a flash memory. For example, a flash memory to which the technique of the present invention is applied can be mounted on an information processing system such as a mobile device or a desktop computer. Such a flash memory may consist of a semiconductor disk device (SSD). In this case, the electronic system 1300 can stably store a large amount of data in the flash memory system. The electronic system 1300 may further include an interface 1340 for transferring data to or receiving data from the communication network. The interface 1340 may be in wired or wireless form. For example, the interface 1340 may include an antenna or a wired or wireless transceiver. Although not shown in the drawings, the electronic system 1300 may further include an application chipset, a camera image processor (CIS), and an input / output device. Self-evident to one.

The electronic system 1300 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card A digital music system, and an information transmission / reception system. When the electronic system 1300 is a device capable of performing wireless communication, the electronic system 1300 may be used in a communication interface protocol such as a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, or CDMA2000. Can be used.

Referring to FIG. 10, the memory card 1400 may include a nonvolatile memory device 1420 and a memory controller 1420. The nonvolatile memory device 1420 and the memory controller 1420 may store data or read stored data. The nonvolatile memory device 1420 may include a semiconductor package 1 according to embodiments of the present invention. The memory controller 1420 may control the flash memory device 1420 to read stored data or store data in response to a read / write request from a host.

Claims (9)

A package substrate;
A semiconductor chip mounted on the package substrate;
A bump interposed between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate;
An underfill film filled between the package substrate and the semiconductor chip; And
And a residual adhesive portion provided in the underfill film.
The method according to claim 1,
The remaining adhesive portion is a semiconductor package having a particle shape.
The method according to claim 1,
The remaining adhesive portion is a semiconductor package having a height equal to or less than the distance between the substrate and the semiconductor chip.
The method according to claim 1,
The semiconductor chip is spaced apart from the package substrate at regular intervals.
Providing a substrate;
Forming adhesive parts spaced apart from each other on the substrate;
Fixing a semiconductor chip including a bump to the substrate by the adhesive portions and placing the semiconductor chip on the substrate;
Reflowing the bump to electrically connect the semiconductor chip with the substrate; And
A method of manufacturing a semiconductor package comprising filling the substrate and the semiconductor chip to form an underfill film.
6. The method of claim 5,
And removing a portion of the adhesive parts by the reflow to form a residual adhesive part.
6. The method of claim 5,
Forming the bonds is:
Applying an adhesive solution to the printing roll surface to form adhesive dots; And
And transferring the adhesive dot on the surface of the printing roll onto the package substrate.
6. The method of claim 5,
Forming the adhesive portions includes applying an adhesive to have a pattern on the substrate by a dispenser.
6. The method of claim 5,
Providing the substrate further comprises loading the substrate onto a carrier,
And separating the substrate from the carrier after forming the underfill film.

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