KR20140030903A - Printed circuit board, pcb for semiconductor chip package, semiconductor chip pakage and method for manufacturing semiconductor chip pakage using pcb there of - Google Patents

Abstract

The present invention relates to a printed circuit board for a semiconductor chip package, a semiconductor package using the same, and a manufacturing method of the semiconductor chip package, wherein the printed circuit board includes a through hole formed through the whole printed circuit board in a thickness direction in order to prevent the printed circuit board from being bent during thermal processing.

Description

Printed circuit board for semiconductor chip package and semiconductor package using same and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board for a semiconductor chip package, a semiconductor package using the same, and a manufacturing method thereof, and more particularly, A printed circuit board for a semiconductor chip package, a semiconductor package using the substrate, and a semiconductor package method.

BACKGROUND ART [0002] Semiconductor packages widely used in high-performance electronic devices have undergone various developments in order to make them smaller in size, multifunctional in performance, and increased in internal capacity. In order to reduce the size, a printed circuit board is mainly used instead of a conventional lead frame.

Generally, a printed circuit board is a component in which wiring is integrated so that various devices such as a semiconductor chip can be mounted or an electrical connection between the devices can be made.

FIG. 1 is a top view of a conventional printed circuit board, and FIG. 2 is a sectional view taken along line A-A 'of FIG.

The printed circuit board 10 shown in FIGS. 1 and 2 includes an insulating layer 10C, at least one via hole 12 penetrating the insulating layer 10C, a circuit pattern (not shown) formed on the upper and lower surfaces of the insulating layer 10C, And at least one conductive pad 11A and 11B for electrically connecting the circuit patterns 10A and 10B and the via hole 12 to each other.

3A and 3B are sectional views of a general semiconductor chip.

3A and 3B, the semiconductor chip 20 includes a semiconductor die 21, at least one bump pad 22 formed on the semiconductor die 21, and at least one solder bump 22 connected to the bump pad 22, (23).

In recent years, the printed circuit board used in the electronic package has become thinner as the product becomes more lightweight. In order to realize various functions in a thin structure, a high integration is required to increase the number of cells per unit area in order to increase the capacity of the semiconductor device. A packaging technique in which a plurality of chips 20 are stacked to increase capacity is becoming common.

FIG. 4 is a flowchart of a conventional method for manufacturing a semiconductor package, and FIGS. 5A to 5C are sectional views sequentially showing the result of the process according to FIG.

4 and 5A to 5C, a printed circuit board 10 to be mounted with the semiconductor chip 20 is prepared (S11), and the semiconductor chip 20 is mounted on the upper surface of the printed circuit board 10 (S13, Fig. 5B), and then the solder ball 13 is attached (S14, Fig. 5C).

However, since the flip chip bonding method using the solder bumps 23 instead of the wires as the connection terminals for connecting the printed circuit board, which is a basic frame, to the semiconductor chip is most effective for high-speed, high-performance and high- In recent years, the application range has been gradually increasing.

The printed circuit board has a very weak characteristic in the case where various environmental changes such as ambient temperature, humidity, and the like change, thereby causing a sudden deformation. In particular, warpage occurs due to a difference in thermal expansion coefficient between a semiconductor chip, a resin adhesive, and a printed circuit board during a manufacturing process, thereby causing a problem such as a vacuum error or a feeding error in the package assembly process do.

At this time, if the deforming force of the printed circuit board spreads widely around the solder bumps 23 to reach the solder bumps 23 of the semiconductor chip 20, the solder bumps 23 are electrically connected to the bump pads 22 on the semiconductor chip 20, The solder bumps 23 are broken by the impact due to the attachment points of the solder bumps 23 being attached to each other between the connection pads 11A on the substrate 10 or by any external force during curing of the melted solder bumps 23 Which causes fine cracks on a certain surface.

The solder bump 23 serves as a joint member between the semiconductor chip and the circuit block and greatly affects the overall function of the semiconductor package. Therefore, if the solder bump 23 is damaged by the above-described process, The semiconductor package 20 can not achieve a smooth conduction relationship with the printed circuit board 10, and thus the semiconductor package can not smoothly perform its role.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide a semiconductor chip package which effectively reduces PCB warpage of a printed circuit board against heat during a reflow process during a semiconductor package process. And a semiconductor package and a packaging method using the printed circuit board.

A printed circuit board for a semiconductor chip package according to the present invention includes an insulating layer having circuit patterns formed on upper and lower surfaces thereof and via holes for electrically connecting the circuit patterns on upper and lower surfaces thereof, A printed circuit board on which a chip is mounted, the printed circuit board including a through hole formed in a thickness direction to penetrate the entire printed circuit board in order to prevent warpage of the printed circuit board in a thermal process. to provide.

And the through holes in the printed circuit board are regularly arranged in a portion where the via holes and the circuit patterns are not formed in the respective units of the printed circuit board.

And the through hole is filled with an encapsulant for sealing the semiconductor chip in the printed circuit board.

A semiconductor package according to the present invention includes: an insulating layer on which a via hole is formed; a circuit pattern formed on upper and lower surfaces of the insulating layer and electrically connected through the via hole; And a second connection pad formed on a lower surface of the insulating layer and extending outwardly from the semiconductor chip. A semiconductor chip including a solder bump attached to the first connection pad; a semiconductor die having a bump pad to which the solder bump is attached and a semiconductor die to which the bump pad is attached; A solder ball connected to the second connection pad; And at least one through hole filled with the sealing material is formed on the printed circuit board, the semiconductor chip and the sealing material being coated on the entire upper surface of the printed circuit board. Package.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, comprising the steps of: processing at least one through hole in a printed circuit board including an insulating layer on which circuit patterns are formed on upper and lower sides and via holes for electrically connecting the circuit patterns on upper and lower sides, ; Mounting a semiconductor chip on one surface of the printed circuit board; Attaching a film to the other surface of the printed circuit board opposite to the one surface; Molding the semiconductor chip and the printed circuit board into an encapsulation material, the encapsulation material filling the through-hole; Removing the film attached to the other surface; And attaching a solder ball to the second connection pad on the other side of the semiconductor chip package.

The present invention can reduce the warpage of the printed circuit board against heat during the reflow process by processing the through holes in the substrate when the printed circuit board is manufactured.

In addition, it is possible to reduce the occurrence of stress on the joint surface between the semiconductor chip and the printed circuit board due to the difference in the coefficient of thermal expansion (CTE) between the semiconductor chip and the printed circuit board, (Bump crack) and open (open) can be reduced.

In addition, since voids that can occur in a molding process can be removed through a through hole, void defects may be generated in the encapsulating material filling the space between the printed circuit board and the semiconductor chip. .

Further, in the step of molding the semiconductor package into the encapsulation material, the encapsulation material may be impregnated and filled in the whole of the through hole, so that the printed circuit board can be firmly fixed in the transverse direction.

1 is a top view of a conventional printed circuit board,
FIG. 2 is a cross-sectional view taken along line AA 'of FIG. 1,
3A and 3B are cross-sectional views of a general semiconductor chip and a general stacked semiconductor chip,
4 is a flowchart of a semiconductor package method using a general printed circuit board for a semiconductor package,
5A to 5C are cross-sectional views illustrating a semiconductor package process using a general printed circuit board according to FIG. 4,
6 is a top view of a printed circuit board according to an embodiment of the present invention,
7 is a sectional view taken along line BB 'of FIG. 6,
8 is a flowchart of a semiconductor package method using a printed circuit board for a semiconductor package according to an embodiment of the present invention,
9A to 9E are cross-sectional views illustrating a semiconductor package process according to an embodiment of the present invention with reference to FIG.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, the constituent elements are shown enlarged for the sake of convenience of explanation, and the proportions of the constituent elements may be exaggerated or reduced.

It is to be understood that when an element is described as being on or in contact with another element, it may be directly in contact with or coupled to another element, but there may be another element in between.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. And the like are used to designate a feature, a number, a step, an operation, an element, a part, or a combination thereof, which is described in the specification, means that one or more other features, It is to be understood that the components, parts or combinations thereof may be added.

The terms used in the embodiments of the present invention may be construed as commonly known to those skilled in the art unless otherwise defined.

Hereinafter, a printed circuit board for a semiconductor chip package of the present invention will be described in detail with reference to the drawings.

FIG. 6 is a top view of a printed circuit board according to an embodiment of the present invention, and FIG. 7 is a B-B 'sectional view of FIG.

6 and 7, a printed circuit board 100 for a semiconductor chip package according to an embodiment of the present invention includes an insulating layer 100C having a via hole 112 formed therein; Circuit patterns (100A, 100B) formed on the upper and lower surfaces of the insulating layer (100C) and electrically connected through the via holes (112); A first connection pad 111A formed on the upper surface of the insulating layer 100C and connected to the semiconductor chip; A second connection pad 111B formed on the lower surface of the insulating layer 100C and extending the function of the semiconductor chip to the outside; And at least one through hole (110) passing through the entire printed circuit board (100).

The via hole 112 may be electrically connected to each other by a via contact connecting the first connection pad 111A and the second connection pad 111B and may include at least one internal wiring layer Not shown) may be further formed. The first and second connection pads 111A and 111B formed on the upper surface and the lower surface of the via hole 112 of the printed circuit board 100 and the printed circuit board 100 are made of aluminum or copper foil And in some embodiments the surface of the metal wiring may be plated with tin (Sb), gold (Au), nickel (Ni), lead (Pb), or an alloy of these metals.

Referring to FIG. 6, in the present embodiment, the through hole 110 is shown as a circular shape, but is merely an example of a shape of a through hole, and may be modified into various shapes such as a rhombus, a rectangle, and the like. Also, the first connection pads 111A formed on the upper surface of the printed circuit board 100, for example, the bump pads, may be modified into various arrangements at appropriate positions according to the needs of the designer.

FIG. 8 is a flowchart of a semiconductor package process using a printed circuit board for a semiconductor package according to an embodiment of the present invention, and FIGS. 9A to 9E are sectional views sequentially illustrating a semiconductor package process according to FIG.

FIG. 9A is a cross-sectional view of a printed circuit board and a semiconductor chip according to an embodiment of the present invention, FIG. 9B is a cross-sectional view of the film of FIG. 9A, FIG. 9C is a cross- 9D is a cross-sectional view in which the film is removed in FIG. 9C, and FIG. 9E is a cross-sectional view of the solder ball in FIG. 9D, which is a semiconductor package using a printed circuit board for semiconductor chip package for reducing PCB warpage including through holes.

8A and 9A to 9E, a semiconductor package and a method of manufacturing the same according to the present invention will be described in detail. In the semiconductor package manufacturing method and the semiconductor package according to the present invention, An insulating layer (100C) including an upper surface and a lower surface opposite to the upper surface; A first connection pad 111A formed on the upper surface and connected to the semiconductor chip; A second connection pad 111B formed on the lower surface and extending the function of the semiconductor chip 120 to the outside; And a printed circuit board 100 for a package of a semiconductor chip 120 for reducing the warp of the PCB by machining the through hole 110 passing through from the upper surface to the lower surface of the printed circuit board 100 A method of manufacturing a semiconductor device, comprising the steps of: machining two or more through holes (110) in each unit of the printed circuit board (S12); Mounting a semiconductor chip on the upper surface (S13); Attaching the film 130 to the lower surface (S14); (S15) molding the semiconductor chip 120 and the printed circuit board 100 into the encapsulant 140 such that the encapsulant 140 penetrates the entirety of the through hole 110 through the upper surface; Removing the film 130 attached to the lower surface (S16); And attaching a solder ball 113 to the second connection pad 111B on the bottom surface (S17).

In addition, the semiconductor package according to an embodiment of the present invention may further include a solder ball 113, which is a conductive layer attached to the second connection pad 111B on the lower surface of the printed circuit board 100. If the semiconductor package is a pin grid array type, the conductor attached to the second connection pad 111B may be a pin instead of the solder ball.

In the present embodiment, the through hole 110 is formed into a circular shape in the process of forming the through hole 110 extending from the upper surface to the lower surface of the printed circuit board 100. However, And may be modified into various shapes such as a diamond shape, a rectangle, and the like. The through hole 110 may be formed by, for example, drilling or the like, or by forming a mask pattern by a lithography process and etching the insulator material constituting the printed circuit board by an etching process, , And the through hole 110 can be formed by various other methods.

Also, the arrangement of the connection pads 111A, 111B, e.g., bump pads or solder pads, may also be modified into various arrangements depending on the needs of the designer.

And a semiconductor chip 120 connected to the solder bumps 123 through a reflow process on a first connection pad 111A provided on an upper surface of the printed circuit board 100, The semiconductor chip 120 may be a semiconductor chip 120 that performs various functions such as a memory, a logic, a microprocessor, an analog device, a digital signal processor, and a system-on-chip.

The semiconductor chip 120 may be a stacked semiconductor chip 120 having a structure in which at least two semiconductor chips 120 are stacked and may be a pin grid array or a ball grid array. Type semiconductor chip 120. The semiconductor chip 120 may be a semiconductor chip.

The semiconductor chip 120 is mounted on the upper surface of the printed circuit board 100 for the semiconductor chip 120 package according to the present invention through the solder bumps 123. The solder bump 123 may be formed on the UBM layer after first forming an under bump metallurgy (UBM) layer (not shown) on the bump pad 122 of the semiconductor chip 120. The solder bumps 123 may be connected 1: 1 to the first connection pads 111A on the printed circuit board 100. [ The mounting of the semiconductor chip 120 on the printed circuit board 100 can be accomplished through a high temperature heat treatment such as wave soldering or reflow soldering.

The reflow soldering process refers to a process of soldering by melting a pre-formed solder paste or a solder cream. More specifically, the reflow soldering process includes a step of melting solder (Sn / Pb, Sn / Pb / Au, etc.) is melted and the liquid in contact with the surface flows and spreads. At the same time, the metal elements constituting the solder are diffused between the base metal elements to form an alloy layer, .

For example, the reflow soldering process may include a heat-up period from a room temperature of about 25 ° C to about 100 ° C, a soaking period from about 100 ° C to about 200 ° C, A reflow soldering section from a temperature of about 200 ° C to a peak value (about 245 ° C), and a cooling section from about 200 ° C to a room temperature. Here, the reflow soldering section is a temperature section near the melting point of the solder. For example, the melting point of a solder containing 96.5% of tin (Sn) and 3.5% of silver (Ag) is about 221 ° C and 99.3% of tin (Sn) A solder containing 0.7% of copper (Cu) has a melting point of about 227 ° C. Therefore, depending on the configuration of the solder, the reflow soldering period may be set differently. The temperature range described to describe the reflow soldering process is merely an example, and the present invention is not limited to this temperature range.

9C, the step of attaching the film 130 to the lower surface of the printed circuit board 100 (S14) is added before the molding of the encapsulant 140 (S15) The sealing material 140 filling the upper surface of the printed circuit board 100 penetrates the through hole 110 to fill the entire inside of the through hole 110 and prevents the printed circuit board 100 from flowing out of the printed circuit board 100, .

At this time, a lamination tape may be used as the film 130, or a film 130 having a superior compression performance may be used.

9C, a molding process (S15) is performed on the printed circuit board 100 on which the semiconductor chip 120 is mounted with the encapsulant 140 with the film 130 attached to the lower surface of the printed circuit board 100. Then, ). The encapsulant 140 for the semiconductor package used in the molding process S15 may cause a void defect in the bonding surface between the semiconductor chip 120 and the printed circuit board 100 by the encapsulant 140 for MUF It is suitable that the material does not. The MUF encapsulant 140 has a low content of ions and a low hygroscopic property and is excellent in adhesion between the semiconductor chip 120 and the printed circuit board 100, Flowability is preferable.

 The sealing material 140 first fills a space between the semiconductor chip 120 on the upper surface of the printed circuit board 100 and the printed circuit board 100 and flows to the lower surface of the printed circuit board through the through hole 110 . Therefore, there is an advantage that an underfill process for filling a space between the semiconductor chip 120 and the printed circuit board 100 by using a separate underfill resin is not performed. In addition, since the flow of the sealing material 140 is controlled through the through hole 110, the problem of void defects between the semiconductor chip 120 and the printed circuit board 100 can be solved.

The encapsulant 140 may be a MUF (Molded Under Fill) encapsulant 140 that functions not only to fill a space between the semiconductor chip 120 and the printed circuit board 100 but also to seal the semiconductor package. Do. Since the MUF-type encapsulant 140 uses an epoxy mold compound (EMC) that has undergone reliability verification, the underfill process can be performed without separately performing the underfill process. Therefore, the underfill process can be simplified and the process can be simplified have.

The sealing member 140 is filled in the through hole 110 passing through the inside of the printed circuit board 100 so that thermal stress is generated in the printed circuit board 100 and the semiconductor chip 120 to repeatedly shrink and expand , The printed circuit board 100 is fixed in the lateral direction and locked. Therefore, the thermal stress generated in the semiconductor package can be absorbed into the encapsulant 140 filled in the upper encapsulant 140 and the through-hole 110.

After the step S15 of molding the encapsulant 140 is completed, the film 130 attached to the lower surface of the printed circuit board 100 is removed (S16).

At this time, the method of removing the film 130 may be various methods depending on the material of the film 130. For example, only the film 130 may be melted using a medicine, or heat may be applied to the film 130 due to a difference in thermal expansion coefficient It may be removed by being separated naturally from the circuit board 100. In this case, a cleaning step may be added for finishing cleanly so that no residue is left.

9E, a solder ball 113 is attached to a second connection pad of the printed circuit board 100 (S17). By this method, a semiconductor package having a through hole 110 is formed by the method of manufacturing a semiconductor package according to an embodiment of the present invention. A semiconductor package using the printed circuit board 100 for a chip package is completed.

4, the through hole 110 is formed in the printed circuit board 100, and the semiconductor chip 120 is mounted on the printed circuit board. In this case, The thermal expansion coefficient CTE of the semiconductor chip 120 and the printed circuit board 100 are different from each other in the semiconductor package so that the printed circuit board 100 and the semiconductor When the stress is concentrated on the bonding surface of the chip 120, the through hole 110 serves to reduce the influence of the thermal expansion coefficient (CTE) difference, so that the warpage of the printed circuit board 100 ).

In some modified embodiments, as is well known in the art, semiconductor chips on the top and bottom surfaces of a printed circuit board are stacked vertically with respect to a printed circuit board, or another substrate is stacked with a semiconductor chip to form a multi-stack package structure A semiconductor chip package may be formed.

100: printed circuit board 110: through hole
120: semiconductor chip 123: solder bump
130: Film 140: Encapsulant

Claims (8)

A printed circuit board having a circuit pattern formed on upper and lower surfaces, an insulating layer having via holes for electrically connecting the circuit patterns on upper and lower surfaces, and on which semiconductor chips are mounted so as to be electrically connected to the circuit patterns.
The printed circuit board for semiconductor chip package, characterized in that it comprises a through hole formed in the thickness direction to penetrate the entire printed circuit board in order to prevent the bending of the printed circuit board during the thermal process.
The method of claim 1,
The through hole is a printed circuit board for the semiconductor chip package, characterized in that arranged regularly in the via hole and the circuit pattern is not formed in each unit of the printed circuit board.
3. The method according to claim 1 or 2,
The through hole is a printed circuit board for a semiconductor chip package, characterized in that the sealing material for sealing the semiconductor chip is filled.
An insulating layer having a via hole, a circuit pattern formed on upper and lower surfaces of the insulating layer and electrically connected through the via hole, a first connection pad formed on an upper surface of the insulating layer and connected to a semiconductor chip, and the insulating layer A printed circuit board formed on a lower surface of the substrate, the printed circuit board including a second connection pad to extend a function of the semiconductor chip to the outside;
A semiconductor chip including a solder bump attached to the first connection pad, a bump pad to which the solder bump is attached, and a semiconductor die to which the bump pad is attached;
A solder ball connected to the second connection pad; And
It includes an encapsulant coating the entire upper portion of the semiconductor chip and the printed circuit board,
The printed circuit board is a semiconductor package, characterized in that at least one through-hole penetrating the printed circuit board, the sealing material is filled.
Processing at least one through hole in a printed circuit board having a circuit pattern formed on upper and lower surfaces, and an insulating layer having a via hole for electrically connecting the circuit patterns on upper and lower surfaces;
Mounting a semiconductor chip on one surface of the printed circuit board;
Attaching a film to the other surface of the printed circuit board opposite to the one surface;
Molding the semiconductor chip and the printed circuit board into an encapsulation material, the encapsulation material filling the through-hole;
Removing the film attached to the other surface; And
And attaching solder balls to the second connection pads of the other surface.
The method of claim 5, wherein
The semiconductor chip packaging method using a semiconductor chip package printed circuit board, characterized in that the semiconductor chip is a stacked semiconductor chip.
The method of claim 5, wherein
The semiconductor chip is a semiconductor package method using a printed circuit board for semiconductor chip package, characterized in that attached to the printed circuit board by a ball grid array.
The method of claim 5, wherein
The film is a semiconductor packaging method using a printed circuit board for a semiconductor chip package, characterized in that the lamination tape.

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