KR20140029976A - Circuit for trimming voltage - Google Patents

Circuit for trimming voltage Download PDF

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Publication number
KR20140029976A
KR20140029976A KR1020120096735A KR20120096735A KR20140029976A KR 20140029976 A KR20140029976 A KR 20140029976A KR 1020120096735 A KR1020120096735 A KR 1020120096735A KR 20120096735 A KR20120096735 A KR 20120096735A KR 20140029976 A KR20140029976 A KR 20140029976A
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KR
South Korea
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voltage
mode
flat
linear
signal
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KR1020120096735A
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Korean (ko)
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KR101965360B1 (en
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김철회
박재범
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에스케이하이닉스 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A voltage trimming circuit according to the present invention selectively performs a linear mode trimming operation and a flat mode trimming operation and includes: a common voltage distributing unit which distributes both end voltages of a resistor string in which a driving current flows, a comparing unit which compares a reference voltage with a feedback voltage outputted from the common voltage distributing unit in response to a flat mode enable signal which is activated, a flat mode driving unit which supplies the driving current to the common voltage distributing unit in response to the output signal of the comparing unit, and a linear mode driving unit which supplies the driving current to the common voltage distributing unit in response to a linear enable signal which is activated. [Reference numerals] (300) Mode signal generating unit; (410) Linear mode driving unit; (420) Comparing unit; (430) Flat mode driving unit; (450) Common voltage distributing unit

Description

Voltage trimming circuit {circuit for trimming voltage}

TECHNICAL FIELD This invention relates to the circuit of a semiconductor device. Specifically, It is related with the voltage trimming technique.

Since a semiconductor device including a memory is composed of many internal circuits, and the level of driving voltage required to drive each internal circuit may be different, in order to generate a driving voltage having a voltage level required by the internal circuit of the semiconductor device. Alternatively, in order to generate a driving voltage having a target voltage level independent of PVT (Process, Voltage, Temperature) fluctuations, voltage trimming to adjust the driving voltage by dividing the voltage level of the supply voltage is necessary.

The voltage trimming circuit is largely divided into a trimming circuit for performing a linear mode operation and a trimming circuit for a flat mode operation according to an operation method. The linear mode trimming circuit is simple in configuration and can output a target voltage whose voltage level is variable in response to a change in the supply voltage level. On the other hand, the flat mode trimming circuit has a complicated configuration, cannot change the target voltage level in response to the change in the supply voltage level, and can output a target voltage having a constant voltage level that is not affected by the change in the supply voltage. have.

1 is a linear mode trimming circuit diagram for use in a general semiconductor device.

Referring to FIG. 1, a linear mode trimming circuit of a general semiconductor device includes a current driver 10 and a voltage distribution selector 20.

The current driver 10 includes an inverter INV and a PMOS transistor P11. The linear enable LINEAR_EN input to the inverter INV is inverted and amplified and output to the gate of the PMOS transistor P11. A drain of the PMOS transistor P11 connected between the supply voltage terminal VDD and the voltage distribution selector 20 is connected to the voltage distribution selector 20.

In order to activate the trimming operation in the current driver 10, the linear enable LINEAR_EN input at the high level is inverted and amplified and input to the gate of the PMOS transistor P11 as a low level signal, and the PMOS transistor P11 is turned on. ON to supply current from the supply voltage terminal VDD to the voltage distribution selecting section 20. When the linear enable LINEAR_EN is at the low level, the PMOS transistor P11 is turned off to cut off the supply of current.

The voltage divider selector 20 selects one of a plurality of voltages and a voltage divider 21 for generating a plurality of voltages in response to the output current of the current driver 10, and selects a voltage for outputting a target voltage V_TRIM. And a portion 22.

The voltage divider 21 includes an ultrashort resistor RA, a resistance string R0 to R15, and a terminal resistor RB connected in series between the current driver 10 and the ground terminal VSS. The output current of the driving unit 10 is divided into voltages according to the ratios of the respective resistance sizes of the ultra short resistance RA, the resistance strings R0 to R15, and the terminal resistance RB to divide the voltages between the resistance strings R0 to R15 and the terminals. A plurality of voltages are generated at the nodes n0 to n15 of the resistor RB. Here, the ultrashort resistor RA and the terminal resistor RB serve to roughly set a range of the generated voltages, thereby enabling precise voltage trimming by the resistor strings R0 to R15.

The voltage selector 22 includes switches SW0 to SW15 having one end connected to each node n0 to n15 of the resistor strings R0 to R15 and the terminal resistor RB and the other end connected to each other. Operating one of the switches SW0 to SW15 connected from each of the nodes R0 to R15 between the strings R0 to R15 and the terminal resistor RB selects one of the divided voltages and outputs the target voltage V_TRIM. .

In this case, the target voltage V_TRIM is substantially a voltage selected from one of the voltage divided by the ultrashort resistor RA, the resistor strings R0 to R15, and the terminal resistor RB as the voltage level of the supply voltage terminal VDD. In response to the change in the voltage level of the supply voltage terminal VDD, the level of the target voltage V_TRIM also changes.

2 is a flat mode trimming circuit diagram for use in a general semiconductor device.

Referring to FIG. 2, a flat mode trimming circuit of a general semiconductor device includes a comparator 11, a driver 12, and a voltage distribution selector 20.

The comparator 11 is activated when the flat enable FLAT_EN has a high level, and receives a reference voltage V_REF and a feedback voltage V_FEED having a constant voltage level and outputs a differential voltage V_AO in response thereto. do.

The driver 12 includes a PMOS transistor P12 connected between the supply voltage terminal VDD and the voltage distribution selector 20. The differential voltage V_AO is connected to the gate of the PMOS0 transistor P12, and the source and drain are connected to each other. Both ends are connected to the supply voltage terminal VDD and the voltage distribution selector 20, respectively, to supply current to the voltage distribution selector 20 in response to the differential voltage V_AO.

The comparator 11 may be configured as a current mirror type. In detail, the first to fourth PMOS transistors P1, P2, P3, and P4 having a source commonly connected to the supply voltage terminal VDD, the first and second NMOS transistors N1 and N2 having a common source connected to each other, and the source having a ground terminal ( A fourth NMOS transistor N4 connected to the VSS, and a third NMOS transistor N3 connected to a source of the fourth NMOS transistor N4 are included.

Here, the first and second PMOS transistors P1 and P2 connect a common connected drain to the differential voltage V_AO of the comparator 11 and the drain of the first NMOS transistor N1, respectively, and the gate and the drain are connected to each other. The gate of the 3 PMOS transistor P3 is connected to the gate of the second PMOS transistor P2, and the third and fourth PMOS transistors P3 and P4 connect a common connected drain to the drain of the second NMOS transistor N2. The third NMOS transistor N3, which receives the bias signal VBIAS as a gate, connects the drain to a common connected source of the first and second NMOS transistors N1 and N2. Each gate of the first and fourth PMOS transistors P1 and P4 and the fourth NMOS transistor N4 is connected to the flat enable FLAT_EN, and the gate of the first NMOS transistor N1 is connected to the reference voltage V_REF. The gate of the second NMOS transistor N2 is connected to the feedback voltage V_FEED.

The voltage divider selector 20 includes a voltage divider 21 and a voltage selector 22.

The voltage divider 21 generates a plurality of voltages in response to the output current of the driver 12 and outputs a specific feedback voltage V_FEED of one of the plurality of voltages, and the voltage selector 22 generates a plurality of voltages. Select one and output the target voltage V_TRIM.

The voltage divider 21 may be composed of resistance strings R0 to R15 and terminal resistors RB connected between the driver 12 and the ground terminal VSS, and the output current of the driver 12 is a resistance string ( R0 to R15 and the terminal resistor (RB) are input to divide the voltage according to the ratio of the resistor size to the plurality of voltages between the nodes (n0 ~ n15) between the resistance string (R0 ~ R15) and the terminal resistor (RB) It generates and outputs the voltage of the specified node n12 as the feedback voltage (V_FEED). Here, the resistor RB serves to roughly set a range of the generated voltages, thereby enabling precise voltage trimming by the resistors R0 to R15 of the resistance string.

The voltage selector 22 includes switches SW0 to SW15 having one end connected to each node n0 to n15 of the resistance strings R0 to R15 and the terminal resistor RB, and the other end connected to each other. One of the plurality of voltages generated by the distribution unit 21 is selected as an operation of the switches SW0 to SW15 to output the target voltage V_TRIM.

Referring to the operation characteristics of the flat mode trimming circuit as described above, when the bias signal VBIAS having a constant voltage level that determines the bias current of the flat enable FLAT_EN having a high level and the comparator 11 is inputted, the comparator 11, the bias current flows to be activated and compares the voltage level between the reference voltage V_REF and the feedback voltage V_FEED having a constant voltage level, and when the feedback voltage V_FEED is greater than the reference voltage V_REF, the differential voltage ( When the voltage level of V_AO increases and is smaller than the reference voltage V_REF, the voltage level of the differential voltage V_AO decreases. Accordingly, the PMOS transistor P12 receiving the differential voltage V_AO of the comparator 11 as a gate decreases the current when the voltage level of the differential voltage V_AO increases, and conversely, the voltage level of the differential voltage V_AO. This decrease increases the current. In response to the current supplied by the PMOS transistor P12, a plurality of voltages are generated at each node n0 to n15 of the resistance strings R0 to R15 and the terminal resistor RB, and the specified node n12 voltage is generated. It outputs by the feedback voltage V_FEED of the comparator 11. Here, a negative feedback operation in which the feedback voltage V_FEED generated in response to the differential voltage V_AO of the comparator 11 is used as the input of the comparator 11 is performed.

By such a negative feedback operation, the driver (eg, in response to the differential voltage V_AO comparing the magnitude of the voltage level between the reference voltage V_REF having a constant voltage level and the feedback voltage V_FEED of the specified node n12) 12 adjusts the current to the voltage divider 21, so that the voltage divider 21 can generate a plurality of voltages without affecting the voltage level variation of the supply voltage terminal VDD, resulting in a plurality of voltages. The target voltage V_TRIM level at which one is selected is also not affected by the voltage level variation of the supply voltage terminal VDD.

Comparing the different characteristics of the linear mode trimming circuit and the flat mode trimming circuit, the linear mode trimming circuit is configured to adjust the voltage level at which the target voltage V_TRIM is divided according to the variation of the voltage level of the supply voltage terminal VDD. The flat mode trimming circuit outputs a constant target voltage V_TRIM regardless of the variation of the supply voltage terminal VDD.

In a general semiconductor device, only a voltage trimming circuit operating in one trimming mode most suitable for the device is used as needed. Therefore, since the semiconductor device operates in only one of the trimming modes, the trimming characteristics also have only one operation characteristic in accordance with the linear mode or the flat mode operation. Whether the most suitable trimming circuit for a semiconductor device is a linear mode trimming circuit or a flat mode trimming circuit is difficult to know until the actual semiconductor device is manufactured and tested, and it is difficult to determine the trimming circuit in the most suitable mode according to various uses of the semiconductor device. There is a difficult problem.

The present invention has been devised to solve the above problems, and provides a voltage trimming circuit capable of appropriately selecting one of the trimming modes of the linear mode and the flat mode, and operating in accordance with the selected trimming mode.

The voltage trimming circuit according to an embodiment of the present invention includes a common voltage divider for dividing a voltage across a resistance string through which a driving current flows, a reference voltage and a feedback voltage output from the common voltage divider in response to an activated flat mode enable. A comparator for comparing a signal, a flat mode driver for supplying the driving current to the common voltage divider in response to an output signal of the comparator, and the drive to the common voltage divider in response to an activated linear mode enable. And a linear mode driver for supplying current.

According to another embodiment of the present invention, a voltage trimming circuit includes a common voltage divider including a resistance string connected in series between a pull-up node and a ground voltage terminal, and is output from a reference voltage and the common voltage divider in response to a flat mode enable. A comparator for comparing a feedback voltage, a flat mode driver for driving the pull-up node to a power supply voltage in response to an output signal of the comparator, and a linear for driving the pull-up node to the power supply voltage in response to a linear mode enable. And a mode driver.

The voltage trimming circuit according to the present invention selects one of the linear mode trimming operation and the flat mode trimming operation as needed to perform the trimming operation, thereby providing the most suitable trimming mode according to the operation characteristics of each trimming mode. .

1 is a linear mode trimming circuit diagram for use in a general semiconductor device.
2 is a flat mode trimming circuit diagram for use in a general semiconductor device.
3 is a block diagram illustrating a voltage trimming circuit according to the present invention.
4A is a circuit diagram illustrating in detail a mode signal generation unit of a voltage trimming circuit according to an exemplary embodiment of the present invention.
4B is a graph illustrating a power-up signal output while power is supplied to a general semiconductor device.
5 is a circuit diagram illustrating in detail a trimming processing unit of a voltage trimming circuit according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

For reference, the terms, symbols, and symbols used in referring to elements, blocks, and the like in the drawings and the detailed description can be expressed in detail unit by necessity, so that the same terms, symbols, May not be referred to. In general, logic signals and binary data values of a circuit are classified into high level or low level in response to voltage level, and may be expressed as '1' and '0', respectively. Additionally, it is defined and described that it may have a high impedance state. Further, the high-level configuration for indicating the activation state of the signal and the circuit can be configured as a low level according to the embodiment.

3 is a block diagram illustrating a voltage trimming circuit according to the present invention.

Referring to FIG. 3, the voltage trimming circuit according to the present invention includes a mode signal generator 300 and a trimming processor 400.

The mode signal generation unit 300 selects one mode signal most suitable from the linear enable line LINE_EN and the flat enable FLAT_EN in the semiconductor device including the voltage trimming circuit according to the present invention, and selects the selected mode. Activate and output the signal.

The trimming processing unit 400 trims according to the operation mode in response to one of the linear enable signal LINEAR_EN and the flat enable FLAT_EN input from the mode signal generator 300, and trims according to the operation mode to generate the target voltage V_TRIM. Outputs

The trimming processor 400 includes a linear mode driver 410, a comparator 420, a flat mode driver 430, and a common voltage divider 450.

The linear mode driver 410 is activated and operates when the activated linear enable LINEAR_EN is input. The linear mode driver 410 receives the linear driving current C1 from the supply voltage in response to the linear enable LINEAR_EN to the common voltage divider 450. Will output

The comparator 420 is activated when the activated flat enable FLAT_EN is input. The comparator 420 compares the reference voltage V_REF having a constant voltage with the feedback voltage V_FEED from the common voltage divider 450. In response to the difference, a differential voltage V_AO is generated and output.

The flat mode driver 430 outputs the flat driving current C2 to the common voltage divider 450 from the supply voltage in response to the differential voltage V_AO.

The common voltage divider 450 includes a resistance string, and flows the input flat driving current C2 or linear driving current C1 into the resistance string to generate a plurality of voltages through each node of the resistance string, The target voltage V_TRIM is output among the voltages. Here, when a plurality of voltages generated by the flat driving current C2 are generated at each node of the resistance string, the feedback voltage V_FEED generated at one specific node is supplied to the comparator 420 to provide negative feedback ( negative feedback) operation.

For reference, the common voltage divider 450 may further include a voltage selector including a plurality of switches for selecting and outputting a target voltage V_TRIM among a plurality of generated voltages. The voltage selector includes a plurality of switches, one end of which is connected to each node of the resistance string and the other end of which is commonly connected.

4A is a circuit diagram illustrating in detail the mode signal generators (FIGS. 3 and 300) of the voltage trimming circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, the mode signal generators 3 and 300 are initialized by the power up bar signal PWRUPB, and in response to cutting of the test mode signal TM and the fuse cell FC, One of the linear enable (LINEAR_EN) and the flat enable (FLAT_EN) is enabled by the high level output, and the other is disabled by the low level.

The mode signal generation unit (FIGS. 3 and 300) includes a fuse unit unit 11 and a signal output unit 12.

The mode signal generation unit (FIGS. 3 and 300) is activated and operated when the voltage level of the supply voltage terminal VDD is stabilized to a constant voltage level, and is linearly enabled in response to the output of the fuse unit unit 11 (LINEAR_EN). ) And flat enable (FLAT_EN).

Herein, the power up bar signal PWRUPB is a signal generated during the initial power supply of a general semiconductor device. As shown in FIG. 4B, the power up bar signal PWRUPB is connected to a supply voltage terminal VDD for supplying power to the semiconductor device. As a result, the voltage level of the ground terminal VSS is lowered at the time point T0 when the supply voltage terminal VDD is stabilized through the period in which the voltage level rises. Here, the mode signal generation unit (FIGS. 3 and 300) is activated in accordance with the falling time point T0 of the power up bar signal PWRUPB, which is the time point T0 at which the supply voltage terminal VDD is stabilized. For reference, the power up bar signal PWRUPB may be omitted according to another exemplary embodiment.

The fuse unit 11 includes a fuse cell FC connected at one end thereof to a supply voltage terminal VDD, first and second NMOS transistors N1 and N2 having a common drain connected thereto, and a fuse state signal FU_OUT. It includes a first inverter (INV1) connected to the output terminal. The first and second NMOS transistors N1 and N2 having a source connected to the ground terminal VSS respectively connect a common connected drain to the other end of the fuse cell FC and the input terminal of the first inverter INV1, and the first NMOS. The gate of the transistor N1 is connected to the power up bar signal PWRUPB, and the gate of the second NMOS transistor N2 is connected to the fuse state signal FU_OUT.

The fuse unit 11 is activated by the power up bar signal PWRUPB, and outputs a fuse state signal FU_OUT in response to cutting of the fuse cell FC. When the fuse cell FC is not cut, the signal having the high level voltage of the supply voltage terminal VDD is lowered after the voltage level of the power up bar signal PWRUPB falls after the rising period. The signal is input to the first inverter INV1 and outputs a low level signal as the fuse state signal FU_OUT. When the first fuse cell FC1 is cut, the signal having the low level voltage of the ground terminal VSS is applied to the first inverter INV1 while the voltage level of the power up bar signal PWRUPB passes the rising section. The high level signal is output as the fuse state signal FU_OUT, and the state is maintained by the turned-on second NMOS transistor N2 even after the voltage level of the power up bar signal PWRUPB decreases. In conclusion, the fuse unit 11 outputs the fuse state signal FU_OUT at a low level when the fuse cell FC is not cut, and the fuse state signal FU_OUT when the fuse cell FC is cut. Outputs to a high level.

The signal output unit 12 activates and outputs one of the linear enable line LINE_EN and the flat enable FLAT_EN to a high level in response to the test mode signal TM and the fuse state signal FU_OUT, and the other Deactivate the other to low level.

The signal output unit 12 includes a logic sum gate OR and a second inverter INV2. The NOR receives a fuse state signal FU_OUT and a test mode signal TM, which are outputs of the fuse unit unit 11, as inputs. The gate NOR outputs the output to the linear enable LINEAR_EN. The logic sum gate OR is again inverted via the second inverter INV2 and output to the flat enable FLAT_EN. For reference, if the time delay caused by the second inverter INV2 is ignored, the linear enable LINEAR_EN and the flat enable FLAT_EN are always inverted and cannot be activated at the same time.

Referring to the operation of the mode signal generation unit (FIGS. 3 and 300), when the fuse cell FC of the fuse unit unit 11 is not cut, the fuse state signal FU_OUT has a low level, and thus, the logic sum gate OR. Outputs a voltage level of the test mode signal TM so that one of the linear enable LINEAR_EN and the flat enable FLAT_EN is activated and outputted at a high level according to the test mode signal TM. When the fuse cell FC is cut, since the fuse state signal FU_OUT has a high level, the logic sum gate OR outputs a low level regardless of the test mode signal TM, thereby providing a linear enable line LINE_EN. ) Is output at low level and flat enable (FLAT_EN) is output at high level.

The mode signal generation unit (FIGS. 3 and 300) changes the test mode signal TM during the initial test mode operation of the semiconductor device using the voltage trimming circuit of the present invention, and verifies and selects the trimming mode most suitable for the semiconductor device. . During the initial test mode operation, the semiconductor device including the trimming circuit is verified by analyzing and evaluating the performance of each trimming mode through a conventional measuring method, thereby selecting a trimming operation mode most suitable for the semiconductor device.

In the case where the most appropriately selected trimming mode is the linear trimming mode, since the fuse cell FC is not cut after the test mode operation, the test mode signal TM after the test mode operation always maintains the low level. The signal generator 300 activates and outputs the linear enable LINEAR_EN to a high level, and outputs the flat enable FLAT_EN to a low level.

When the most appropriately selected trimming mode is the flat trimming mode, if the fuse cell FC is cut after the test mode operation is completed, the mode signal generation unit 300 is flat enabled regardless of the test mode signal TM. Enables (FLAT_EN) at high level and outputs, and outputs linear enable (LINEAR_EN) at low level.

5 is a circuit diagram illustrating in detail a trimming processing unit of a voltage trimming circuit according to an exemplary embodiment of the present invention.

3 and 400, the trimming processing unit (FIGS. 3 and 400) may include a linear mode driving unit 410, a comparator 420, a flat mode driving unit 430, a common voltage divider 450, and a voltage selecting unit 460. It includes.

The linear mode driver 410 includes an inverter INV and a first PMOS transistor P411. The linear enable line LINE_EN is inverted and amplified through the inverter INV and input to the gate of the first PMOS transistor P411. The source and the drain of the first PMOS transistor P411 are connected between the supply voltage terminal VDD and the common voltage divider 450, respectively.

When the linear mode driver 410 is activated with the linear enable LINEAR_EN, the low level signal inverted and amplified through the inverter INV is input to the gate of the first PMOS transistor P411. The PMOS transistor P411 is turned on to supply the first driving current from the supply voltage terminal VDD to the common voltage divider 450. When the linear enable line LINE_EN is deactivated, the linear mode driver 410 turns off the first PMOS transistor P411 to block the first driving current.

The comparator 420 is activated by the flat enable FLAT_EN having a high level input to activate the flat mode trimming operation, and inputs the reference voltage V_REF and the feedback voltage V_FEED having a constant voltage level. It outputs the differential voltage (V_AO) which received and compared the difference.

The comparator 420 may be provided as a current mirror type. In detail, the second, third, fourth, and fifth PMOS transistors P421, P422, P423, and P424 having a source commonly connected to the supply voltage terminal VDD, and the first and second NMOS transistors N421 and N422 having a common source connected to each other. And a fourth NMOS transistor N424 connected to a ground terminal VSS, and a third NMOS transistor N423 connected to a source of a drain of the fourth NMOS transistor N424. The second and third PMOS transistors P421 and P422 connect a common connected drain to the differential voltage V_AO of the comparator 420 and the drain of the first NMOS transistor N421, respectively, and have a gate and a drain connected thereto. The gate of the 4 PMOS transistor P423 is connected to the gate of the third PMOS transistor P422, and the fourth and fifth PMOS transistors P423 and P424 connect a common connected drain to the drain of the second NMOS transistor N422. The third NMOS transistor N423, which receives the bias signal VBIAS as a gate, connects the drain to a common connected source of the first and second NMOS transistors N421 and N422. Each gate of the second and fifth PMOS transistors P421 and P424 and the fourth NMOS transistor N424 is connected to a flat enable FLAT_EN, and a gate of the first NMOS transistor N421 is connected to a reference voltage V_REF. The gate of the second NMOS transistor N422 is connected to the feedback voltage V_FEED.

The flat mode driver 430 includes a sixth PMOS transistor P431. The differential voltage V_AO is connected to the gate, and both ends of the source and drain are connected to the supply voltage terminal VDD and the common voltage divider 450, respectively. The second driving current is supplied to the common voltage divider 450 in response to the differential voltage V_AO. The flat mode driver 430 does not supply the second driving current to the common voltage divider 450 when the flat enable FLAT_EN is deactivated.

The common voltage divider 450 generates a plurality of first and second voltages in response to the first and second driving currents according to the linear mode trimming operation or the flat mode trimming operation. In the case of the flat mode trimming operation, the specified one of the plurality of second voltages is output as the feedback voltage V_FEED.

The common voltage divider 450 includes resistance strings RA, R0 to R15, and RB. In detail, an ultrashort resistor RA connected between the output of the linear mode driver 410 and the output of the flat mode driver 430, and a resistance string R0 connected between the output of the flat mode driver 430 and the ground terminal VSS. R15) and terminal resistance (RB). Here, the ultra short resistance RA and the resistor RB serve to roughly set a range of the plurality of first and second voltages generated, thereby precisely setting the voltages by the remaining resistors R0 to R15 of the resistance string. Trimming is possible. For reference, according to another exemplary embodiment, the ultra short resistance RA and the resistor RB may be omitted.

In the linear mode trimming operation, the common voltage divider 450 supplies the first driving current to the ultra short resistor RA, the resistor strings R0 to R15, and the terminal resistor RB to provide a voltage according to the ratio of each resistor size. Is distributed, and a plurality of first voltages are output to the nodes n0 to n15 of the resistance strings R0 to R15 and the terminal resistor RB.

In addition, the common voltage divider 450 supplies the second driving current to the resistance strings R0 to R15 and the terminal resistor RB in the flat mode trimming operation, and divides the voltage according to the ratio of the resistance sizes. A plurality of second voltages are output to the nodes n0 to n15 of the resistance strings R0 to R15 and the terminal resistor RB. Here, the voltage of the node n12 specified among the plurality of second voltages is output as the feedback voltage V_FEED.

The voltage selector 460 selects one of a plurality of first and second voltages according to the linear mode trimming operation or the flat mode trimming operation, and outputs a target voltage V_TRIM.

The voltage selector 460 may include switches SW0 to SW15 having one end connected to each node n0 to n15 of the resistance strings R0 to R15 and the terminal resistor RB, and the other end connected to each other. Outputs the target voltage V_TRIM by selecting one of the plurality of first and second voltages generated by the common voltage divider 450 according to the linear mode trimming operation or the flat mode trimming operation as the switches SW0 to SW15. do. For reference, the voltage selector 460 may be omitted according to another exemplary embodiment.

Hereinafter, the linear mode trimming operation and the flat mode trimming operation in the trimming processing unit (FIGS. 3 and 400) will be described.

In the linear mode trimming operation of the trimming unit (FIGS. 3 and 400), when the linear enable LINEAR_EN having a high level is input, the first PMOS transistor P411 is turned on completely. The first driving current is supplied to the common voltage divider 450 from the supply voltage terminal VDD. The common voltage divider 450 flows the first driving current to the resistance strings RA, R0 to R15 and RB to generate a plurality of first voltages, and the voltage selector 460 operates the switches SW0 to SW15. Operation to output the target voltage (V_TRIM).

In the flat mode trimming operation of the trimming unit (FIGS. 3 and 400), when the flat enable FLAT_EN having a high level and the bias signal VBIAS having a constant voltage level for determining the bias current of the comparing unit 420 are inputted, The comparator 420 is activated by flowing a bias current. The activated comparator 420 compares the voltage level between the reference voltage V_REF and the feedback voltage V_FEED. When the feedback voltage V_FEED is greater than the reference voltage V_REF, the voltage level of the differential voltage V_AO increases. If the voltage is smaller than the reference voltage V_REF, the voltage level of the differential voltage V_AO is reduced. When the voltage level of the differential voltage V_AO increases, the sixth PMOS transistor P431 decreases the current supply, and conversely, when the voltage level of the differential voltage V_AO decreases, the sixth PMOS transistor P431 turns off. ON to increase the current to regulate the second drive current. In response to the second driving current, the resistance strings R0 to R15 and the terminal resistor RB generate a plurality of second voltages at the nodes n0 to n15 and compare the voltages of the specified nodes n12 with each other. It outputs to the feedback voltage V_FEED of 420. Here, a negative feedback operation in which the feedback voltage V_FEED generated in response to the differential voltage V_AO of the comparator 420 is used as the input of the comparator 420 is performed again.

By the negative feedback operation as described above, the flat mode driver in response to the amplified signal V_AO amplified by comparing the level between the reference voltage V_REF having a constant voltage level and the feedback voltage V_FEED of the specified node n12. Since 430 adjusts and supplies a second driving current to the common voltage divider 450, the common voltage divider 450 supplies a plurality of second voltages that are not affected by a change in the voltage level of the supply voltage terminal VDD. As a result, the target voltage V_TRIM from which one of the plurality of second voltages is selected and output is not affected by the variation of the voltage level of the supply voltage terminal VDD.

As described above, since the voltage trimming circuit according to the embodiment of the present invention can selectively use the linear mode trimming operation and the flat mode trimming operation, the linear mode trimming operation and the flat mode trimming operation in the semiconductor device including the voltage trimming circuit. One of the most suitable trimming operation modes can be selected and used.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

410: linear mode drive unit
420: comparison unit
430: flat mode drive unit
450: common voltage distribution
460: voltage selector

Claims (8)

A common voltage distribution unit for distributing a voltage between both ends of the resistance string through which the driving current flows;
A comparator for comparing a reference voltage and a feedback voltage output from the common voltage divider in response to an activated flat mode enable signal;
A flat mode driver configured to supply the driving current to the common voltage divider in response to an output signal of the comparator;
Linear mode driver for supplying the drive current to the common voltage distribution in response to the linear mode enable signal is activated
A voltage trimming circuit comprising:
The method of claim 1,
The linear mode enable signal and the flat mode enable signal are not activated simultaneously with each other.
The method of claim 1,
In response to a test mode signal, the control unit activates one of the linear mode enable signal and the flat mode enable signal in response to a test mode signal, and after the test mode operation, the linear mode enable signal and A mode signal generation unit controlling to activate one of the flat mode enable signals
Voltage trimming circuit further comprising
The method of claim 1,
Voltage selector for selecting and outputting the voltage of each node of the resistance string using a plurality of switches connected to each node of the resistance string
Voltage trimming circuit further comprising
A common voltage divider including a resistor string connected in series between the pull-up node and the ground voltage terminal;
A comparator for comparing a reference voltage and a feedback voltage output from the common voltage divider in response to a flat mode enable signal;
A flat mode driver for driving the pull-up node to a power voltage in response to an output signal of the comparator;
Linear mode driver for driving the pull-up node to the power supply voltage in response to the linear mode enable signal
A voltage trimming circuit comprising: The method of claim 5, wherein
The linear mode enable signal and the flat mode enable signal are not activated simultaneously with each other.
The method of claim 5, wherein
In response to a test mode signal, the control unit activates one of the linear mode enable signal and the flat mode enable signal in response to a test mode signal, and after the test mode operation, the linear mode enable signal and Morse signal generation unit for controlling to activate one of the flat mode enable signal
Voltage trimming circuit further comprising
The method of claim 5, wherein
Voltage selector for selecting and outputting the voltage of each node of the resistance string using a plurality of switches connected to each node of the resistance string
Voltage trimming circuit further comprising
KR1020120096735A 2012-08-31 2012-08-31 circuit for trimming voltage KR101965360B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060111798A (en) * 2005-04-25 2006-10-30 주식회사 하이닉스반도체 Internal voltage circuit for semiconductor device
KR20070077875A (en) * 2006-01-25 2007-07-30 주식회사 하이닉스반도체 A reference voltage generating circuit of semiconductor memory device
KR20080060389A (en) * 2006-12-27 2008-07-02 주식회사 하이닉스반도체 Internal voltage generator and generation method in semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060111798A (en) * 2005-04-25 2006-10-30 주식회사 하이닉스반도체 Internal voltage circuit for semiconductor device
KR20070077875A (en) * 2006-01-25 2007-07-30 주식회사 하이닉스반도체 A reference voltage generating circuit of semiconductor memory device
KR20080060389A (en) * 2006-12-27 2008-07-02 주식회사 하이닉스반도체 Internal voltage generator and generation method in semiconductor device

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