KR20140021320A - Data input circuit of semiconductor apparatus - Google Patents

Data input circuit of semiconductor apparatus Download PDF

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Publication number
KR20140021320A
KR20140021320A KR1020120087598A KR20120087598A KR20140021320A KR 20140021320 A KR20140021320 A KR 20140021320A KR 1020120087598 A KR1020120087598 A KR 1020120087598A KR 20120087598 A KR20120087598 A KR 20120087598A KR 20140021320 A KR20140021320 A KR 20140021320A
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KR
South Korea
Prior art keywords
signal
generate
response
enable signal
pattern data
Prior art date
Application number
KR1020120087598A
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Korean (ko)
Inventor
김재일
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020120087598A priority Critical patent/KR20140021320A/en
Publication of KR20140021320A publication Critical patent/KR20140021320A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects

Abstract

The present invention relates to a data input circuit of a semiconductor device capable of self-adjust to fit timing margins related to a write operation into the features of the semiconductor device. The data input circuit comprises: a pattern data generating unit which generates pattern data in response to a first strobe signal; a variable delay unit which generates a write enable signal by delaying a second strobe signal for a delay time corresponding to a delay control signal; and a control block which generates the delay control signal in response to the phase of the pattern data and the write enable signal. [Reference numerals] (200) Data write path block; (32) Memory block; (400) Write enable signal path block; (500) Control block

Description

DATA INPUT CIRCUIT OF SEMICONDUCTOR APPARATUS}

The present invention relates to a semiconductor device, and more particularly to a data input circuit of the semiconductor device.

Semiconductor Device For example, when a write command is input, the semiconductor memory device writes data input through the pad DQ to memory cells inside the memory bank through the global line GIO.

The memory bank includes a driver for writing data transmitted through a data input path (including a global line) to a memory cell through an internal input / output line (eg, BIO, LIO, etc.) according to a write enable signal.

At this time, in order for the write operation, that is, the data input to be stable, the data and the write enable signal transmitted through the global line must have a predetermined timing margin.

1 is a block diagram of a data input circuit 1 of a semiconductor device according to the prior art.

As shown in FIG. 1, the data input circuit 1 of the semiconductor device according to the related art includes a data write path block 10, a write enable signal path block 20, and a memory bank 30.

The data write path block 10 includes a buffer 11, an alignment unit 12, latches 13 and 14, a global line driver 15, and a global line GIO.

The buffer 11 receives data through the pad DQ.

The alignment unit 12 aligns the data input through the buffer 11 in response to the strobe signals DQSR and DQSF.

The latches 13 and 14 latch the data ALGNR0, ALGNF0, ALGNR1, and ALGNF1 arranged through the alignment unit 12 in response to the clock signals DCLK1 and DCLK2, respectively.

The global line driver 15 transmits the output signals of the latches 13 and 14 to the global line GIO in response to the strobe signal DINSTBP.

The write enable signal path block 20 includes a pulse width adjusting unit 21, delay units 22 and 25, a plurality of signal generators 23, 24, and 26, and a plurality of logic gates.

The pulse width adjusting unit 21 adjusts and outputs the pulse width of the strobe signal CASPWT.

The delay unit 22 adjusts and outputs the delay time of the output signal of the pulse width adjustment unit 21.

The signal generator 23 generates a switching signal DATASTB <0: 7> in response to the output signal of the pulse width adjuster 21.

The signal generator 24 generates a bank select signal AYP <0: 7> by combining the output signal of the delay unit 22 and the bank addresses BKA <0: 7>.

The signal generator 26 generates strobe signals DINSTBP and CASPWT in response to the write command WT and the address signal ADD.

When the write state signal WTS defines the write operation, the delay unit 25 generates the write enable signal BWEN in response to the bank select signal AYP <i> corresponding to the memory bank 30. .

The memory bank 30 includes a memory block 30 and a driver 31.

The driver 31 transmits data transmitted through the global line GIO to the memory block through the input / output lines BIO and LIO in response to the write enable signal BWEN and the corresponding switching signal DATASTB <i>. Record at 30.

For stable write operation, the GIO vs BWEN margin, that is, the data transmission of the global line GIO and the timing margin of the write enable signal BWEN must be constant.

Since the switching signal DATASTB <i> is transmitted to the driver 31 of the memory bank 30 through a short path, it is almost impossible for the margin to be insufficient compared to the GIO.

However, in the case of BWEN, the multi-stage delay part causes the logic gate delay of the multi-stage, which may result in insufficient margins compared to GIO, and the margin is further insufficient due to the influence of PVT (Process, Voltage or / and Temperature). It can cause a (Fail).

An embodiment of the present invention provides a data input circuit of a semiconductor device in which the timing margin related to write operation can be adjusted according to the characteristics of the semiconductor device.

An embodiment of the present invention includes a pattern data generator configured to generate pattern data in response to a first strobe signal; A variable delay unit configured to delay the second strobe signal by a delay time corresponding to the delay control signal to generate a write enable signal; And a control block configured to generate the delay control signal in response to a phase of the pattern data and the write enable signal.

An embodiment of the present invention includes a data write path block configured to write internally generated pattern data in the memory bank in response to a first strobe signal; A memory bank configured to write the pattern data in response to a write enable signal; A write enable signal path block configured to delay the second strobe signal by a delay time corresponding to a delay control signal to generate the write enable signal; And a control block configured to generate the delay control signal in response to a phase of the pattern data and the write enable signal.

Embodiments of the present invention can stably write data regardless of PVT variation.

1 is a block diagram of a data input circuit 1 of a semiconductor device according to the prior art;
2 is a block diagram of a data input circuit 100 of a semiconductor device according to an embodiment of the present invention;
3 is a circuit diagram illustrating an internal configuration of the data write path block 200 of FIG. 2.
4 is a circuit diagram illustrating an internal configuration of the write enable signal path block 400 of FIG. 2.
FIG. 5 is a circuit diagram illustrating an internal configuration of the control block 500 of FIG. 2.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a data input circuit 100 of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a circuit diagram illustrating an internal configuration of the data write path block 200 of FIG. 2.

As illustrated in FIG. 2, the data input circuit 100 of the semiconductor device according to the embodiment of the present invention may include a data write path block 200, a write enable signal path block 400, a control block 500, and a memory. Bank 30.

The memory bank 30 includes a memory block 32 and a driver 31.

The driver 31 transmits data transmitted through the global line GIO to the memory block through the input / output lines BIO and LIO in response to the write enable signal BWEN and the corresponding switching signal DATASTB <i>. Record at 30.

As illustrated in FIG. 3, the data write path block 200 may include a buffer 11, an alignment unit 12, latches 13 and 14, a global line driver 15, a global line GIO, and a pattern generator. And 210.

The buffer 11 receives data through the pad DQ.

The alignment unit 12 aligns the data input through the buffer 11 in response to the strobe signals DQSR and DQSF.

The latches 13 and 14 latch the data ALGNR0, ALGNF0, ALGNR1, and ALGNF1 arranged through the alignment unit 12 in response to the clock signals DCLK1 and DCLK2, respectively.

The global line driver 15 transmits the output signals of the latches 13 and 14 to the global line GIO in response to the strobe signal DINSTBP.

The pattern generator 210 includes a pattern generator 211 and a path blocker 212.

The pattern generator 211 generates the pattern data GIO_TPH in response to the margin adjustment enable signal BWEN_TUNEN and the strobe signal DINSTBP.

The pattern generator 211 generates the pattern data GIO_TPH in response to the strobe signal DINSTBP when the margin adjustment enable signal BWEN_TUNEN is activated.

The pattern generator 211 initially transitions the pattern data GIO_TPH from logic low to logic high in response to the strobe signal DINSTBP, and repeats the transition of the pattern data GIO_TPH in response to the strobe signal DINSTBP. It is configured to.

In this case, in the case of a global line adjacent to the global line GIO in which the margin adjustment operation is performed, data is shifted in reverse.

For example, when the pattern data of GIO No. 1 is transitioned as low-high-low, the data of GIO No. 2 adjacent thereto is transitioned as high-low-high.

The path blocking unit 212 deactivates the clock signals DCLK1 and DCLK2 when the margin adjustment enable signal BWEN_TUNEN is activated.

As the clock signals DCLK1 and DCLK2 are deactivated, the normal data write path from the pad DQ to the global line driver 15 is blocked.

4 is a circuit diagram illustrating an internal configuration of the write enable signal path block 400 of FIG. 2.

As shown in FIG. 4, the write enable signal path block 400 includes a pulse width adjusting unit 21, a delay unit 22, 25, a plurality of signal generators 23, 24, 420, and a plurality of logic gates. And a variable delay unit 410.

The pulse width adjusting unit 21 adjusts and outputs the pulse width of the strobe signal CASPWT.

The delay unit 22 adjusts and outputs the delay time of the output signal of the pulse width adjustment unit 21.

The signal generator 23 generates a switching signal DATASTB <0: 7> in response to the output signal of the pulse width adjuster 21.

The signal generator 24 generates a bank select signal AYP <0: 7> by combining the output signal of the delay unit 22 and the bank addresses BKA <0: 7>.

The strobe signal generator 420 generates strobe signals DINSTBP and CASPWT in response to the write command WT and the address signal ADD.

At this time, the write command WT and the address signal ADD are signals generated during the normal write operation.

The strobe signal generator 420 generates strobe signals DINSTBP and CASPWT even when the source signal EWL_BWEN is generated.

In this case, the source signal EWL_BWEN is a signal generated regardless of the normal light operation in order to perform the margin adjustment operation in the embodiment of the present invention.

When the write state signal WTS defines the write operation, the delay unit 25 generates the write enable signal BWEN in response to the bank select signal AYP <i> corresponding to the memory bank 30. .

The variable delay unit 410 delays and outputs the output signal of the delay unit 22 by a variable delay time in response to the delay control signals DLY <0: 7>.

FIG. 5 is a circuit diagram illustrating an internal configuration of the control block 500 of FIG. 2.

As shown in FIG. 5, the control block 500 includes a delay time controller 600 and a margin adjustment enable signal generator 700.

The delay time controller 600 includes a detector 610, a counter 620, and a decoder 630.

When the margin adjustment enable signal BWEN_TUNEN is activated, the detector 610 transmits the pattern through the input / output line BIO in the memory bank 30 via the write enable signal BWEN and the global line GIO. The detection signals BWEN_DLY_INC, BWEN_GEN_RST, and BWEN_TUNDIS are generated in response to the data GIO_TPH.

The detector 610 generates the detection signals BWEN_DLY_INC, BWEN_GEN_RST, and BWEN_TUNDIS by comparing the phase of the pattern data GIO_TPH transmitted through the write enable signal BWEN and the input / output line BIO.

The detector 610 compares each of the rising edge and the falling edge of the pattern data GIO_TPH transmitted through the input / output line BIO with the rising edge of the write enable signal BWEN.

The detector 610 activates the detection signals BWEN_DLY_INC and BWEN_GEN_RST when the rising edge of the write enable signal BWEN is faster than the rising edge or the falling edge of the pattern data GIO_TPH.

The detector 610 activates the detection signal BWEN_TUNDIS when the rising edge of the write enable signal BWEN is later than both the rising edge and the falling edge of the pattern data GIO_TPH.

At this time, in the embodiment of the present invention, only the example of using the input / output line BIO in the memory bank 30 as a target for comparing the margin with the write enable signal BWEN, and the margin with the write enable signal BWEN It is also possible to use the global line (GIO) as the object of comparison.

The detector 610 may include a plurality of delay units DLY, a latch SR_LATCH, a plurality of flip-flops DFF, a plurality of logic gates, and a plurality of transistors.

The detector 610 is initialized by the reset signal RSTB.

The counter 620 counts the detection signal BWEN_DLY_INC to generate the preliminary delay control signal DLY_PRE <0: 2>.

The counter 620 is initialized by the reset signal RSTB.

The decoder 630 generates the delay control signal DLY <0: 7> by decoding the preliminary delay control signal DLY_PRE <0: 2>.

The margin adjustment enable signal generator 700 includes a delay unit DLY, a latch SR_LATCH, a plurality of flip-flops DFF, a plurality of transistors, and a plurality of logic gates.

The margin adjustment enable signal generator 700 is configured to activate the margin adjustment enable signal BWEN_TUNEN after a set time (eg, 2tCK) after being initialized by the reset signal RSTB.

The margin adjustment enable signal generator 700 generates the source signal EWL_BWEN after the margin adjustment enable signal BWEN_TUNEN is activated and after a set time (eg, 1tCK).

The margin adjustment enable signal generator 700 generates a source signal EWL_BWEN when the detection signal BWEN_GEN_RST is activated.

When the detection signal BWEN_TUNDIS is activated, the margin adjustment enable signal generator 700 disables the source signal EWL_BWEN and the margin adjustment enable signal BWEN_TUNEN so that the margin adjustment operation is terminated.

Referring to the data input operation, that is, the write operation according to the embodiment of the present invention, as follows.

The initialization process of the semiconductor device, that is, the reset signal RSTB is activated, and after a set time (eg, 2tCK), the margin adjustment enable signal BWEN_TUNEN is activated by the control block 500.

The margin adjustment enable signal BWEN_TUNEN is activated and a source signal EWL_BWEN having a set pulse width (eg 1tCK) is generated after the set time (eg 1tCK).

As the source signal EWL_BWEN is generated, the write enable signal BWEN having a variable delay time is generated through the variable delay unit 410.

 As the source signal EWL_BWEN is generated, the strobe signal DINSTBP is also generated.

At this time, the write enable signal BWEN and the strobe signal DINSTBP due to the source signal EWL_BWEN are generated regardless of the write operation.

Meanwhile, as the margin adjustment enable signal BWEN_TUNEN is activated and the strobe signal DINSTBP is generated, the pattern data GIO_TPH is toggled.

At this time, the pattern data GIO_TPH basically transitions from a logic low to a logic high and shifts whenever the strobe signal DINSTBP occurs.

In the control block 500, detection signals BWEN_DLY_INC, BWEN_GEN_RST, and BWEN_TUNDIS are generated by comparing the phase of the pattern data GIO_TPH transmitted through the write enable signal BWEN and the input / output line BIO.

If the rising edge of the write enable signal BWEN is faster than the rising edge or the falling edge of the pattern data GIO_TPH, the detection signals BWEN_DLY_INC and BWEN_GEN_RST are generated.

As the detection signals BWEN_DLY_INC and BWEN_GEN_RST are generated, the delay time of the variable delay unit 410 increases.

Accordingly, the write enable signal BWEN is delayed, the pattern data GIO_TPH is toggled again, and the phase comparison between the above-described write enable signal BWEN and the pattern data GIO_TPH is repeated.

On the other hand, if the rising edge of the write enable signal BWEN is later than both the rising edge and the falling edge of the pattern data GIO_TPH, the detection signal BWEN_TUNDIS is generated.

As the detection signal BWEN_TUNDIS is generated, the margin adjustment enable signal BWEN_TUNEN and the source signal EWL_BWEN are deactivated.

As the margin adjustment enable signal BWEN_TUNEN and the source signal EWL_BWEN are deactivated, the margin data adjustment operation is terminated by deactivating the pattern data GIO_TPH and the strobe signal DINSTBP.

According to the embodiment of the present invention, the above-described margin adjustment operation may be performed during the initialization process of the semiconductor device, so that the GIO vs BWEN margin may be adjusted to an optimal level regardless of the PVT variation.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (18)

A pattern data generator configured to generate pattern data in response to the first strobe signal;
A variable delay unit configured to delay the second strobe signal by a delay time corresponding to the delay control signal to generate a write enable signal; And
And a control block configured to generate the delay control signal in response to a phase of the pattern data and the write enable signal. The method of claim 1,
And the first strobe signal and the second strobe signal are generated by the same source signal. The method of claim 1,
And a driver configured to write the pattern data to a memory block in response to the write enable signal. The method of claim 1,
The control block
A detector configured to generate a detection signal in response to a phase comparison result of the pattern data and the write enable signal;
A counter configured to count the detection signal to generate a preliminary delay control signal;
And a decoder configured to decode the preliminary delay control signal to generate the delay control signal. The method of claim 1,
The pattern data generation unit
And generate the pattern data in response to the first strobe signal when a margin adjustment enable signal is activated. The method of claim 5, wherein
The control block
A delay time controller configured to generate the delay control signal in response to the pattern data and the write enable signal;
And a margin adjustment enable signal generator configured to generate the margin adjustment enable signal in response to a reset signal. The method according to claim 6,
The delay time controller
A detector configured to generate a detection signal in response to a phase comparison result of the pattern data and the write enable signal;
A counter configured to count the detection signal to generate a preliminary delay control signal;
And a decoder configured to decode the preliminary delay control signal to generate the delay control signal. The method of claim 7, wherein
The margin adjustment enable signal generator
And a data input circuit configured to generate a source signal when the detection signal is activated. The method of claim 8,
And a strobe signal generator configured to generate the first strobe signal and the second strobe signal in response to the source signal. A data write path block configured to write internally generated pattern data in the memory bank in response to a first strobe signal;
A memory bank configured to write the pattern data in response to a write enable signal;
A write enable signal path block configured to delay the second strobe signal by a delay time corresponding to a delay control signal to generate the write enable signal; And
And a control block configured to generate the delay control signal in response to a phase of the pattern data and the write enable signal. 11. The method of claim 10,
The light path block is
An alignment unit configured to align data input through the pad,
A pattern data generator configured to generate the pattern data in response to the first strobe signal;
A latch configured to latch an output signal of the alignment unit in response to a clock signal;
A global line connected with the memory bank, and
And a global line driver configured to transmit the output signal of the latch or the pattern data to the global line. 11. The method of claim 10,
The write enable signal path block is
A strobe signal generator configured to generate the first strobe signal and the second strobe signal in response to a source signal;
A variable delay unit configured to delay the second strobe signal by a delay time corresponding to a delay control signal, and
And a circuit block configured to generate the write enable signal using the output signal of the variable delay unit. 13. The method of claim 12,
The control block
A delay time controller configured to generate the delay control signal in response to the pattern data and the write enable signal;
And a margin adjustment enable signal generator configured to generate a margin adjustment enable signal and the source signal in response to a reset signal. The method of claim 13,
The delay time controller
A detector configured to generate a detection signal in response to a phase comparison result of the pattern data and the write enable signal;
A counter configured to count the detection signal to generate a preliminary delay control signal;
And a decoder configured to decode the preliminary delay control signal to generate the delay control signal. 15. The method of claim 14,
The margin adjustment enable signal generator
And generate the source signal in response to the detection signal. 11. The method of claim 10,
The light path block is
And when the margin adjustment enable signal is activated, write the internally generated pattern data to the memory bank in response to the first strobe signal. 17. The method of claim 16,
The light path block is
And when the margin adjustment enable signal is deactivated, block a path in which externally input data is written to the memory bank. The method of claim 11,
The pattern data generation unit
And deactivate the latch when a margin adjustment enable signal is deactivated.
KR1020120087598A 2012-08-10 2012-08-10 Data input circuit of semiconductor apparatus KR20140021320A (en)

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KR1020120087598A KR20140021320A (en) 2012-08-10 2012-08-10 Data input circuit of semiconductor apparatus

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Application Number Priority Date Filing Date Title
KR1020120087598A KR20140021320A (en) 2012-08-10 2012-08-10 Data input circuit of semiconductor apparatus

Publications (1)

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KR20140021320A true KR20140021320A (en) 2014-02-20

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