KR20140006447A - Encoding, decoding, and multi-stage decoding circuits and methods for concatenated bch code, error correct circuit of flash memory device using the same, and flash memory device using the same - Google Patents

Abstract

The present invention relates to a connected BCH code, a decode, a multi-layer code circuit and a method, an error correction circuit of a flash memory device using the same, and a flash memory device, capable of controlling delay time according to error degrees by executing the coding, the decoding, and the multi-layer decoding for the flash memory device. The present invention relates to a connected BCH multi-layer decoding circuit comprising: a first stage decoding unit for outputting a first output BCH code and a first output data protected by the first output BCH code by executing the BCH coding by receiving a part of the connected BCH code; a deinterleaving unit for outputting the first output BCH code or the first output data by dividing the first output BCH coding or the first output data into two or more blocks; a second stage decoding unit for outputting second output data protected by second output BCH coding by executing the BCH decoding in the output of the deinterleaving unit; an interleaving unit for outputting a second output BCH code or the second output data by dividing the second output BCH coding or the second output data into two or more blocks; and a decoder power control unit for temporally blocking power supply until the reception of a new connected BCH coding for a decoding success block and by obtaining the decoding success block by monitoring the operation state of the first and the second stage decoding unit.

Description

CONNECTION, DECODING, AND MULTI-STAGE DECODING CIRCUITS AND METHODS FOR CONCATENATED BCH CODE, ERROR CORRECT CIRCUIT OF FLASH MEMORY DEVICE USING THE SAME, AND FLASH MEMORY DEVICE USING THE SAME}

The present invention relates to concatenated Bose-Chadhuri-Hocquenghem (BCH) Encode, Decode, and multilayer decoding circuits and methods, and error correction circuits and flash memory devices of flash memory devices using the same. More specifically, the concatenated BCH code improves the error correction performance of the flash memory, and the multi-layer decoding adjusts the delay time according to the degree of error, and further reduces the power consumption significantly. A code, decoding and multi-layer decoding circuit and method, and an error correction circuit and a flash memory device of a flash memory device using the same.

In recent years, as the speed of main memory devices such as processors and RAMs used in many electronic products increases, bottlenecks in which the computational processing speed of electronic products is determined by the speed of the auxiliary memory device are intensifying. Existing secondary storage devices mainly used magnetic storage devices such as HDD (Hard Disk Drive), and optical disk devices (ODD, Optic Disc Drive) such as CD or DVD. Among them, optical disk devices are not free for data input and output, and the speed of data output is extremely slow. In addition, the magnetic storage device is faster than the optical disk device, but still causes bottlenecks, and the data may be easily damaged or lost due to the impact.

Thus, solid state drives (SSDs) composed of semiconductor devices using the conventional MOSFET structure are emerging.

SSDs are faster than HDDs and can store data at high speeds without any search time through random access. In addition, the mechanical delay or failure rate is remarkably small and data is not damaged by external shock. In addition, since SSD consumes little power and does not require a separate mechanical device to drive, low heat generation, low noise, and low power driving are possible, which makes it possible to reduce the size and weight of a product including the SSD.

SSDs generally include NOR flash memory configured in NOR and NAND flash memory configured in NAND. Among them, NAND flash memory is connected in series, so the circuit density is high, so it is easy to make a large capacity, and the read / write speed is fast. In addition, NAND flash memory is used in most large-capacity SSDs because of its excellent data storage capacity and easy to make large capacity.

However, NAND flash memory devices are becoming more and more miniaturized due to the use of micro processes and an increase in the number of storage bits per cell. This increase in storage density has increased side effects such as deterioration of device reliability and shortening of lifespan.

Referring to FIG. 1, the problem and the necessity of an error correction code according to an increase in the storage density of the NAND flash memory will be described.

Referring to FIG. 1, a single-level cell (SLC) flash memory (a) is a NAND element that stores one bit of information, and a multi-level cell (MLC) flash memory (b) stores two bits of information. NLC device, TLC (Tri-Level Cell) flash memory (c) is a NAND device that stores three bits of information, QLC (Quad-Level Cell) flash memory (d) is a NAND device that stores four bits of information to be.

Referring to FIG. 1, as the number of bits to be stored per cell increases, the probability of an error due to inter-level interference during a read operation increases, and as the read / write operation is repeated, an error occurrence probability increases greatly. The problem of inferior reliability arises. Therefore, low power and high throughput error correction circuits are essential for the design of reasonable and reliable NAND flash memory.

In order to solve such a problem, an error correction code is generally used. The error correction code requires extra bits containing information for detecting and correcting the error. Thus, an extra area of the cell is required to store the extra bits. However, in order to maximize the storage capacity of the storage medium, the area of the cell required to store the extra bits is minimized, and thus there is a need to minimize the extra bits.

In addition, due to an increase in stored data errors, new error correction codes are required to replace existing BCH codes or Reed-Solomon (RS) codes that require exponential complexity and many extra bits for the number of errors.

The higher the error correction code, the higher the complexity and the longer the decoding delay time. In the case of NAND flash memory, fewer errors occur initially, but the number of errors increases as the usage time increases. Simply using a high performance error correction code is not efficient because it has a longer decoding delay time than necessary when there are few errors.

The technical problem to be solved by the present invention is to adjust the delay time according to the degree of error through the code, decoding and multi-layer decoding for the flash memory device, and the power consumption of the decoding operation The present invention provides a concatenated BCH code, a decoding, and a multi-layer decoding circuit and method for reducing the number.

Another object of the present invention is to provide an error correction circuit and a flash memory device of a flash memory device.

The solution to the problem of the present invention is not limited to those mentioned above, and other solutions not mentioned can be clearly understood by those skilled in the art from the following description.

As a means for solving the above-described technical problem, the concatenated BCH code circuit according to the present invention receives a portion of the concatenated BCH code to perform BCH decoding to output a first output BCH code or first output data protected by the concatenated BCH code. A first stage decoder; A deinterleaving unit for de-interleaving and outputting the first output BCH code or the first output data into two or more blocks; A second stage decoder for BCH decoding the output of the deinterleaving unit to output a second output BCH code or second output data protected by the second output BCH code; An interleaving unit dividing the second output BCH code or the second output data into two or more blocks and interleaving the interleaving unit to output the first output BCH code to the first stage decoder; And a decoder power controller configured to monitor operation states of the first and second stage decoders to identify a decoding success block, and temporarily block power supply until a new concatenated BCH code is input to the decoding success block. have.

Here, the concatenated BCH decoding circuit repeats column decoding and row decoding in an iterative decoding manner, and may repeat the repetition by a maximum number of repetitions or a repetition termination condition.

Here, the first stage decoder is a plurality of column code decoders, the second stage coder is a plurality of row code decoders, and the deinterleaving unit is a block unit deinterleaver. interleaver, and the interleaving unit may be a block-wise interleaver.

Here, the decoder power control unit recognizes a decoder that has successfully decoded by using decoding failure information transmitted from each of the plurality of column decoders and the plurality of row decoders, and successfully decodes the decoder. The power supply to the decoder can be temporarily interrupted until a new concatenated BCH code is received.

Here, the concatenated BCH decoding circuit combines the outputs of the first and second stage decoders in the flash memory core when the first and second stage decoders successfully decode the columns and the rows. A codeword to be generated can be generated.

In addition, the concatenated BCH code circuit receives decoding failure information from the first and second stage decoders and receives the second output BCH code or the second output data protected by the second BCH coder to perform additional decoding on the decoding failure block. An additional decoder may be further included.

Here, when the decoding failure of the concatenated BCH code occurs for a few error blocks, the additional decoder may correct only the error by performing additional decoding by obtaining only additional information corresponding to the error block.

Here, the additional information may include information about bits corresponding to a small number of error blocks in which position is determined.

In this case, the additional decoding unit may determine the positions of the few error blocks by receiving whether or not each component code has failed to be decoded in both the first and second stage decoders for the additional decoding.

The configuration code may be a part or all of a page that is a read and write unit, a column code, or a row code.

In addition, as a means for solving the above-described technical problem, the error correction circuit of the flash memory device according to the present invention, after separating the input data into two or more data, each BCH coded by the same number of rows as the separated data An external coder for outputting a BCH code; An interleaving unit for dividing the row BCH code or data protected by it into two or more blocks, interleaving the blocks, and outputting the same number of blocks; An internal coder for BCH encoding the interleaved blocks in the interleaving unit to output a column BCH code; A first stage decoder configured to receive a portion of stored data provided from a flash memory core to perform BCH decoding to output a first output BCH code or first output data protected by the first output BCH code; A deinterleaving unit configured to deinterleave and output the first output BCH code or the first output data into two or more blocks; A second stage decoding unit for BCH decoding the output of the deinterleaving unit to output a second output BCH code or second output data protected by the second output BCH code; An interleaving unit dividing the second output BCH code or the second output data into two or more blocks and interleaving the interleaving unit to output the first output BCH code to the first stage decoder; And a decoder power controller configured to monitor operation states of the first and second stage decoders to identify a decoding success block, and temporarily block power supply until a new concatenated BCH code is input to the decoding success block. have.

According to the present invention, the BCH code is an outer code and an inner code, but the outer code is interleaved in block units to be encoded into an inner code, and the encoded stored data is decoded into multiple layers according to an error degree, thereby selecting either an outer code or an inner code. Error correction by decoding only the code, repeating the internal and external code repeatedly until the error is completely corrected or can no longer be fixed, or by obtaining additional information when a block unit error occurs. It is possible to improve the capability and adaptively reduce the decoding delay time.

In addition, when the error is corrected by the decoding of the outer code or the inner code due to the small number of errors, access to the small size data which is a part of the entire data becomes easy.

In addition, the power supply is temporarily cut off for the decoding successive decoders in the decoding operation, so that the decoding succession decoders are excluded from the iterative decoding operation, thereby reducing the average number of decoders used for the multi-layer decoding operation, thereby reducing the total number of contiguous BCH decoding circuits. Power consumption can be reduced.

The effects of the present invention are not limited to those mentioned above, and other effects that are not mentioned will be clearly understood by those skilled in the art from the following description.

FIG. 1 is a diagram illustrating a distribution of threshold voltages in a single level cell (SLC), a multi level cell (MLC), a tri-level cell (TLC), and a quad level cell (QLC) flash memory.
2A is a structural diagram of a concatenated BCH code used in the present invention configured in parallel concatenation.
2B is a structural diagram in which a concatenated BCH code used in the present invention is configured in series concatenation.
3A is a functional block diagram illustrating a parallel concatenated BCH code circuit of a flash memory device according to an exemplary embodiment of the present invention.
3B is a functional block diagram illustrating a series concatenated BCH code circuit of a flash memory device according to an exemplary embodiment of the present invention.
4 is a functional block diagram illustrating a concatenated BCH decoding circuit of a flash memory device according to an exemplary embodiment of the present invention.
5 is a functional block diagram illustrating a functional block of a concatenated BCH decoding circuit for a flash memory device according to another embodiment of the present invention.
6 is a diagram illustrating a concatenated BCH multi-layer decoding method of a flash memory device according to an exemplary embodiment of the present invention.
FIG. 7 is a diagram comparing lower bounds and experimental results due to errors in units of blocks of the present invention.
8 is a diagram comparing the performance of the existing BCH code and the experimental results of the decoding method using the additional information for solving one block error of the present invention.
9 is a functional block diagram illustrating a concatenated BCH multilayer decoding circuit capable of further decoding a flash memory device according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly explain the present invention in the drawings, parts not related to the description are omitted, and similar parts are denoted by similar reference numerals throughout the specification.

In general, a flash memory device has a basic structure of dies connected in parallel, and a die is composed of memory blocks, which are units that can be erased at one time. Each memory block is composed of pages that are read / write units. Therefore, the error correction code is preferably performed in units of pages that are read / write units. Units of pages vary from manufacturer to manufacturer, but typically use 1KB pages for SLC devices and 4KB or 8KB pages for MLC devices.

Since flash memory devices require high reliability as a storage device, they must operate in a very low error rate range when an error correction code is applied. In addition, the latency and complexity of the code and decoder are limited for fast read and write speeds. At the same time, the extra space other than the data is limited for the efficiency of the storage space, so that the ratio of parity bits to the total stored data is limited. Therefore, a code suitable for a flash memory device has a high code rate (for example, 0.9 or more), and there is no error floor or a solution that can solve this problem even if there is an error floor. It should be presented on the basis of

The concatenated BCH code used in the present invention is configured in block units. If the concatenated BCH code is used in units of bits rather than blocks in order to improve error correction performance than the existing BCH code, the concatenated BCH code is composed of a plurality of short-length BCH constituent codes. Short length component codes have very small error correction capability (one or two bit correction) due to the high code rate required in flash memory devices. As a result, in a flash memory device capable of hard decision only, a configuration code that fails to correct the bit unit contiguous BCH code easily occurs, and thus the bit unit contiguous BCH code has low performance. In this case, the performance can be improved by using additional information, but since this is required for all decoding, there is a problem of high complexity and relatively long delay time.

The concatenated BCH code in block units used in the present invention has a feature suitable for a flash memory device. The contiguous BCH code in blocks is composed of a few long BCH component codes. Long length component codes have sufficient error correction capability even at the high code rates required in flash memory devices. For example, referring to FIG. 7, it can be seen that the configuration codes are configured to correct errors of 10 bits and 14 bits, respectively. As a result, even in a flash memory device capable of hard decision only, the block contiguous BCH code has a low probability of failing a correction code, and thus has higher performance than the contiguous bit concatenated BCH code.

On the other hand, since the contiguous BCH code in block units is configured in block units, decoding may fail due to an erroneous block. Referring to FIG. 6, it can be seen that an error floor occurs due to a lower bound of the error block. As shown in Figure 6, the error floor is mainly caused by a few error blocks.

Accordingly, the present invention proposes a method for solving an error floor by correcting an error block by obtaining additional information on a few error blocks. Only when the block-wise concatenated BCH code fails hard decision iterative decoding, since additional information is limited to a few error blocks, complexity and decoding delay time can be effectively reduced.

In the following description, unless otherwise specified, the concatenated BCH code refers to a block unit concatenated BCH code.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2A is a structural diagram of a concatenated BCH code used in the present invention configured as parallel concatenation, and FIG. 2B is a structural diagram of a concatenated BCH code used in the present invention configured as a serial concatenation.

A block of contiguous BCH codes is distinguished from a memory block and has a different meaning. A block is a bundle of bits, shown as a rectangle in FIG. 2A or FIG. 2B, but the bits within the block are arranged in a line and have a certain order. The block may include a message block, a parity block, or a message-parity block in which parity blocks are combined after the message block.

There are two types of constituent codes in the concatenated BCH code. For convenience, these are called row and column codes, respectively. Since the role of the row code and the column code in the parallel concatenated structure is the same, in the description, the row code and the column code may be replaced with each other. In the serial concatenation structure, the row code serves as an outer code and the column code serves as an inner code, and cannot be replaced with each other. One row code and one column code always share one block with each other, and the other blocks do not share with each other. In addition, one row code (or column code) shares only one block with all the column codes (or row codes).

Both row and column codes are BCH codes. The row code is a total of n _r bits, the message k _r bits to be protected, and the parity m _r bits to fix t _r bit errors in the entire code. The column code has a total of n _c bits, a protected message k _c bits, and a parity m _c bits, so that t _c bit errors can be corrected within the entire code.

Then, in the description of the embodiment of the present invention, the size of data protected by the concatenated BCH code is k (k is a natural number).

2A is a structural diagram of a concatenated BCH code used in the present invention configured in parallel concatenation.

Referring to Figure 2a, the data is k _r ^B × k _c ^B consisting of a message block Corresponds to the message matrix of size. One line sign is the message block k _c ^B And one or more parity blocks. One column code consists of k _r ^B message blocks and one or more parity blocks.

For example, as shown below, it is possible to configure a parallel concatenated BCH code in which each message block equally includes n _B bits. Referring to FIG. 2A, the i th row code is composed of message blocks of the i th row and a parity block of the i th row, and may be represented by Equation 1 below.

Referring to FIG. 2A, the j th column code is composed of message blocks of the j th column and a parity block of the j th column, and may be represented by Equation 2 below.

In this case, the message length of the row code may be expressed as in Equation 3.

In addition, the code length of the line code can be expressed as in Equation 4.

Similarly, the message length of the column code can be expressed as in Equation 5.

Similarly, the code length of the column code can be expressed as in Equation 6.

In this case, the code rate of the parallel concatenated BCH code may be expressed as shown in Equation (7).

비트를 포함하며 모든 메시지 블록의 크기는 같다.In this embodiment, the message block is

It contains bits and the size of all message blocks is the same.

For an embodiment in which interleaving is different so that different columns have message blocks of different sizes and only message blocks of the same size within one column, the row code is represented by Equation 1, and the column code is represented by Equation 8. Can be.

where f (x) = {(x-1) mod k _c ^B } +1

2B is a structural diagram in which a concatenated BCH code used in the present invention is configured in series concatenation.

Referring to FIG. 2B, data is assigned to a message block, and the last message block of each row is combined with a parity block or part of the row code of that row to become a message-parity block. Except for the parity block of column codes, the message block, the message-parity block of each row, and the extra parity block of each row are k _r ^B × k _c ^B It is a message matrix of size. One line sign is the message block k _c ^B Consists of one and one message-parity block. One column code consists of a message block or a message-parity block k _r ^B and one parity block. In the case of a serially concatenated BCH code, the column code can be designed to correct more errors (t _r ≤ t _c ) than the row code.

For example, as follows, it is possible to configure a serial concatenated BCH code in which each message block and message-parity block include n _B bits equally. Referring to FIG. 2B, the i th row code includes message blocks of the i th row and a parity block of the i th row, and may be represented by Equation 1 above.

Referring to FIG. 2B, the j th column code is composed of message blocks of the j th column and a parity block of the j th column, and may be represented by Equation 9 for 1 ≦ j ≦ k _c ^B.

In the case of j = k _c ^B , it may be expressed as Equation 10.

In this case, the message length of the row code may be expressed as in Equation (11).

In addition, the code length of the line code can be expressed by Equation 12.

Similarly, the message length of the column code can be expressed as in Equation 13.

Similarly, the code length of the column code can be expressed as in Equation 6 above.

In this case, the code rate of the serially concatenated BCH code may be expressed as shown in Equation 7.

개의 비트를 포함하며, 모든 메시지 블록과 메시지-패리티 블록의 크기는 서로 같다.In the embodiment of the serially concatenated BCH code, each message block and a message-parity block are

Bits, and all message blocks and message-parity blocks have the same size.

For an embodiment in which the interleaving is different so that different columns have message blocks of different sizes and only message blocks of the same size within one column, the row code is as shown in Equation 1, and the column code is similar to Equation 8. It can be represented as

3A is a functional block diagram illustrating a functional block of a parallel concatenated BCH code circuit for the flash memory device of the present invention.

As shown in FIG. 3A, the parallel concatenated BCH code circuit receives a part or all of data m input to a flash memory device to perform BCH encoding to output a first output BCH code or a parity bit thereof. A second output BCH code or its parity by BCH encoding a stage code unit, an interleaving unit that receives some or all of the data input to the flash memory device, and interleaves and outputs the BCH code or data that is an output of the interleaving unit And a second stage coder for outputting the bits. Here, the first stage encoder is a row code encoder, the interleaving unit is a block-wise interleaver, and the second stage encoder is a column code encoder.

로 바뀌어 열 부호기(Column Code Encoder)에 인가된다. Referring to FIG. 3A, the data m input for storing in the flash memory device is m _r ⁽¹⁾ ,. , Divided into a row code encoder or a block-wise interleaver, m _c ⁽¹⁾ ,. ,

Is applied to the Column Code Encoder.

The row encoder and the column encoder are systematic encoders, and a message block and a parity block may be simultaneously output from the row encoder or the column encoder. The row encoder and column encoder output at least a parity block of the corresponding code. The message block of the row encoder, the message block of the column encoder, or the message block of the input data may be output as a message block of the code circuit output. The codeword to be stored in the flash memory device is generated by combining the row coder and the column coder, or the line coder and the column coder and the output from the data input terminal.

In FIG. 3A, a row encoder outputs a message block and a parity block at the same time, and a column encoder outputs a parity block to generate a codeword to be stored. In FIG. 3A, although the row encoder and the column encoder are configured in parallel, the row encoder and the column encoder may be configured in series regardless of the order of the two encoders, but may be configured in series by placing an interleaver between the two encoders.

3B is a functional block diagram illustrating a functional block of a serially concatenated BCH code circuit for the flash memory device of the present invention.

As illustrated in FIG. 3B, the serially connected BCH code circuit receives a part or all of data input to a flash memory device to perform BCH encoding to output a first output BCH code or a parity bit thereof. And an interleaving unit for interleaving and outputting the first output BCH code or data protected by the first output BCH code, and a second output BCH code or its parity bit by BCH encoding the BCH code or data which is an output of the interleaving unit. It includes a two-stage coder. Here, the first stage encoder is a row code encoder, the interleaving unit is a block-wise interleaver, and the second stage encoder is a column code encoder.

로 나뉘어져 행 부호기에 인가된다. 행 부호는 블록 단위 인터리버에 인가되어 m_c ⁽¹⁾, … ,

로 바뀌어 열 부호기에 인가된다. 행 부호기와 열 부호기는 체계적 부호기(systematic encoder)로, 각 부호기에서 메시지 블록과 패리티 블록이 동시에 출력될 수 있다. 행 부호기와 열 부호기는 적어도 해당 부호의 패리티 블록을 출력한다. 행 부호기의 메시지 블록, 열 부호기의 메시지 블록, 또는 입력된 데이터의 메시지 블록은 부호 회로 출력의 메시지 블록으로 출력될 수 있다. 행 부호기와 열 부호기, 또는 행 부호기와 열 부호기 그리고 데이터 입력단에서 나오는 출력을 조합하여 플래쉬 메모리 장치에 저장될 코드워드를 생성한다. Referring to FIG. 3B, data input for storing in the flash memory device is m _r ⁽¹⁾ ,. ,

Divided into and applied to the row encoder. The row code is applied to the block unit interleaver so that m _c ⁽¹⁾ ,... ,

Is applied to the column encoder. The row encoder and the column encoder are systematic encoders, and a message block and a parity block may be simultaneously output from each encoder. The row encoder and column encoder output at least a parity block of the corresponding code. The message block of the row encoder, the message block of the column encoder, or the message block of the input data may be output as a message block of the code circuit output. The codeword to be stored in the flash memory device is generated by combining the row coder and the column coder, or the line coder and the column coder and the output from the data input terminal.

In FIG. 3B, a message block and a parity block corresponding to each code are simultaneously output from each of the row encoder and the column encoder to generate a codeword to be stored. In FIG. 3B, the row encoder and the column encoder are configured in series, but the two encoders are configured in parallel, but the column encoder encodes the input data and receives the parity block through the column encoder and the interleaver. It may have a structure for generating a word.

4 is a functional block diagram illustrating a functional block of a concatenated BCH decoding circuit for a flash memory device according to an embodiment of the present invention.

As shown in FIG. 4, the concatenated BCH decoding circuit receives a portion of the concatenated BCH code to perform BCH decoding to output a first output BCH code or first output data protected by the first stage decoder; A deinterleaving unit for de-interleaving and outputting one output BCH code or the first output data into two or more blocks, and a second output BCH code for BCH decoding of the output of the deinterleaving unit And a second stage decoding unit for outputting the second output data protected by the interleaving unit, and an interleaving unit for dividing the second output BCH code or the second output data into two or more blocks and outputting the interleaving unit to the first stage decoding unit.

Here, the first stage decoder is a plurality of column code decoders, the deinterleaving unit is a block-wise de-interleaver, and the second stage decoder is a plurality of column code decoders. The interleaving unit is a block-wise interleaver.

The concatenated BCH decoding circuit repeats column decoding and row decoding in an iterative decoding manner. The repetition end is declared by the maximum number of repetitions or the repetition end condition. The repetition termination condition may be a condition in which during one repetition, all of codes that failed to decode until the previous repetition of column codes and row codes continue to fail decoding. This condition means that the error is no longer corrected even after repeated decoding.

Referring to FIG. 4, n-bit stored data read from a memory cell of a flash memory device is divided into k _c ^B column codes, applied to a column decoder, decoded by a BCH decoder, and output as k _c ^B column messages. k _c ^B-column messages back out through the deinterleaver on a block-by-block basis, in the case of a parallel concatenated BCH code k _r to the ^B row message, serial concatenation for BCH code output by k _r ^B of line code comprising a line message do. If the column decoder successfully decodes all k _c ^B column codes, the row message or row message which is part of the row code is immediately output as data. Otherwise, the k _r ^B of line message or line code is output to the rear is applied to the row decoder decodes a BCH decoder, k _r ^B rows code including a ^B _r k rows, messages or message line if it is not. When the repetition end is declared or the row decoder successfully decodes all k _r ^B row codes, the row message or row message included in the row code is immediately output as data. Otherwise, it is applied to the interleaver in block units to output k _c ^B column messages. The k _c ^B column messages are applied back to the column decoder to proceed with repeated decoding.

5 is a functional block diagram illustrating a functional block of a concatenated BCH decoding circuit for a flash memory device according to another exemplary embodiment of the present invention, which proposes a structure for further providing a power saving effect.

The concatenated BCH decoding circuit of Fig. 5 is a first stage decoder which receives a portion of the concatenated BCH code and performs BCH decoding to output a first output BCH code or first output data protected by it, and a first output BCH code or A deinterleaving unit for dividing the first output data into two or more blocks to de-interleaving and outputting the second output BCH code or a second output protected by the BCH decoding of the output of the deinterleaving unit; A second stage decoding unit for outputting data, an interleaving unit for dividing the second output BCH code or the second output data into two or more blocks, and outputting the interleaving unit to the first stage decoding unit, and the first and second stage decoding units Monitor the operation status to identify the decoding success block, and power on the decoding success block until the new concatenated BCH code is input. It includes a decoder power control to temporarily shut off.

In the multi-layer decoding method based on hard decision information in the concatenated BCH code according to the present invention, the error of one page is fixed while repeating the decoding of the row code and the column code, or the number of errors to be corrected even if the repeated decoding is performed. If not, the decoding ends. In this iterative decoding process, in the case of the component code that has been successfully decoded in the previous step, it is not necessary to use the decoder again until the decoding is completed for the codeword of the entire page.

Therefore, if the power of the decoder which has successfully decoded in the previous step is turned off until the sign of the next page comes, it can play a big role in reducing the power required in the decoding process. The number of average constituent codes that are successfully decoded for each repetition code and the probability of occurrence of an event that should proceed to the corresponding repetition number are shown in Table 1 below.

Table 1

Accordingly, the present invention proposes a decoder power control which temporarily cuts off the power of the decoder which has successfully decoded in the previous step until the code of the next page is received.

The decoder power control unit receives decoding failure information from the first and second stage decoders, and determines a decoding failure block or a decoding success block based on the decoding failure information. That is, the column / row decoder that successfully decodes a plurality of column / row decoders is identified from the code failure information provided by the first and second stage decoders. Then, the power supply to the column / row decoder that successfully decodes the plurality of column / row decoders is temporarily cut off.

Then, the decoder that has successfully decoded in the previous step is excluded from the iterative decoding operation, thereby reducing the average number of decoders used for the multilayer decoding operation, thereby reducing the total power consumption of the concatenated BCH decoding circuit.

However, when the repetitive decoding operation is terminated and a new code is input, the decoder power control is reset in response to supplying power to all the row / column decoders again, thereby performing the repetitive decoding operation on the new concatenated BCH code. Let it start over again.

6 is a diagram illustrating a concatenated BCH multi-layer decoding method for a flash memory device of the present invention.

In the present invention, a concatenated code system that adaptively reduces complexity and decoding delay time by using concatenated BCH codes on a block basis is designed. The concatenated code system consists of at least three levels.

The first level is an error correction step in the component code of the concatenated BCH code in blocks. Since the component code is part of a concatenated BCH code in block units, decoding only the component code can correct an error with a relatively low complexity and a short delay time. Since the code has a relatively long code length, a large number of errors can be corrected even at a high code rate. The configuration code may be part of a page and may be a column code or a row code. In a file system storing data in a flash memory device, the configuration code may be designed to fit the data access unit size of the file system in order to efficiently execute data access of the flash memory device. For example, a file system that performs data access in units of 512 bytes may be designed to have a message length of 512 bytes, that is, 4096 bits, so that data access can be efficiently performed. The probability that the component code fails to correct is equal to Equation 14 when the code length is n _c , the number of correctable bits t _c , and the initial error probability is P _e .

The second level is a step of correcting an error that cannot be corrected at the first level by decoding the entire concatenated BCH code when a large number of errors occur and the component code fails to correct the error. Decoding of contiguous BCH codes has been described with reference to FIG. 4. Since the concatenated BCH code is composed of block units, decoding fails due to an error block. In the low error rate region in which a flash memory core operates, decoding fails mainly due to a few error blocks. Decoding failure probability due to such a small number of error blocks can be calculated by the summer as shown in equation (15). Equation 15 shows, as an example, the probability of decoding failure by one error block in a parallel concatenated BCH code in which all message blocks are the same size.

는 조건 S_{1 ,1}가 만족될 때에는 1이고 그 외에는 0인 논리값이다. 이때 상기 조건 S_{1 , 1}는 t_r<n₁ ^e + n₂ ^e, 그리고 t_r<n₁ ^e + n₃ ^e를 나타낸다. 즉, 하나의 오류 블록과 하나의 행 부호의 패리티 블록에 발생한 비트 오류의 개수가, 그 블록들이 속하는 행 부호가 고칠 수 없을 정도로 많고, 동시에 하나의 오류 블록과 하나의 열 부호의 패리티 블록에 발생한 비트 오류의 개수가, 그 블록들이 속하는 열 부호가 고칠 수 없을 정도로 많은 조건을 나타낸다. 수학식 16는 예로서 모든 메시지 블록이 같은 크기인 병렬 연접 BCH 부호에서 하나의 행에 있는 두 개의 오류 블록에 의한 복호 실패 확률을 나타낸다.In Equation 15, P _{i , j} denotes an error probability due to i decoded failed row codes and j decoded failed column codes, and P _e denotes an average raw bit error rate. In addition, n _B is the message block size, m _r is the parity block size of one row code, m _c is the parity block size of one column code, n ^e (= n ₁ ^e + n ₂ ^e + n ₃ ^e ) N ₁ ^e is the number of bit errors in the message block, n ₂ ^e is the number of bit errors in the parity block of one row code, n ₃ ^e is the parity block of one column code. It means the number of bit error occurred.

Is a logical value that is ₁ when the condition S _{1 , 1} is satisfied and 0 otherwise. In this case, the conditions S _{1 , 1} indicate t _r <n ₁ ^e + n ₂ ^e , and t _r <n ₁ ^e + n ₃ ^e . That is, the number of bit errors occurring in the parity block of one error block and one row code is so large that the row code to which the blocks belong cannot be corrected, and simultaneously occurs in the parity block of one error block and one column code. The number of bit errors indicates so many conditions that the column code to which the blocks belong cannot be corrected. Equation 16 shows a decoding failure probability by two error blocks in one row in a parallel concatenated BCH code in which all message blocks are the same size.

는 조건 S_{2 ,1}가 만족될 때에는 1이고 그 외에는 0인 논리값이다. 이때 상기 조건 S_{2 , 1}는 1) t_r < n₁ ^e + n₂ ^e+ n₃ ^e, 2) t_c < n₁ ^e + n₄ ^e, 그리고 3) t_c < n₂ ^e + n₅ ^e를 나타낸다. 이와 같은 방식으로 하계를 구하면 도 6과 같이 연접 BCH 부호의 컴퓨터 시뮬레이션에 의한 성능 측정 결과가 하계에 의해 제한되는 것을 확인할 수 있다.In Equation 16, P _{i , j} denotes an error probability due to i decoded failed row codes and j decoded failed column codes, and P _e denotes an average raw bit error rate. In addition, n _B is the message block size, m _r is the parity block size of one row code, m _c is the parity block size of one column code, n ^e (= n ₁ ^e + n ₂ ^e + n ₃ ^e + n ₄ ^e + n ₅ ^e ) is the number of all bit errors encountered, n ₁ ^e is the number of bit errors encountered in the first message block, n ₂ ^e is the number of bit errors encountered in the second message block, n ₃ ^e Is the number of bit errors in the parity block of one row code, n ₄ ^e is the number of bit errors in the parity block of the first column code, and n ₅ ^e is the number of bit errors in the parity block of the second column code. Means.

Is a logical value that is ₁ when the condition S _{2 , 1} is satisfied and 0 otherwise. The condition S _{2 , 1} is 1) t _r <n ₁ ^e + n ₂ ^e + n ₃ ^e , 2) t _c <n ₁ ^e + n ₄ ^e , and 3) t _c <n ₂ ^e + n ₅ ^e is represented. When summer is obtained in this manner, it can be seen that the results of performance measurement by computer simulation of contiguous BCH codes are limited by summer as shown in FIG. 6.

Limiting the performance of contiguous BCH codes means that the decoding failure is caused by the error block indicated by the summer. For example, referring to FIG. 6, if the concatenated BCH code is decoded when the initial bit error rate is about 2.75 × 10 ^(-3) or less, decoding failure by most one error block occurs.

When decoding failure occurs in the concatenated BCH code used in the present invention, the position of the error block is determined by the component code that failed to decode. Therefore, when a decoding failure due to an error block occurs, additional operations may be performed only on the corresponding error block.

The third level is to correct only more errors than the second level by performing additional decoding with relatively low complexity by obtaining only additional information corresponding to the error block when the decoding failure of the contiguous BCH code occurs for a few error blocks. to be. Referring to FIG. 9, if the repetition end is declared in the hard decision iterative decoding of a concatenated BCH code, the additional decoding is performed, and whether the decoding of each component code is failed in both the row decoder and the column decoder for the additional decoding. And determine the position of the fractional error block. The additional information is information about bits corresponding to the located small number of error blocks. For example, the flash memory core may read a cell in which the bits are stored and a neighboring cell thereof, or may store a cell in which the bits are stored. The read reference threshold voltage value, which determines the bit value for the threshold voltage of, may be obtained by replacing the previous read reference threshold voltage value with a method of determining the bit value. The additional decoding may be a decoding method using the additional information. For example, a reliability-based decoding method such as chase decoding may be used.

Hereinafter, the performance difference between the error correction circuit using the concatenated code of the present invention and the conventional error correction circuits will be described by way of example.

Referring to FIG. 8, Sim. Is a (70528, 65536) parallel concatenated BCH consisting of 16 row codes ((4226, 4096, 10) BCH codes) and 16 column codes ((4278, 4096, 14) BCH codes). Computer simulation of the performance of the code.

I _max means the maximum number of attempts in the reliability-based decoding method, I _max = N means performance when the reliability-based decoding of the maximum number of N attempts is performed at the third level. In the example of FIG. 8, the reliability-based decoding method uses a method of inverting a value by selecting only a predetermined number of bits. Reliability-based decoding, in which a maximum number of attempts can be performed 512 times for one block error, shows that most error blocks can be corrected for the target page-error rate. Table 1 shows that the average number of attempts is small when the maximum number of attempts is 16, 32, 64, 128, and 512 times with respect to FIG. 8. This means that the third level of decoding is achieved with a relatively low complexity.

Referring to FIG. 8, it can be seen that error correction capability of the third level indicated by Sim. Is superior to the symbol indicated by Short BCH. The Short BCH is a code (16 (4278, 4096, 24) BCH codes) obtained by applying a BCH code for correcting 24 bits per 512 bytes for 8 KB. The two codes denoted by Short BCH and Sim. Have the same code rate (0.929), have the same code length, and have the same number of parity bits.

Referring to FIG. 8, it can be seen that the error correction capability of the third level indicated by Sim. Is not significantly different from the sign indicated by Long BCH. The Long BCH is a BCH code (one (70534, 65536, 295) BCH code) that corrects 295 bits per 8KB. The two codes marked Long BCH and Sim. Have the same code rate (0.929), have almost the same code length, and have almost the same number of parity bits. The code marked Long BCH has the maximum performance that can be achieved by a simple BCH code, but is an error correction code that is difficult to implement or cannot be used in a flash memory device due to excessive complexity and delay time.

9 is a functional block diagram illustrating a concatenated BCH multi-layer decoding circuit capable of further decoding the flash memory device of the present invention.

As shown in FIG. 9, the concatenated BCH multi-layer decoding circuit includes a first stage decoder that receives a portion of the concatenated BCH code and performs BCH decoding to output a first output BCH code or first output data protected by the concatenated BCH code; A deinterleaving unit for de-interleaving the first output BCH code or the first output data into two or more blocks, and outputting the deinterleaving unit, and performing a BCH decoding of the output of the deinterleaving unit; A second stage decoder for outputting the second output data protected by the interleaving unit, an interleaving unit for dividing the second output BCH code or the second output data into two or more blocks, and outputting the interleaved output to the first stage decoder; And decoding failure by receiving decoding failure information from the second stage decoding unit and receiving the second output BCH code or the second output data protected by the second stage decoding unit. It includes an additional decoder that performs additional decoding on the lock.

Here, the first stage decoder is a column code decoder, the deinterleaving part is a block-wise de-interleaver, the second stage decoder is a row code decoder, and the interleaving part is a block It is a block-wise interleaver.

When the decoding failure of the contiguous BCH code occurs for a few error blocks, the additional decoding unit obtains additional information corresponding to the error block and performs additional decoding to correct the error. In this case, the additional information includes information about bits corresponding to a small number of error blocks in which a position is determined.

The additional decoding unit receives the decoding failure of each component code from both the first and second stage coders for additional decoding to determine the position of the few error blocks. The construction code is part or all of the page, which is a read and write unit, or a column or row code.

In addition, although not shown, the concatenated BCH multi-layer decoding circuit diagram of FIG. 9 may further include a decoder power control as shown in FIG. 5 to further provide a power saving effect.

An error correction circuit of a flash memory device according to the present invention includes an external coder for separating input data into two or more data and then performing BCH encoding to output the same number of row BCH codes as the separated data, and a row BCH code. Or an interleaving unit for dividing the data protected by the data into two or more blocks, interleaving the blocks and outputting the same number of blocks, and an internal encoder for outputting a column BCH code by BCH encoding the interleaved blocks in the interleaving unit; A first stage decoder for receiving a portion of the stored data provided from the flash memory core to perform BCH decoding to output a first output BCH code or first output data protected by the first output BCH code; 1 A deinterleaving unit for dividing the output data into two or more blocks for deinterleaving and outputting the deinterleaving unit. BCH decoding the output of the ice block to output the second output BCH code or the second output data protected by the second stage decoder and the second output BCH code or the second output data divided into two or more blocks And an interleaving unit for outputting to the first stage decoding unit.

The flash memory device of the present invention may be basically applied to a NAND flash memory device, but may also be applied to other types of memory devices such as NOR flash memory.

The concatenated BCH code, decoding and multi-layer decoding circuit and method of the present invention configured as described above, the error correction circuit and the flash memory device of the flash memory device using the same, the error degree through the code, decoding and multi-layer decoding for the flash memory device By adjusting the delay time according to the above, the technical problem of the present invention can be solved.

It will be apparent to those skilled in the art that various modifications and changes can be made in the present invention without departing from the spirit or scope of the present invention as defined by the appended claims. It will be appreciated that such modifications and variations are intended to fall within the scope of the following claims.

Claims (11)

A first stage decoder receiving a concatenated BCH code to perform BCH decoding to output a first output BCH code or first output data protected by the first BCH code;
A deinterleaving unit for de-interleaving and outputting the first output BCH code or the first output data into two or more blocks;
A second stage decoder for BCH decoding the output of the deinterleaving unit to output a second output BCH code or second output data protected by the second output BCH code;
An interleaving unit dividing the second output BCH code or the second output data into two or more blocks and interleaving the interleaving unit to output the first output BCH code to the first stage decoder; And
A decoder power control unit configured to monitor operation states of the first and second stage decoders to identify a decoding success block, and temporarily block power supply until a new concatenated BCH code is input to the decoding success block. Decoding Circuit.
The circuit of claim 1, wherein the concatenated BCH decoding circuit is:
10. A concatenated BCH decoding circuit for repeating column decoding and row decoding in an iterative decoding manner, and ending the iteration by a maximum number of iterations or an iteration termination condition.
The method of claim 1,
The first stage decoder is a plurality of column code decoder (Column Code Decoder),
The second stage coder is a plurality of row code decoders,
The deinterleaving unit is a block-wise de-interleaver.
And the interleaving unit is a block-wise interleaver.
The method of claim 3, wherein the decoder power control unit
Decode the successful decoder using the decoding failure information transmitted from each of the plurality of column coders and the plurality of row code decoders, and supply power to the decoder that successfully decodes the new decoder. A concatenated BCH decoding circuit, which temporarily blocks until a concatenated BCH code is received.
The circuit of claim 1, wherein the concatenated BCH decoding circuit is:
A concatenated BCH that combines the outputs of the first and second stage decoders to generate codewords to be stored in the flash memory core upon successful column and row decoding in the first and second stage decoders. Decoding Circuit.
The method of claim 1,
An additional decoder that receives decoding failure information from the first and second stage decoders and receives the second output BCH code or second output data protected by the first and second stage decoders to perform additional decoding on a decoding failure block; Concatenated BCH decoding circuit.
7. The apparatus of claim 6, wherein the additional decoder is:
A concatenated BCH decoding circuit for correcting an error by performing additional decoding by obtaining only additional information corresponding to the error block when a decoding failure of a contiguous BCH code occurs for a few error blocks.
8. The method of claim 7,
The additional information includes information on bits corresponding to a small number of error blocks in which the location is determined.
7. The apparatus of claim 6, wherein the additional decoder is:
A concatenated BCH decoding circuit configured to determine the positions of the few error blocks by receiving whether or not the decoding codes of respective components are decoded by both the first and second stage decoding units for the additional decoding.
The method of claim 9,
Wherein the configuration code is part or all of a page in read and write units or a column or row code.
An outer coder for separating input data into two or more data and then performing BCH encoding to output the same number of row BCH codes as the separated data;
An interleaving unit for dividing the row BCH code or data protected by it into two or more blocks, interleaving the blocks, and outputting the same number of blocks;
An internal coder for BCH encoding the interleaved blocks in the interleaving unit to output a column BCH code;
A first stage decoder configured to receive a portion of stored data provided from a flash memory core to perform BCH decoding to output a first output BCH code or first output data protected by the first output BCH code;
A deinterleaving unit configured to deinterleave and output the first output BCH code or the first output data into two or more blocks;
A second stage decoding unit for BCH decoding the output of the deinterleaving unit to output a second output BCH code or second output data protected by the second output BCH code;
An interleaving unit dividing the second output BCH code or the second output data into two or more blocks and interleaving the interleaving unit to output the first output BCH code to the first stage decoder; And
And a decoder power controller configured to monitor operation states of the first and second stage decoders to identify a decoding success block, and temporarily cut off power supply until a new concatenated BCH code is input to the decoding success block. Error correction circuit in the device.

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