KR20140002183A - Semiconductor memory apparatus - Google Patents

Semiconductor memory apparatus Download PDF

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Publication number
KR20140002183A
KR20140002183A KR1020120070007A KR20120070007A KR20140002183A KR 20140002183 A KR20140002183 A KR 20140002183A KR 1020120070007 A KR1020120070007 A KR 1020120070007A KR 20120070007 A KR20120070007 A KR 20120070007A KR 20140002183 A KR20140002183 A KR 20140002183A
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KR
South Korea
Prior art keywords
bit line
cap
reference bit
sense amplifier
cap control
Prior art date
Application number
KR1020120070007A
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Korean (ko)
Inventor
장웅주
임규남
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120070007A priority Critical patent/KR20140002183A/en
Publication of KR20140002183A publication Critical patent/KR20140002183A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

A cap control signal generator configured to generate a plurality of cap control signals in response to the plurality of control signals and the sense amplifier enable signal, and a reference bit line for varying a voltage level and capacitance of a reference bit line in response to the plurality of cap control signals A provision unit, a mat connected to the bit line, and a sense amplifier for sensing and amplifying the voltage level of the reference bit line and the bit line in response to the sense amplifier enable signal.

Description

[0001] Semiconductor Memory Apparatus [0002]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory device.

A general semiconductor memory device is configured to receive data from an external source, store the data, and output the stored data to the external device.

1, the first and second dummy mats 10-1 and 10-2, the first to Nth sense amplifiers 20-1 to 20 -N, and the first to the second dummy mats are illustrated in FIG. 1. N-1 mats 30-1 to 30-N-1.

The first to N-1 mats 30-1 to 30 -N-1 store data, and may include a plurality of memory cells including a transistor (not shown) and a capacitor (not shown). The first to N-th mats 30-1 to 30-N-1 configured as described above are configured to store data.

The first and second dummy mats 10-1 and 10-2 are configured of transistors and capacitors in the same manner as the first to N-1 mats 30-1 to 30 -N-1. It may include a plurality of cells. In this case, the first and second dummy mats 10-1 and 10-2 are configured in the same manner as the first to N-1 mats 30-1 to 30-N-1, but do not store data. Do not.

Each of the first to Nth sense amplifiers 20-1 to 20 -N senses and amplifies signals received from mats connected at both ends. For example, the first sense amplifier 20-1 is connected to the first dummy mat 10-1 and the first mat 30-1, and the first dummy mat 10-1 is connected. The signal output by the first mat 30-1 is detected and amplified based on the output signal. The second sense amplifier 20-1 senses and amplifies signals output from the first mat 30-1 and the second mat (not shown).

The general semiconductor memory device configured as described above is a semiconductor memory device having an open bit line structure, and dummy mats that do not store data are disposed at both ends, and the dummy mats provide a reference signal to a sense amplifier connected to each other. Normally detects and amplifies the signal input from the connected mat.

Placing dummy mats that do not store data at both ends of the semiconductor memory device lowers the area efficiency of the semiconductor memory device.

The present invention provides a semiconductor memory device capable of increasing the area sensing efficiency of a semiconductor memory device having an open bit line structure while testing and increasing a data sensing margin.

In an embodiment, a semiconductor memory device may include a cap control signal generator configured to generate a plurality of cap control signals in response to a plurality of control signals and a sense amplifier enable signal, and a reference bit line in response to the plurality of cap control signals. A reference bit line providing unit for varying a voltage level and capacitance of the circuit board; a mat connected to the bit line; and a sense amplifier configured to sense and amplify voltage levels of the reference bit line and the bit line in response to the sense amplifier enable signal. .

According to another aspect of the present invention, a semiconductor device may include a cap control signal generator that outputs a sense amplifier enable signal as a cap control signal when a control signal is enabled, and corresponds to a voltage change amount of the cap control signal. A reference bit line providing unit for changing a voltage level, and a sense amplifier for detecting and amplifying the voltage difference between the reference bit line and the bit line connected to the mat.

The semiconductor memory device according to another embodiment of the present invention generates a cap control signal that generates a plurality of cap control signals that are enabled by the same number as the number of control signals enabled when the sense amplifier enable signal is enabled. A reference bit line providing unit for changing a voltage level of a reference bit line by the number of enabled signals among the plurality of cap control signals, and a sense amplifier detecting and amplifying a difference between voltage levels of the reference bit line and the bit line. It includes.

The semiconductor memory device according to the present invention can increase the data sensing margin while increasing the area efficiency of the semiconductor memory device having an open bit line structure.

1 is a block diagram of a general semiconductor memory device,
2 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention;
3 is a configuration diagram according to an embodiment of the cap control signal generator of FIG. 2;
4 is a configuration diagram according to another embodiment of the cap control signal generator of FIG. 2;
5 is a configuration diagram of a reference bit line providing unit of FIG. 2;
6 is a timing diagram of a semiconductor memory device according to an embodiment of the present invention.

As illustrated in FIG. 2, a semiconductor memory device according to an exemplary embodiment of the present invention includes a cap control signal generator 100, a reference bit line providing unit 200, a sense amplifier 300, and a mat 400. do.

The cap control signal generator 100 may include the first to third cap control signals Cap_ctrl <0: in response to the first to third control signals CTRL <0: 2> and the sense amplifier enable signal SA_EN. 2>). For example, the cap control signal generator 100 may output the first to third control signals CTRL <0: 2> when the sense amplifier enable signal SA_EN is enabled. It outputs as a cap control signal Cap_ctrl <0: 2>. In more detail, the cap control signal generator 100 has the same number as the number of enabled signals among the first to third control signals CTRL <0: 2>, and the sense amplifier enable signal ( The first to third cap control signals Cap_ctrl <0: 2> are generated at the same timing as SA_EN. That is, the cap control signal generator 100 may enable the first and second control signals CTRL <0: 1> of the first to third control signals CTRL <0: 2>. The first and second cap control signals Cap_ctrl <0: 1> are generated at the same timing as the sense amplifier enable signal SA_EN. In addition, when the sense amplifier enable signal SA_EN is disabled while the first and second control signals CTRL <0: 1> are enabled, the first and second cap control signals at the same timing. Cap_ctrl <0: 1>) is disabled.

As shown in FIG. 3, the cap control signal generator 100 includes first to third NAND gates ND11, ND12, and ND13, and first to third inverters IV11, IV12, and IV13. . The first NAND gate ND11 receives the first control signal CTRL <0> and the sense amplifier enable signal SA_EN. The first inverter IV11 receives the output signal of the first NAND gate ND11 and outputs the first cap control signal Cap_ctrl <0>. The second NAND gate ND12 receives the second control signal CTRL <1> and the sense amplifier enable signal SA_EN. The second inverter IV12 receives the output signal of the second NAND gate ND12 and outputs the second cap control signal Cap_ctrl <1>. The third NAND gate ND13 receives the third control signal CTRL <2> and the sense amplifier enable signal SA_EN. The third inverter IV13 receives the output signal of the third NAND gate ND13 and outputs the third cap control signal CaP_ctrl <2>. As described above, the cap control signal generator 100 performs a logical multiplication on each of the first to third control signals CTRL <0: 2> and the sense amplifier enable signal SA_EN to form the first to third caps. Generate the control signal Cap_ctrl <0: 2>.

As shown in FIG. 4, the cap control signal generator 100-1 according to another embodiment includes a signal combination unit 110-1, and first to third level shifters 120-1 and 130-1. 140-1).

The signal combination unit 110-1 includes fourth to sixth NAND gates ND21, ND22, and ND23, and fourth to sixth inverters IV21, IV22, and IV23. The fourth NAND gate ND21 receives the first control signal CTRL <0> and the sense amplifier enable signal SA_EN. The fifth NAND gate ND22 receives the second control signal CTRL <1> and the sense amplifier enable signal SA_EN. The sixth NAND gate ND23 receives the third control signal CTRL <2> and the sense amplifier enable signal SA_EN. The fourth inverter IV21 receives the output signal of the fourth NAND gate ND21 and outputs a first combined signal com1. The fifth inverter IV22 receives the output signal of the fifth NAND gate ND22 and outputs a second combined signal com2. The sixth inverter IV23 receives the output signal of the sixth NAND gate ND23 and outputs a third combined signal com3. In this case, the fourth inverter IV21 receives the external voltage VDD and the ground voltage VSS as driving voltages. In addition, the fifth and sixth inverters IV22 and IV23 also receive an external voltage VDD and a ground voltage VSS. Therefore, the first to third combination signals com1 to com3 swing to the external voltage VDD and the ground voltage VSS.

The first level shifter 120-1 shifts the voltage level of the first combined signal com1 and outputs the first cap control signal Cap_ctrl <0>. In this case, the first level shifter 120-1 receives the pumping voltage VPP and the ground voltage VSS as driving voltages. Therefore, the first level shifter 120-1 level shifts the first combination signal com1 swinging to an external voltage VDD and a ground voltage VSS level, thereby pumping the voltage VPP and the ground voltage VSS. Output as the first cap control signal Cap_ctrl <0> swinging at

The second level shifter 130-1 shifts the voltage level of the second combined signal com2 and outputs the second cap control signal Cap_ctrl <1>. In this case, the second level shifter 130-1 receives a pumping voltage VPP and a ground voltage VSS as driving voltages. Therefore, the second level shifter 130-1 level shifts the second combination signal com2 swinging to the external voltage VDD and the ground voltage VSS level, thereby pumping voltage VPP and ground voltage VSS. Output as the second cap control signal Cap_ctrl <1> swinging at a level.

The third level shifter 140-1 shifts the voltage level of the third combined signal com3 and outputs the third cap control signal Cap_ctrl <2>. In this case, the third level shifter 140-1 receives the pumping voltage VPP and the ground voltage VSS as driving voltages. Therefore, the third level shifter 140-1 shifts the third combination signal com3 swinging to the external voltage VDD and the ground voltage VSS level to level the pumping voltage VPP and the ground voltage VSS. Output as the third cap control signal Cap_ctrl <2> swinging at a level.

The reference bit line providing unit 200 varies the voltage level and the capacitance of the reference bit line BL_ref in response to the first to third cap control signals Cap_ctrl <0: 2>. For example, the reference bit line providing unit 200 corresponds to the voltage change amount of the enabled signals among the first to third cap control signals Cap_ctrl <0: 2>, so as to correspond to the reference bit line BL_ref. To change the voltage level. That is, the reference bit line providing unit 200 may change the voltage level of the enabled signals among the first to third cap control signals Cap_ctrl <0: 2> and the first and third cap control signals Cap_ctrl. The voltage level of the reference bit line BL_ref is changed by the number corresponding to the number of enabled signals in <0: 2>.

As illustrated in FIG. 5, the reference bit line providing unit 200 includes the reference bit line BL_ref and first to third capacitors C11, C12, and C13. The first capacitor C11 is connected to the reference bit line BL_ref at one end thereof and receives the first cap control signal Cap_ctrl <0> at the other end thereof. One end of the second capacitor C12 is connected to the reference bit line BL_ref and the other end receives the second cap control signal Cap_ctrl <1>. One end of the third capacitor C13 is connected to the reference bit line BL_ref and the other end receives the third cap control signal Cap_ctrl <2>.

The sense amplifier 300 senses and amplifies the voltage levels of the reference bit line BL_ref and the bit line BL. For example, the sense amplifier 300 senses and amplifies a voltage level difference between the reference voltage BL_ref and the bit line BL.

The mat 400 has the same configuration as that of the mats 30-1 to 30 -N-1 storing data shown in FIG. 1, and is configured to store data. In addition, the bit line BL is a signal line for transferring data stored in the mat 400 to the sense amplifier 300.

The operation of the semiconductor memory device according to the embodiment of the present invention will now be described.

It is assumed that only the first control signal CTRL <0: 2> of the first to third control signals CTRL <0: 2> is enabled.

The cap control signal generator 100 receives the first to third control signals CTRL <0: 2> and the sense amplifier enable signal SA_EN. In this case, when the first control signal CTRL <0> is enabled, the cap control signal generator 100 is enabled at a timing at which the sense amplifier enable signal SA_EN is enabled and enables the sense amplifier. A first cap control signal Cap_ctrl <0> is generated at a timing at which the signal SA_EN is disabled. Meanwhile, since the second and third control signals CTRL <1: 2> are disabled, the cap control signal generator 100 may disable the second and third cap control signals Cap_ctrl <1: 2. >)

As illustrated in FIG. 6, when the first cap control signal Cap_ctrl <0> rises to the external voltage VDD level, the reference voltage provider 200 adjusts the voltage level of the reference bit line BL_ref. Raise. That is, the first capacitor C11 illustrated in FIG. 6 increases the voltage level of the reference bit line BL_ref by the voltage corresponding to the voltage level rising width of the first cap control signal Cap_ctrl <0>.

If the data stored in the mat 400 is low data, the voltage level of the bit line BL is lowered.

The sense amplifier 300 senses and amplifies a voltage level difference between the reference bit line BL_ref having a higher voltage level and the bit line BL having a lower voltage level. Since the sense amplifier 300 senses and amplifies a voltage level difference between the reference bit line BL_ref having a higher voltage level and the bit line BL having a lower voltage level, as shown in FIG. 1, the dummy mat 10-1. Is sensed than the first sense amplifier 20-1 which senses and amplifies the voltage level difference between the bit line at which the voltage level provided from the fixed line is fixed and the bit line at which the voltage level provided from the first mat 30-1 is lowered. The margin is large. In addition, since the voltage level difference between the reference bit line BL_ref and the bit line BL provided by the mat is increased, the possibility of sensing malfunction of the sense amplifier 300 is reduced.

The semiconductor memory device according to an exemplary embodiment of the present invention may include a general semiconductor memory device shown in FIG. In comparison, the area efficiency can be increased. This is because only the capacitor is used instead of the dummy mat to provide the reference bit line to the sense amplifier.

In addition, the semiconductor memory device according to the embodiment of the present invention can increase the voltage level of the reference bit line to enable timing of the sense amplifier enable signal, thereby increasing the sensing margin of the sense amplifier.

Meanwhile, since the number of cap control signals enabled at the enable timing of the sense amplifier enable signal can be controlled by using the plurality of control signals, it is possible to control up to the changed voltage level of the reference bit line. Moreover, the level shifter can be used to increase the voltage level of the cap control signal by a variable width, thereby further increasing the voltage level change of the reference bit line.

If the high data is stored in the mat 400 and the voltage level of the bit line BL is high, the capacitance of the reference bit line BL_ref is smaller than that of the mat 400, so that the sense amplifier 400 May perform a normal data sensing operation.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (13)

A cap control signal generator configured to generate a plurality of cap control signals in response to the plurality of control signals and the sense amplifier enable signal;
A reference bit line providing unit configured to vary a voltage level and capacitance of a reference bit line in response to the plurality of cap control signals;
A mat connected to the bit line; And
And a sense amplifier configured to sense and amplify the voltage level of the reference bit line and the bit line in response to the sense amplifier enable signal. The method of claim 1,
The cap control signal generator
And when the sense amplifier enable signal is enabled, output the plurality of control signals as the plurality of cap control signals. 3. The method of claim 2,
The cap control signal generator
And generating the plurality of cap control signals having a number equal to the number of enabled signals among the plurality of control signals and being enabled at the same timing as the sense amplifier enable signal. The method of claim 3, wherein
The cap control signal generator
And generating the plurality of cap control signals by logically multiplying each of the plurality of control signals by the sense amplifier enable signal. The method of claim 1,
The reference bit line providing unit
The reference bit line, and
Including the plurality of capacitors,
And each of the plurality of capacitors is connected to the reference bit line at one end thereof and receives a corresponding one of the plurality of cap control signals at the other end thereof. A cap control signal generator for outputting a sense amplifier enable signal as a cap control signal when the control signal is enabled;
A reference bit line providing unit for changing a voltage level of a reference bit line as much as a voltage change amount of the cap control signal;
And a sense amplifier configured to sense and amplify a voltage difference between the reference bit line and the bit line connected to the mat. The method according to claim 6,
The cap control signal generator
When the control signal is enabled, the cap control signal is enabled at a timing when the sense amplifier enable signal is enabled, and is disabled at a timing when the sense amplifier enable signal is disabled. Memory device. The method of claim 7, wherein
The cap control signal generator
And a level shifter for shifting the voltage level of the cap control signal to a pumping voltage level. The method of claim 8,
The reference bit line providing unit
The reference bit line, and
And a capacitor connected to the reference bit line at one end and receiving the cap control signal at the other end. A cap control signal generator configured to generate a plurality of cap control signals enabled by the same number as the number of control signals enabled when the sense amplifier enable signal is enabled;
A reference bit line providing unit for changing a voltage level of a reference bit line by the number of enabled signals among the plurality of cap control signals; And
And a sense amplifier configured to sense and amplify a difference in voltage levels between the reference bit line and the bit line. 11. The method of claim 10,
The cap control signal generator
Generating a plurality of cap control signals having a number equal to the number of enabled signals among the plurality of control signals,
The enabled signals of the plurality of cap control signals are enabled at a timing at which the sense amplifier enable signal is enabled, and are disabled at a timing at which the sense amplifier enable signal is disabled. 11. The method of claim 10,
The reference bit line providing unit
And changing a voltage level of the reference bit line by a voltage change corresponding to an amount of voltage change of an enable signal among the plurality of cap control signals and a number of enabled signals among the plurality of cap control signals. 11. The method of claim 10,
The reference bit line providing unit
The reference bit line, and
And a plurality of capacitors to which the plurality of cap control signals are input at one end,
And the other ends of the reference bit line and the plurality of capacitors are connected to each other.
KR1020120070007A 2012-06-28 2012-06-28 Semiconductor memory apparatus KR20140002183A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627020B1 (en) 2015-12-24 2017-04-18 SK Hynix Inc. Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627020B1 (en) 2015-12-24 2017-04-18 SK Hynix Inc. Semiconductor device

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