KR101218604B1 - Semiconductor Memory Apparatus - Google Patents

Abstract

The present invention provides a semiconductor memory device including a cell region including a plurality of cells having a transistor whose threshold voltage varies according to a bulk voltage supplied to a bulk terminal, and the cell region is divided into a plurality of memory banks. A plurality of bulk voltage generators varying a level of the bulk voltage according to a signal to independently supply the bulk voltage to each of the plurality of memory banks, and a bulk voltage corresponding to an activated memory bank among the plurality of memory banks And a controller for outputting the control signal so that the level of the bulk voltage of the generator is varied.

Bank, VBB, active

Description

[0001] Semiconductor Memory Apparatus [0002]

1 is a block diagram of a semiconductor memory device according to the prior art;

2 is a block diagram of a semiconductor memory device according to the present invention;

3 is a block diagram of a first bulk voltage generator of FIG. 2;

4 is a circuit diagram of the controller of FIG. 2;

5 is a circuit diagram of a delay unit of FIG. 4;

6 is a waveform diagram illustrating an operation of the active determination unit of FIG. 4;

7 is a waveform diagram illustrating an operation of a control signal generator of FIG. 4;

8 is a waveform diagram illustrating an operation of a bulk voltage generation circuit of a semiconductor memory device according to the present invention;

9 is a waveform diagram illustrating an operation of a semiconductor memory device according to the present invention.

Description of the Related Art

110 to 150: first to fifth bulk voltage generators 111: oscillator

112: charge pump 113: level detector

114: voltage level adjusting unit 200: control unit

300: active determination unit 310: active determination logic

400: control signal generation unit 410: control signal generation logic

411: delay unit

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which a bulk voltage is independently generated and controlled for each memory bank.

Since a semiconductor memory device stores one data in one cell, to store more data, more cells must be integrated in one semiconductor memory device. Therefore, in order to integrate more cells into a semiconductor memory device, the size of the cells is made as small as the technology allows.

Therefore, since the size of the signal of the data stored in the cell is very small, it is not possible to directly transfer the data stored in one cell to the outside, it is necessary to detect and amplify the data stored in the cell. Most semiconductor memory devices have a sense amplifier that senses and amplifies data stored in a cell. In fact, the time of sensing amplification of the time of accessing data is relatively large. When the data stored in the cell is applied to the bit line, the sense amplifier develops a small signal difference between the bit line bar (/ bitline) that is precharged to a predetermined voltage level and the bit line. That is, it senses amplification.

On the other hand, in order to reduce the power consumption of the semiconductor memory device, the level of the power supply voltage input from the outside into the semiconductor memory device is gradually decreasing. Therefore, the level of the driving voltage for driving the sensing amplifier is also getting lower. Therefore, using a relatively low level driving voltage, the time for the sense amplifier to detect and amplify the voltage difference between the bit line to which the data signal is applied and the precharged bit line bar is increasing.

Since the level of the externally supplied power supply voltage is decreasing, it is also difficult to transfer data stored in the cell to the bit line. For example, a transistor serving as a switch for transferring data stored in a cell to a bit line or transferring a data signal applied to the bit line to a cell is not easily turned on or turned off. That is, the gate of a transistor that acts as a switch in the cell is connected to a wordline. If the voltage applied to the wordline is not sufficient, the threshold voltage of the transistor of the cell becomes relatively high, and thus it is not turned on within a desired time. I can't.

If the driving voltage level of the word line generated by using the power supply voltage temporarily drops while the read-write-read operation of data is continuously performed, the transistor of the cell is turned on at all. It will not be possible. In this case, no data signal is transmitted to the bit line, and no sense amplification of data is performed.

As shown in FIG. 1, a semiconductor memory device according to the related art includes a plurality of banks BANK0 to BANK3 each having a plurality of cells 11 and cells of the plurality of banks BANK0 to BANK3. And a peripheral area in which circuits for writing data to or reading data written into the cell 11 are arranged. The cell 11 includes one transistor (Tr) and a capacitor (Cap), and the transistor (Tr) includes a bulk terminal for adjusting a threshold voltage, and the bulk voltage at the bulk terminal. (VBB) is supplied. In addition, the circuits of the peripheral region are provided with a myriad of transistors, and the bulk voltage VBB is supplied to the bulk terminals like the transistor Tr of the cell 11. The transistor Tr of the cell 11 is an N-type transistor, and the bulk voltage VBB has a negative potential.

According to the related art, one bulk voltage generator 10 supplies a bulk voltage VBB to the bulk terminals of the plurality of banks BANK0 to BANK3 and the transistors Tr in the peripheral region, and bulk. The level of the voltage VBB is maintained at a constant level regardless of an operating state of the semiconductor memory device, for example, an active period for read or write.

Although not shown, the semiconductor memory device according to the related art may include two bulk voltage generators to supply separate bulk voltages VBB to the plurality of banks BANK0 to BANK3 and the peripheral area, respectively. Even when two bulk voltage generators are provided, the level of the bulk voltage VBB output from the bulk voltage generator that supplies the bulk voltages VBB to the plurality of banks BANK0 to BANK3 is an active period for read or write. Regardless of whether you maintain a constant level.

Therefore, in the semiconductor memory device according to the related art, since the bulk voltage generator outputs a constant bulk voltage VBB regardless of the operation state of the semiconductor memory device, the power supply voltage is low or continuous data read-write-read When the driving voltage level of the word line temporarily drops due to a write-read operation, the transistor of the cell cannot be switched smoothly due to a relatively high threshold voltage due to the drop of the word line driving voltage level. There is a problem that the amplification performance is greatly reduced.

It is an object of the present invention to provide a semiconductor memory device capable of achieving stable data sensing amplification even under low power supply voltage conditions.

A semiconductor memory device according to the present invention includes a cell region including a plurality of cells having a transistor whose threshold voltage is changed according to a bulk voltage supplied to a bulk terminal, and the cell region is divided into a plurality of memory banks. A memory device, comprising: a plurality of bulk voltage generators varying a level of the bulk voltage according to a control signal to supply the bulk voltage independently to each of the plurality of memory banks; And a controller for outputting the control signal such that the level of the bulk voltage of the bulk voltage generator corresponding to the activated memory bank of the plurality of memory banks is varied.

Hereinafter, exemplary embodiments of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

As shown in FIG. 2, a semiconductor memory device according to the present invention includes a cell region including a plurality of cells including a transistor Tr, which is used for data transfer and whose threshold voltage is varied according to a bulk voltage supplied to a bulk terminal. And the cell area is divided into first to fourth memory banks BANK0 to BANK3. The number of memory banks may vary depending on the memory capacity of the semiconductor memory device. FIG. 2 illustrates an example of four memory banks.

The semiconductor memory device may independently change the level of the bulk voltages VBB_BANK0 to VBB_BANK3 according to the first to fourth control signals VBB_UP0 to VBB_UP3 to independently of each of the first to fourth memory banks BANK0 to BANK3. The level of the bulk voltage of the bulk voltage generator corresponding to the activated memory bank of the first to fourth bulk voltage generators 110 to 140 and the first to fourth memory banks BANK0 to BANK3 is varied. The controller 200 may output the first to fourth control signals VBB_UP0 to VBB_UP3.

As illustrated in FIG. 3, the first bulk voltage generator 110 operates according to an enable signal OSCEN to generate a clock signal OSC, and according to the clock signal OSC. The charge pump 112 pumping the bulk voltage VBB_BANK0, the level detector 113 for outputting the enable signal OSCEN by determining whether the bulk voltage VBB is equal to or greater than a predetermined voltage level, and the first control signal. And a voltage level adjusting unit 114 for outputting a bulk voltage VBB_BANK0 that is higher than the original level or the original level in response to VBB_UP0. The first to fourth bulk voltage generators 110 to 140 have the same configuration.

The voltage level adjusting unit 114 includes a transistor M11 that connects the bulk voltage VBB_BANK0 to a ground terminal according to the first control signal VBB_UP0 to increase the bulk voltage VBB_BANK0 relative to its original level. do.

As illustrated in FIG. 4, the control unit 200 according to the active signal ACT and the first to fourth bank selection signals BA <0: 3> may include the first to fourth memory banks BANK0 to BANK3. ) The active determination unit 300 for outputting first to fourth active determination signals RATT0 to RACT3 for determining whether to activate each of the plurality of first and fourth active determination signals RATT0 to RACT3. The control signal generator 400 generates the first to fourth control signals VBB_UP0 to VBB_UP3.

The active determination unit 300 receives the active signal ACT in common and receives the first to fourth bank selection signals BA <0: 3>, respectively, and the first to fourth active determination signals RAT0 to First to fourth active decision logics 310 to 340 for outputting RACT3). The first active determination logic 310 receives the inverter IV31 receiving the active signal ACT, the output of the inverter IV31 and the first bank selection signal BA <0>, and receives the first active. And a NAND gate ND31 for outputting the determination signal RAT0. The first to fourth active decision logics 310 to 340 are configured in the same manner.

The control signal generator 400 receives the first to fourth active determination signals RATT0 to RACT3 and is activated for a predetermined period from a time when each of the active determination signals RATT0 to RACT3 is activated. First to fourth control signal generation logics 410 to 440 for generating the control signals VBB_UP0 to VBB_UP3 are provided. The first control signal generation logic 410 inputs a delay unit 411 for receiving the first active determination signal RAT0, and an output of the first active determination signal RAT0 and the delay unit 411. And a NAND gate ND41 for outputting the first control signal VBB_UP0.

The delay unit 411 is set to have a longer time for delaying the rising edge than the falling edge of the input signal. As shown in FIG. 5, the delay unit 411 includes a plurality of inverters IV1 to IVn and a plurality of capacitors C1 to Cn connected between the inverters. The plurality of inverters IV1 to IVn include a pull-up transistor M41 connected to a power supply terminal, a pull-down transistor M42 connected to a ground terminal, and an output terminal and the pull-down transistor M42. And a resistor R41 connected therebetween. The delay unit 411 has the resistor R41 connected in series with the output terminal of the inverter IV1 and the capacitors C1 and C2 are connected in parallel with the output terminal of the inverter IV1, thereby providing a basic inverter delay and an RC delay. The rising edges of the first to fourth active determination signals RATT0 to RACT3 are delayed longer than the falling edges. The delay unit 411 determines the activation period of the first to fourth control signals VBB_UP0 to VBB_UP3.

The operation of the semiconductor memory device according to the present invention configured as described above is as follows.

The controller 200 rises to the ground level VSS so that the level of the bulk voltage output from the bulk voltage generator corresponding to the activated memory bank among the first to fourth memory banks BANK0 to BANK3 is variable. The first to fourth control signals VBB_UP0 to VBB_UP3 are output.

For example, assume that the active signal ACT is activated and the first memory bank BANK0 is selected.

As shown in FIG. 6, the first active decision logic 310 of the active determiner 300 of the controller 200 has an output terminal A of the inverter IV31 when the active signal ACT is activated at a low level for a predetermined period. ) Becomes a high level for a predetermined period, and since the first bank selection signal BA <0> is activated to a high level during a period in which the output terminal A of the inverter IV31 maintains a high level, the first active determination signal Outputs (RACT0) at low level.

As shown in FIG. 7, the first control signal generation logic 410 of the control signal generator 400 of the controller 200 is activated at a low level during the predetermined period. The output terminal B of the delay unit 411 delays the rising edge of the first active determination signal RAT0 longer than the falling edge so that the low level period is increased compared to the first active determination signal RAT0. The NAND gate ND41 of the first control signal generation logic 410 receives the first active determination signal RAT0 and the output terminal B signal of the delay unit 411 to receive the first active determination signal RAT0. The first control signal VBB_UP0 having an activation period from the time of activation to the low level period of the output terminal B signal of the delay unit 411 is output.

The first bulk voltage generator 110 raises the bulk voltage VBB_BANK0 to the ground level VSS to the first memory bank BANK0 during the period in which the first control signal VBB_UP0 is activated. .

The operation of the semiconductor memory device according to the present invention when the active signal ACT for the read or write operation is activated and the first memory bank BANK0 and the second memory bank BANK1 are selected with a predetermined time difference is illustrated in FIG. 8. Is shown.

As the first active determination signal RAT0 is activated at a low level, the first control signal VBB_UP0 is activated at a high level for a predetermined period, and the first bulk voltage generator 110 generates the first control signal VBB_UP0. During the activation period, the bulk voltage VBB_BANK0 is raised to the ground level VSS and outputted to the first memory bank BANK0.

When the first active determination signal RAT0 is activated at a low level and the second active determination signal RAT1 is activated after a predetermined time, the second control signal VBB_UP1 is activated at a high level for a predetermined period, and the second bulk voltage is activated. The generator 120 increases the bulk voltage VBB_BANK1 to the ground level VSS to the second memory bank BANK1 during the period in which the second control signal VBB_UP1 is activated. The third and fourth bulk voltage generators 130 and 140 output bulk voltages VBB_BANK2 and VBB_BANK3 of the original level since the third and fourth control signals VBB_UP2 and VBB_UP3 are not activated.

The transistors of the first and second memory banks BANK0 and BANK1 have a threshold voltage lowered according to the bulk voltages VBB_BANK0 and VBB_BANK1 raised to the ground level during the active period, thereby lowering the power supply voltage or the word line driving voltage. Performs stable data transfer even if low.

In other words, as shown in FIG. 9, when an active command is first applied and an address corresponding thereto is input, the word line is selected and activated to the high potential voltage (VPP) level (WL Enable). Meanwhile, the first control signal VBB_UP0 for raising the bulk voltage VBB_BANK0 in response to the active command is activated during the predetermined period T1. By the first control signal VBB_UP0, the bulk voltage of the transistor disposed in the first memory bank BANK0 is increased to the ground level VSS relative to the bulk voltage having a negative potential. (VBB_BANK0) is provided.

Subsequently, the bit line is selected according to the address corresponding to the active command, and the sense amplifier in the selected bit line senses and amplifies the voltage of the bit lines BL (Bit Line) & / BL (Bit Line Bar). .

At this time, since the bulk voltage VBB_BANK0 of the elevated level is provided to the bulk terminal of the transistor, the threshold voltage of the transistor is lowered, so that data stored in the cell is more easily transmitted to the bit line. Therefore, the sensing amplifier can smoothly sense the amplification of the data signal applied to the bit lines BL (Bit Line) & / BL (Bit Line Bar).

It can be seen that the margin of the delta voltage Delta V, which is the difference in the voltage level of the line Y sensed by the present invention, that is, the bit line pair, is larger than the conventional line X sensed by the prior art.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The semiconductor memory device according to the present invention provides an independent bulk voltage for each memory bank, and adjusts the threshold voltage of the transistor of the cell by varying the bulk voltage level for the activated memory bank, thereby reducing the power supply voltage or the word line driving voltage. Even if it is low, it enables stable data sensing and amplification operation, and improves the performance of the semiconductor memory device.

Claims (11)

A semiconductor memory device comprising a cell region including a plurality of cells having a transistor whose threshold voltage is varied according to a bulk voltage supplied to a bulk terminal, wherein the cell region is divided into a plurality of memory banks. A plurality of bulk voltage generators varying a level of the bulk voltage according to a control signal to independently supply the bulk voltage to each of the plurality of memory banks; And A control unit for outputting the control signal so that the level of the bulk voltage of the bulk voltage generation unit corresponding to the activated memory bank among the plurality of memory banks is varied; The control unit An active determination unit for outputting an active determination signal for determining whether each of the plurality of memory banks is activated according to an active signal and a bank selection signal; And a control signal generator for generating the control signal according to the active determination signal. The active determination unit And a plurality of active determination logics configured to receive the active signal in common and receive a bank selection signal for each memory bank and output an active determination signal for each memory bank. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The bulk voltage generator An oscillator operating in response to the enable signal to generate a clock signal, A charge pump for pumping the bulk voltage according to the clock signal; A level detector for outputting an enable signal for operating the oscillator in accordance with the level of the bulk voltage, and And a voltage level adjusting unit for raising the level of the bulk voltage in response to the control signal. Claim 3 has been abandoned due to the setting registration fee. The method of claim 2, The voltage level adjusting unit And a switching element connecting the bulk voltage to a ground terminal according to the control signal. delete delete Claim 6 has been abandoned due to the setting registration fee. The method of claim 1, The active decision logic is An inverting device receiving the active signal, And a logic device configured to receive an output of the inverting device and a bank selection signal for each memory bank. Claim 7 has been abandoned due to the setting registration fee. The method of claim 1, The control signal generator And a plurality of control signal generation logics for receiving an active determination signal for each memory bank and generating a control signal for each memory bank that is activated for a predetermined period from the time when each active determination signal is activated. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The control signal generation logic is A delay unit configured to receive an active determination signal for each memory bank; And a logic device configured to receive an active determination signal for each memory bank and an output of the delay unit. Claim 9 has been abandoned due to the setting registration fee. 9. The method of claim 8, The delay unit The semiconductor memory device, characterized in that the time for delaying the rising edge is set longer than the falling edge of the input signal. Claim 10 has been abandoned due to the setting registration fee. 9. The method of claim 8, The delay unit And a plurality of inverters and capacitors connected between the inverters, wherein the inverter has a resistor connected between the pull-down transistor and the output terminal. Claim 11 was abandoned upon payment of a setup registration fee. 9. The method according to claim 6 or 8, And said logic element is a NAND gate.

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