KR20130138018A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, capable of reducing capacitance (Cb) between bit lines, tying a body, and reducing the junction area of the bit line by forming a PLAD junction area (a first junction area) on the sidewall of a buried bit line and a bit line junction area (a second junction area) on the lower side of the buried bit line.

Description

Technical Field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor device and a method of manufacturing the same, and more particularly, to a manufacturing method capable of improving the integration degree of a semiconductor device including a vertical transistor and improving operating characteristics and yield.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such a semiconductor is used to create a semiconductor device such as a transistor by adding impurities and connecting conductors. A device having various functions made using the semiconductor device is called a semiconductor device. A representative example of such a semiconductor device is a semiconductor memory device.

A semiconductor memory device includes a plurality of unit cells each composed of a capacitor and a transistor. The capacitor is used for temporarily storing data, and the transistor is connected to a control signal (word line) using the property of a semiconductor whose electric conductivity changes according to the environment. And is used to transfer data between the bit line and the capacitor correspondingly. A transistor is composed of three regions: a gate, a source, and a drain. Charge occurs between a source and a drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

When a conventional transistor is formed on a semiconductor substrate, a gate is formed on a semiconductor substrate, and impurities are doped on both sides of the gate to form a source and a drain. In this case, the region between the source and the drain under the gate becomes the channel region of the transistor. A transistor having such a horizontal channel region occupies a semiconductor substrate of a certain area, and in the case of a complicated semiconductor memory device, it is difficult to reduce the total area due to a plurality of transistors included therein.

Reducing the total area of the semiconductor memory device can increase the number of semiconductor memory devices that can be produced per wafer, thereby improving productivity. Various methods have been proposed to reduce the total area of the semiconductor memory device. One of them uses a vertical transistor having a vertical channel region instead of a conventional horizontal transistor having a horizontal channel region .

When the vertical transistor is applied as a cell transistor in a unit cell included in the semiconductor memory device, the size of the unit cell can be reduced to 4F2. Where F is the minimum distance between patterns in the design rule. When the vertical transistor is used as a cell transistor, a capacitor is connected to the upper part of the vertical transistor and a bit line connected to the lower part of the vertical transistor is buried in the semiconductor substrate. In this case, the word line connected to the gate of the cell transistor is formed in the form of enclosing the vertical pillar on the upper part of the bit line.

Such a vertical transistor is liable to be electrically short-circuited between the structurally buried bit line and the word line. Unlike conventional transistors, in which a body is formed on a wide and thick semiconductor substrate, the vertical transistor is limited not only to the very small size of the transistor body including the channel region but also to the punch-through ) And a floating body effect (short-channel effect). In order to overcome this disadvantage, an ion implantation process is performed to form a high concentration ion region, but impurities implanted due to the ion implantation process may cause an increase in electric field and increase a threshold voltage, resulting in deterioration of operational stability as a cell transistor. Can be. In addition, even if a high concentration ion region is formed, it is difficult to prevent an electrical short circuit between a bit line formed through ion implantation under a channel region of a vertical transistor and a word line formed on sidewalls of a channel region.

In order to solve the above-mentioned problems, the present invention forms a PLAD junction region (first junction region) on the sidewall of the buried bit line, and forms a bit line junction region (second junction region) below the buried bit line. Accordingly, the present invention provides a semiconductor device capable of reducing the junction area area of a bit line and enabling body tide, and a method of manufacturing a semiconductor device capable of reducing capacitance Cb between bit lines.

According to an embodiment of the present invention, a first pillar and a second pillar positioned on an upper surface of a semiconductor substrate, a bit line positioned at a bottom portion between the first pillar and a second pillar, a first junction region located at a side of the bit line, and a lower portion of the bit line A semiconductor device comprising a second junction region located at and thicker than the first junction region.

Preferably, the first junction region comprises arsenic (As).

Preferably, the bit line is characterized in that the structure is provided with a polysilicon layer.

Preferably, the semiconductor substrate further comprises a device isolation region defining an active region.

Preferably, the method may further include a junction region provided on the lower side and the sidewall of the device isolation region.

Preferably, the junction region is characterized in that the boron (boron) ion-implanted P-type junction region.

Preferably, the bit line is characterized in that the laminated structure of polysilicon and titanium nitride film.

In addition, the present invention comprises the steps of etching the semiconductor substrate to form a first pillar and a second pillar, forming a first junction region on the side between the first pillar and the second pillar, on the first junction region Forming a bit line, and forming a second junction region thicker than the first junction region under the bit line.

Preferably, the forming of the first pillar and the second pillar may include forming a first trench by etching the semiconductor substrate, forming a liner nitride layer on the first trench surface, and forming a first trench. Further etching the lower portion to form a second trench.

Preferably, after the forming of the second trench, forming an oxide film on the surface of the second trench, and performing implantation of PLAD on the surface of the second trench. .

Preferably, in the plade ion implantation process, arsenic (As) is ion implanted.

Preferably, the step of forming the bit line is characterized in that formed by burying polysilicon.

Preferably, the forming of the first joining region may further include removing the first joining region formed at a bottom portion between the first pillar and the second pillar.

In addition, the present invention is to form a device isolation region defining an active region on the semiconductor substrate, forming a junction region on the lower side and sidewalls of the device isolation region, etching the semiconductor substrate to form a first pillar and a second pillar Forming a first junction region on a side surface between the first pillar and the second pillar, forming a bit line above the first junction region, and forming a bit line below the first junction region, It provides a method for manufacturing a semiconductor device comprising the step of forming a thick second junction region.

The forming of the junction region may include forming a trench by etching the semiconductor substrate using an mask that defines the active region as an etch mask, and ion implanting boron into a lower portion and a sidewall of the trench. And further etching the lower portion of the trench, and ion implanting boron into the lower sidewall and the sidewall of the additionally etched trench.

Preferably, the forming of the first pillar and the second pillar may include forming a first trench by etching the semiconductor substrate, forming a liner nitride layer on the first trench surface, and forming a first trench. Further etching the lower portion to form a second trench.

Preferably, after the forming of the second trench, forming an oxide film on the surface of the second trench, and performing implantation of PLAD on the surface of the second trench. .

Preferably, in the plade ion implantation process, arsenic (As) is ion implanted.

Preferably, the step of forming the bit line is characterized in that formed by burying polysilicon.

Preferably, the forming of the first joining region may further include removing the first joining region formed at a bottom portion between the first pillar and the second pillar.

Preferably, the forming of the bit line includes embedding polysilicon in the second trench, etching back the embedded polysilicon, forming a conductive material on the etched back polysilicon, and It further comprises the step of etching back the conductive material.

Preferably, the conductive material is characterized in that it comprises a titanium nitride film (TiN).

According to the present invention, the PLAD junction region (first junction region) is formed on the sidewall of the buried bit line, and the bit line junction region (second junction region) is formed below the buried bit line, thereby reducing the junction area area of the bit line. Body Tied is possible, and the capacitance Cb between bit lines can be reduced.

1A to 1C are cross-sectional views illustrating a semiconductor device including a vertical transistor and a method of manufacturing the same according to an embodiment of the present invention.
2A to 2D are cross-sectional views illustrating a semiconductor device including a vertical transistor and a method of manufacturing the same according to another embodiment of the present invention.
3A to 3D are cross-sectional views illustrating a semiconductor device including a vertical transistor and a method of manufacturing the same according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

Referring to FIG. 1A, an isolation region 110 defining an active region 105 is formed in a semiconductor substrate 100. The device isolation region 110 may be formed by embedding a silicon on dielectric (SOD) material in a trench (not shown) formed by etching the semiconductor substrate 100 using the mask defining the active region 105 as an etching mask. desirable.

Next, a hard mask pattern 120 is formed on the semiconductor substrate 100. In this case, the hard mask pattern 120 preferably includes a nitride film. Here, the hard mask pattern 120 is preferably a patterned structure to form a buried bitline.

Next, the first trench 130 is formed by etching the active region 105 and the device isolation region 110 using the hard mask pattern 120 as an etch mask.

Next, an oxidation process is performed on the first trench 130, and a liner nitride layer 140 is deposited on the surface of the oxidized first trench 130.

Referring to FIG. 1B, the lower portion of the first trench 130 is additionally etched using the hard mask pattern 120 as an etch mask to form the second trench 150.

 Next, an oxidation process is performed on the exposed second trench 150 to form an oxide film 160 on the surface of the second trench 150, and then a plaque is formed on the surface of the oxidized second trench 150. The first ionization region 170 may be formed on the side and the bottom of the second trench 150 by implanting PLAD ions. Thereafter, it is preferable to partially remove the oxide film 160 by using a cleaning process. Here, fluoride (PLAD) ion implantation uses arsenic (As), and during ion implantation, since the oxide layer 160 is thin, ion implantation is performed through the oxide layer 160 and onto the surface of the semiconductor substrate 100.

Referring to FIG. 1C, the first junction region 170 is removed using the liner nitride layer 140 as a mask until the semiconductor substrate 100 is exposed. After that, it is also preferable to remove the liner nitride layer 140.

Next, after the doped polysilicon 180 is buried in the exposed semiconductor substrate 100 and the second trench 150, the embedded polysilicon 180 is formed to be similar to the height of the junction region 170 on the side surface. Etch back to complete the buried bitline. Here, the bit line junction region 185 (second junction region) is provided under the second trench 150 by the doped polysilicon 180.

Thereafter, an oxidation process is performed on the polysilicon 180 and the exposed semiconductor substrate 100 to form an oxide film 190.

2A to 2D are cross-sectional views illustrating a semiconductor device including a vertical transistor and a method of manufacturing the same according to another embodiment of the present invention.

Referring to FIG. 2A, an isolation region 240 defining an active region 205 is formed in the semiconductor substrate 200. Here, the semiconductor substrate 200 is etched to a predetermined depth using a mask defining the active region 205, and then boron is implanted into the bottom and sidewalls of the etched trench, and the bottom of the trench is further added. After etching, the process of ion implanting boron into the lower sidewall and the sidewall of the additionally etched trench is repeated to provide a P-type junction region 230 (junction). Body Tied may be improved by forming the P-type junction region 230 on the lower and sidewalls of the device isolation region 240. Subsequently, a silicon on dielectric (SOD) material is embedded in the trench 220 to complete the device isolation region 240.

Referring to FIG. 2B, a hard mask pattern 250 is formed on the semiconductor substrate 200. In this case, the hard mask pattern 250 preferably includes a nitride film. Here, the hard mask pattern 250 is preferably a patterned structure to form a buried bitline.

Next, the first trench 260 is formed by etching the active region 205 and the device isolation region 240 using the hard mask pattern 250 as an etch mask.

Next, an oxidation process is performed on the first trench 260, and a liner nitride layer 270 is deposited on the surface of the oxidized first trench 260.

Referring to FIG. 2C, the lower portion of the first trench 260 is additionally etched using the hard mask pattern 250 as an etch mask to form the second trench 280.

 Next, an oxidation process is performed on the exposed second trench 280 to form an oxide film 290 on the surface of the second trench 280, and then a plaque is formed on the surface of the oxidized second trench 280. The first ionization region 300 is formed on the side and the bottom of the second trench 280 by implanting a PLD ion implantation. Thereafter, it is preferable to partially remove the oxide film 290 by using a cleaning process. Here, fluoride (PLAD) ion implantation uses arsenic (As), and during ion implantation, since the oxide film 290 is thin, the ion implanted through the oxide film 290 to the surface of the semiconductor substrate 200.

Referring to FIG. 2D, the first junction region 300 is removed using the liner nitride layer 270 as a mask until the semiconductor substrate 200 is exposed. Thereafter, the liner nitride film 270 may also be removed.

Next, after filling the exposed semiconductor substrate 200 and the polysilicon 310 doped in the second trench 280, similar to the height of the first junction region 300 on the side of the second trench 280. Etch back the embedded polysilicon (310). Here, the second junction region 315 (bit line junction region) is provided under the second trench 280 by the doped polysilicon 310.

Thereafter, an oxidation process is performed on the polysilicon 310 and the exposed semiconductor substrate 200 to form an oxide film 320.

3A to 3D are cross-sectional views illustrating a semiconductor device including a vertical transistor and a method of manufacturing the same according to still another embodiment of the present invention.

Referring to FIG. 3A, an isolation region 440 defining an active region 405 is formed in the semiconductor substrate 400. Here, the semiconductor substrate 400 is etched to a predetermined depth using a mask defining the active region 405, followed by ion implantation of boron into the bottom and sidewalls of the etched trench, and then adding the bottom of the trench again. After etching, a process of ion implanting boron into the lower sidewall and the sidewall of the additionally etched trench is repeated to provide a P-type junction region 430 (junction). Body Tied may be improved by forming the P-type junction region 430 on the lower and sidewalls of the device isolation region 440. Subsequently, a silicon on dielectric (SOD) material is embedded in the trench 420 to complete the device isolation region 440.

Referring to FIG. 3B, a hard mask pattern 450 is formed on the semiconductor substrate 400. In this case, the hard mask pattern 450 preferably includes a nitride film. Here, the hard mask pattern 450 is preferably a patterned structure to form a buried bitline.

Next, the first trench 460 is formed by etching the active region 405 and the device isolation region 440 using the hard mask pattern 450 as an etching mask.

Next, an oxidation process is performed on the first trench 460, and a liner nitride layer 470 is deposited on the surface of the oxidized first trench 460.

Referring to FIG. 3C, the lower portion of the first trench 460 is further etched using the hard mask pattern 450 as an etch mask to form the second trench 480.

 Next, an oxidation process is performed on the exposed second trench 480 to form an oxide film 490 on the surface of the second trench 480, and then a plaque is formed on the surface of the oxidized second trench 480. The first ionization region 500 may be formed on the side and the bottom of the second trench 480 by performing implantation. Afterwards, it is preferable to partially remove the oxide film 490 using a cleaning process. Here, fluoride (PLAD) ion implantation uses arsenic (As), and during ion implantation, since the oxide film 490 is thin, it is implanted into the surface of the semiconductor substrate 400 through the oxide film 490.

Referring to FIG. 3D, the lower first bonding region 500 is removed using the liner nitride layer 470 as a mask until the semiconductor substrate 400 is exposed. Thereafter, it is preferable to also remove the liner nitride film 470.

Next, after the doped polysilicon 510 is buried in the exposed semiconductor substrate 400 and the second trench 480, the embedded polysilicon 510 is etched back. Here, the second junction region 515 (bit line junction region) is provided under the second trench 480 by the doped polysilicon 510.

Next, after the conductive layer 520 is formed on the doped polysilicon 510, the embedded conductive layer 520 is etched back. Here, the conductive layer 520 preferably includes a titanium nitride film (TiN). Thereafter, a spacer nitride film 530 is formed on the surface of the conductive layer 520 and the exposed semiconductor substrate 400.

According to the present invention, the PLAD junction region (first junction region) is formed on the sidewall of the buried bit line, and the bit line junction region (second junction region) is formed below the buried bit line, thereby reducing the junction area area of the bit line. Body Tied is possible, and the capacitance Cb between bit lines can be reduced.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (22)

A first pillar and a second pillar positioned on the semiconductor substrate;
A bit line located at a bottom between the first pillar and the second pillar;
A first junction region positioned on the side of the bit line; And
A second junction region below the bit line and thicker than the first junction region
And a semiconductor layer formed on the semiconductor substrate. The method according to claim 1,
The first junction region includes arsenic (As). The method according to claim 1,
The bit line is a semiconductor device, characterized in that the structure provided with a polysilicon layer. The method according to claim 1,
The semiconductor substrate further comprises a device isolation region defining an active region. The method of claim 4,
And a junction region provided on the lower and sidewalls of the device isolation region. The method according to claim 5,
And the junction region is a P-type junction region into which boron is ion-implanted. The method according to claim 1,
The bit line is a semiconductor device, characterized in that the laminated structure of polysilicon and titanium nitride film. Etching the semiconductor substrate to form a first pillar and a second pillar;
Forming a first junction region on a side surface between the first pillar and the second pillar;
Forming a bit line on the first junction region; And
Forming a second junction region thicker than the first junction region under the bit line;
And forming a second insulating film on the semiconductor substrate. The method according to claim 8,
Forming the first pillar and the second pillar
Etching the semiconductor substrate to form a first trench;
Forming a liner nitride film over the first trench surface; And
And etching the lower portion of the first trench to form a second trench. The method of claim 9,
After forming the second trench,
Forming an oxide film on the surface of the second trench;
And implanting PLAD ions into the surface of the second trench. The method of claim 10,
A method of manufacturing a semiconductor device, characterized in that the arsenic (As) is ion-implanted during the plade ion implantation process. The method according to claim 8,
The forming of the bit line is a method of manufacturing a semiconductor device, characterized in that formed by embedding polysilicon. The method according to claim 8,
Wherein forming the first junction region comprises:
And removing the first junction region formed at the bottom portion between the first pillar and the second pillar. Forming an isolation region defining an active region in the semiconductor substrate, wherein forming a junction region under and sidewalls of the isolation region;
Etching the semiconductor substrate to form a first pillar and a second pillar;
Forming a first junction region on a side surface between the first pillar and the second pillar;
Forming a bit line on the first junction region; And
Forming a second junction region thicker than the first junction region under the bit line;
And forming a second insulating film on the semiconductor substrate. The method according to claim 14,
Forming the junction region is
Forming a trench by etching the semiconductor substrate using the mask defining the active region as an etching mask;
Implanting boron into the bottom and sidewalls of the trench;
Further etching the lower portion of the trench;
And implanting boron into the bottom and sidewalls of the additionally etched trench. The method according to claim 14,
Forming the first pillar and the second pillar
Etching the semiconductor substrate to form a first trench;
Forming a liner nitride film over the first trench surface; And
And etching the lower portion of the first trench to form a second trench. 18. The method of claim 16,
After forming the second trench,
Forming an oxide film on the surface of the second trench;
And implanting PLAD ions into the surface of the second trench. 18. The method of claim 17,
A method of manufacturing a semiconductor device, characterized in that the arsenic (As) is ion-implanted during the plade ion implantation process. The method according to claim 14,
The forming of the bit line is a method of manufacturing a semiconductor device, characterized in that formed by burying polysilicon. The method according to claim 14,
Wherein forming the first junction region comprises:
And removing the first junction region formed at the bottom portion between the first pillar and the second pillar. The method according to claim 14,
Forming the bit line comprises embedding polysilicon in a second trench;
Etching back the embedded polysilicon;
Forming a conductive material on the etched back polysilicon; And
And etching back the conductive material. 23. The method of claim 21,
The conductive material comprises a titanium nitride film (TiN) method of manufacturing a semiconductor device.

Images