KR20130112177A - System for controling channel width of power switch - Google Patents

Abstract

PURPOSE: A power switch channel width control device is provided to improve the efficiency of a switching converter while minimizing the power loss of a power switch. CONSTITUTION: A power switch channel width control device includes a current sensor (100), an average switch unit (200), and a partial switch unit (300). The current sensor applies a voltage value to a + terminal of a comparator (110), applies each voltage to a terminal of the comparator, and outputs S1 to S8 signals through the comparator. The average switch unit is composed of a PMOS power switch or NMOS power switch to switch connection with the partial switch unit regardless of the voltage value. The partial switch unit is composed of a plurality of PMOS power switches or NMOS power switches to be matched with the S1 to S8 signals applied from the current sensor.

Description

Power switch channel width control device {SYSTEM FOR CONTROLING CHANNEL WIDTH OF POWER SWITCH}

The present invention relates to a power switch channel width control device, and more particularly, to a technique for improving stability by minimizing conduction loss of a power switch and minimizing gate driving loss.

With the recent boom of smartphones in society, the importance of power management of mobile devices has become more and more important. Mobile phones, which were intended for personal communication, have been extended to various multimedia functions as well as communication functions as smart phones are on the rise. With this trend, the functions of laptops and video devices, which were fixed equipment, are becoming more portable and the functions of portable devices continue to expand.

In addition, a variety of electronic devices have been integrated in portable devices incorporating various functions, which means demand for various power supplies. That is, even if one portable device is powered from one battery, each building block requires a different power supply condition.

In addition, the handheld device is small and light but must be operated at any time as required, which requires maximum operating time with limited battery capacity. There are new materials such as NiCd, NiMH, or Li Ion in battery materials, and various developments are being made for power management devices to efficiently use power, and in terms of circuits, development of power device management ICs for power management devices. As a result, technology is concentrated.

Korean Patent Publication No. 10-2003-0045820 (Power control and modulation of switch-mode power amplifiers having one or more stages) discloses a technique for a control method for a power amplifier in a switch mode.

Referring to FIG. 1, the method of varying a signal applied to a power port of an amplifier device to control at least one of a modulation characteristic and a power output of an output signal of the amplifier device generated at an output port of the amplifier device; And selectively varying the amplitude of the input signal applied to the input port of the amplifier device in accordance with the desired characteristics of the output signal of the amplifier device, wherein the final amplifier stage in the linear operating region for a significant proportion of time. Inoperative, it has a drive signal that causes it to be driven repeatedly between two states, a hard-on state and a hard-off state, and the final amplifier stage is a continuous or frequent measurement of the variable output signal. And controlled without feedback adjustment.

However, the configuration for varying the signal applied to the power port and for selectively varying the amplitude of the input signal applied to the input port is configured to modulate the pulse width through the DC-DC converter and apply the switched signal to the filter. The problem arises that the size of the measurement subblock is large and the power consumed by itself is also large.

An object of the present invention is to minimize the power loss of the power switch and improve the efficiency of the switching converter by controlling the channel width of the power switch by the switch operation of each of the partial switches according to the signal received from the comparator by the current sensing stage. Sikkim has that purpose.

In order to achieve the above technical problem, the power switch channel width control apparatus of the present invention applies a voltage value of Sensing extracted from the load stage to the + stage of the comparator 110, and at the-stage of the comparator 110, A current sensing unit 100 that applies a voltage and outputs S1 to S8 signals through the comparator 110; An average switch unit 200 including a PMOS (MP1) power switch and an NMOS (MN1) power switch to switch the connection with the partial switch unit 300 regardless of the voltage value applied from the current sensing unit 100; And a plurality of PMOS (MP2 to MP5) power switches and NMOS (MN2 to MN5) power switches to correspond to the output signals S1 to S8 applied from the current sensing unit 100 through switching of the average switch unit 200. It includes; switch portion 300 that operates to.

In addition, the comparator 110 may include a first comparator 111 configured to receive a voltage value of Sensing through a + stage and a voltage of Vref through a − stage to output an S1 signal and an S5 signal; A second comparator 112 receiving a voltage value of Sensing through a + stage and a voltage of 3 / 4Vref through a-stage to output an S2 signal and an S6 signal; A third comparator 113 configured to receive a voltage value of Sensing through a + stage, and output a S3 signal and an S7 signal by receiving a voltage of 1 / 2Vref through a-stage; And a fourth comparator 114 that receives the voltage value of the sensing through the + stage, and outputs the S4 signal and the S8 signal by receiving a voltage of 1 / 4Vref through the − stage.

In addition, the average switch unit 200 further includes a dead-time controller for controlling the power switch NMOS MN1 and the PMOS MP1 to be simultaneously turned ON and OFF.

In addition, the partial switch unit 300 is characterized in that the control to determine the operation number of the PMOS power switch and the NMOS power switch in accordance with the current value flowing through the load of the average switch unit 200.

According to the present invention as described above, by controlling the channel width of the power switch by the switch operation of each of the partial switches in accordance with the signal applied from the comparator, the power loss of the power switch and the efficiency of the switching converter Has the effect of improving.

In addition, according to the present invention, minimizing the power loss of the power switch and improve the efficiency of the switching converter can be used in devices requiring low power, such as a power management device or an electrocardiogram measurement chip of a portable device, and extends the life of the battery It is effective to plan.

1 is a block diagram illustrating power control and modulation of a switch-mode power amplifier having one or more stages of the prior art.
Figure 2 is a block diagram showing a power switch channel width control apparatus according to the present invention.
3 is a view illustrating a current sensing circuit and an operation process of a power switch channel width control apparatus according to the present invention.
4 is a view showing a switch block control circuit of the power switch channel width control apparatus according to the present invention.
5 is a circuit diagram showing a four-foot controller of the power switch channel width control apparatus according to the present invention.
Figure 6 is a circuit diagram showing a parasitic element of the power switch for the power switch channel width control apparatus according to the present invention.
7 is a view showing a power switch current sensing waveform of the partial switch unit for the power switch channel width control apparatus according to the present invention.
8 is a view showing a power switch control waveform of the partial switch unit for the power switch channel width control apparatus according to the present invention.

Specific features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings. Prior to this, terms and words used in the present specification and claims are to be interpreted in accordance with the technical idea of the present invention based on the principle that the inventor can properly define the concept of the term in order to explain his invention in the best way. It should be interpreted in terms of meaning and concept. In addition, when it is determined that the detailed description of the known function and its configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, it should be noted that the detailed description is omitted.

Hereinafter, the power switch channel width control apparatus A according to the present invention will be described in detail with reference to the accompanying drawings.

2 is an overall configuration diagram of a power switch channel width control device A according to the present invention. As shown in FIG. 2, the power switch channel width control apparatus A according to the present invention includes a current sensing unit 100, an average switch unit 200, and a partial switch unit 300.

First, the current sensing unit 100 applies the voltage value of the sensing extracted from the current sensing circuit to the + end of the comparator 110, and applies the voltage of each Vref to the-end of the comparator 110, and the comparator 110. ) Outputs the S1 to S8 signals.

Specifically, the first comparator 111 of the comparator 110 receives the voltage value of Sensing through the + terminal, and receives the voltage of Vref through the − terminal to output the S1 signal and the S5 signal.

In addition, the second comparator 112 receives a voltage value of Sensing through a + terminal, and receives a voltage of 3 / 4Vref through a − terminal to output an S2 signal and an S6 signal.

In addition, the third comparator 113 receives a voltage value of Sensing through the + terminal and outputs an S3 signal and an S7 signal by receiving a voltage of 1 / 2Vref through the − terminal.

In addition, the fourth comparator 114 receives a voltage value of Sensing through the + terminal and outputs an S4 signal and an S8 signal by receiving a voltage of 1 / 4Vref through the − terminal.

In addition, the current sensing unit 100 of the power switch channel width control apparatus (A) according to the present invention, as shown in a) of FIG. 3, enables a high voltage swing in the load sensing stage to smoothly detect even a low supply voltage. Maintain functionality.

In addition, the P-channel switch outputs a load current sense value at turn-on. MP1 is a PMOS power switch and MP2 and MS2 have a width reduced to 1/2500 of MP1.

Further, as shown in FIG. 3B, the drain terminal potential is kept close. In this case, the linearity is increased by reducing the error by adjusting the size of the transistor MS1 to make the Vds voltage as small as possible. In order to keep the potentials of the Va and Vb nodes the same, a two stage operational amplifier having a wide output voltage range was used.

값이 변화 한다는 것이다.In addition, creating an optimal channel can produce conduction losses and gate losses consumed by the power switch, but the problem is that depending on the current flowing into the load stage during operation,

The value changes.

Therefore, the power switch channel width control apparatus A according to the present invention, as shown in Figure 4, the current sensing unit 100 detects the current flowing in the load stage and transmits to the comparator 110, the comparator ( The signal from 110 adjusts the subblock of the switch.

In addition, the power switch is composed of a switch control and a switch subblock, that is, the average switch unit 200 and the partial switch unit 300, as shown in Figure 4, the operation of the partial switch in accordance with the current value flowing through the load stage The number can be determined. Thus, the present invention is configured such that the switch is in fluid operation to maintain minimum power consumption in accordance with the value of the current flowing in the load stage.

Meanwhile, the average switch unit 200 is composed of a PMOS (MP1) power switch and an NMOS (MN1) power switch to switch the connection with the partial switch unit 300 regardless of the voltage value applied from the current sensing unit 100. . At this time, the magnitude of the voltage applied from the average switch unit 200 changes depending on the amount of current flowing.

In the case of the conventional power switch, when the NMOS MN1 is turned ON, the PMOS MP1 is turned OFF, and when the PMOS MP1 is turned ON, the NMOS MN1 is turned OFF. Complementary driving, a large power loss occurs as each power switch is short-circuit instantaneously.

Therefore, the power switch NMOS (MN1) and PMOS (MP1) of the average switch unit 200 according to the present invention constitutes a dead-time controller as shown in FIG. And PMOS (MP1) are configured to simultaneously turn ON and OFF.

Specifically, the design of the power switch NMOS (MN1) and PMOS (MP1) of the power switch channel width control device (A) according to the present invention, the parasitic resistance and capacitor components according to the size of the power switch as shown in FIG. Design in consideration of these.

The power supply and the PMOS parasitic positioned between the switch resistance R _vddp and parasitic generated in the transmission line to the ground and the NMOS parasitic positioned between the switch resistance R _gndp and the two switches and the inductor resistance R _sw are large in conduction loss (conduction loss) Affect When the respective switch is on, the parasitic resistance R and R _{onp onn} generated in the inside of the switch is designed to be equal to the symmetry of the rising operation and the lowering operation of the pulse generated by the switch.

In addition, C _sw represents the parasitic capacitor generated at the switch output stage, and C _{in_p} and Cin_n are the parasitic capacitors generated at the gate of the MOSFET switch, and should be considered when designing a power switch driver. There are gate charge and discharge losses for switch operation control and losses due to channel resistance of the power switch.

In addition, the partial switch unit 300 of the power switch channel width control device A according to the present invention is composed of a plurality of PMOS (MP2 to MP5) power switches and NMOS (MN2 to MN5) power switches, the average switch unit ( The switch 200 operates to correspond to each of the output signals S1 to S8 applied from the current sensing unit 100.

That is, the number of operations of the PMOS power switch and the NMOS power switch is determined according to the current value flowing through the load of the average switch unit 200.

Hereinafter, a simulation test result of the power switch channel width changing circuit of the power switch channel width control device A according to the present invention is as follows.

In order to adjust the channel width of the power switch, it is necessary to know the value of the current flowing through the output stage. In order to sense the current value, the current waveform input to the current conversion circuit may be applied to the switch block control circuit without using an additional subblock.

The waveform shown in FIG. 7 is the Vsense waveform of the circuit shown in FIG. In order to operate the power switch channel width control circuit according to the present invention, the value of the load current sensing circuit was used without using an additional circuit.

At this time, the waveform of the current shows the operating range from 0V to 2.7V, accordingly the waveform that the signal for controlling the sub power switch through the comparator shown in FIG. 4 is output as shown in FIG.

While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It will be appreciated by those skilled in the art that numerous changes and modifications may be made without departing from the invention. And all such modifications and changes as fall within the scope of the present invention are therefore to be regarded as being within the scope of the present invention.

A: power switch channel width control device
100: current detection unit 110: comparator
111: first comparator 112: second comparator
113: third comparator 114: fourth comparator
200: average switch unit 300: partial switch unit

Claims (4)

In the power switch channel width control device,
The voltage value of Sensing extracted from the load terminal is applied to the + terminal of the comparator 110, the voltage of each Vref is applied to the-terminal of the comparator 110, and the S1 to S8 signal is transmitted through the comparator 110. A current sensing unit 100 for outputting;
An average switch unit 200 including a PMOS (MP1) power switch and an NMOS (MN1) power switch to switch the connection with the partial switch unit 300 regardless of the voltage value applied from the current sensing unit 100; And
And a plurality of PMOS (MP2 to MP5) power switches and NMOS (MN2 to MN5) power switches, each of output signals S1 to S8 applied from the current sensing unit 100 through switching of the average switch unit 200; The power switch channel width control device comprising a; and a partial switch unit 300 to operate correspondingly. The method of claim 1,
The comparator 110,
A first comparator 111 that receives a voltage value of Sensing through a + stage and receives a voltage of Vref through a-stage and outputs an S1 signal and an S5 signal;
A second comparator 112 receiving a voltage value of Sensing through a + stage and a voltage of 3 / 4Vref through a-stage to output an S2 signal and an S6 signal;
A third comparator 113 configured to receive a voltage value of Sensing through a + stage, and output a S3 signal and an S7 signal by receiving a voltage of 1 / 2Vref through a-stage; And
A fourth comparator 114 that receives the voltage value of the sensing through the + stage, and outputs the S4 signal and the S8 signal by receiving the voltage of 1 / 4Vref through the-stage; controller. The method of claim 1,
The average switch unit 200,
And a dead-time controller for controlling the power switch NMOS MN1 and the PMOS MP1 to be simultaneously turned ON and OFF. The method of claim 1,
The partial switch unit 300,
And controlling the number of operation of the PMOS power switch and the NMOS power switch according to the current value flowing through the load of the average switch unit 200.

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