KR20130077565A - Semiconductor package and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to simplify processes by successively manufacturing passive devices in a package process after a process for forming a passivation layer is performed. CONSTITUTION: A semiconductor chip (120) is mounted on a package substrate. A passivation layer (140) molds the semiconductor chip on the package substrate. A via layer electrically connects a passive device (150) to the package substrate. The passive device is arranged on the passivation layer. The first electrode and the second electrode of the passive device are arranged on different surfaces of the passivation layer.

Description

Semiconductor package and method of manufacturing the same

The present application relates generally to a semiconductor package, and more particularly, to a semiconductor package including a passive device and a method of manufacturing the same.

Recently, semiconductor package technology is accelerating the trend of high performance, high integration, miniaturization, light weight, and thickness. Examples of technologies driving this trend include flip chip technology, multi chip module technology, multilayer packaging technology, package-on-package technology, and through silicon via technology. It is currently applied to various packaged products.

In addition, as the above-described package technology is miniaturized, reduced in weight, thinned, and highly integrated, a package technology such as a system-in-package (SIP) in which chips of various functions are embedded in one package has appeared. In addition, an integrated passive device (IPD) technology, which implements various functions by mounting passive devices such as an inductor and a capacitor in a package substrate, has also appeared.

Such SIP package technology is applied to a wireless communication chip as an example, and not only an active device chip but also the aforementioned passive devices are integrated in a package. On the other hand, the recent trend of increasing passive devices employed in SIP packages outpaces the trend of active devices. However, there is a difficulty in that the area and volume of the package are not sufficient to accommodate the passive devices. As an example, a built-in antenna for wireless transmission and reception is required in a wireless communication chip package. However, in the related art, a separate antenna chip or a separately manufactured built-in antenna may be inserted into a package substrate and packaged. Such a problem corresponds to a problem to be overcome in the trend of miniaturization and thinning of packages, and research on this has recently been actively conducted.

The technical problem to be solved by the present application is to provide a semiconductor package incorporating passive elements having sufficient performance in order to achieve miniaturization and size reduction of the package size.

Another technical problem to be solved by the present application is to provide a method of manufacturing a semiconductor package incorporating a passive device having sufficient performance as described above.

A semiconductor package according to an embodiment of the present application for achieving the above technical problem is disclosed. The semiconductor package is electrically connected to the package substrate through a package substrate, a semiconductor chip mounted on the package substrate, a passivation layer molding the semiconductor chip on the package substrate, and a via layer formed through the passivation layer. And a passive element disposed on the passivation layer. In this case, the first electrode and the second electrode of the passive element are disposed on different planes above the passivation layer.

A semiconductor package according to another embodiment of the present application for achieving the above technical problem is disclosed. The semiconductor package may include at least one semiconductor chip, a conductive plate disposed along an outer portion of the semiconductor chip, a passivation layer molding the semiconductor chip and the conductive plate, and a via layer formed in the passivation layer. A passive element electrically connected and disposed on the passivation layer. In this case, the first electrode and the second electrode of the passive element are disposed on different planes.

Disclosed is a method of manufacturing a semiconductor package according to another aspect of the present application for achieving the above technical problem. In the method of manufacturing the semiconductor package, first, a package substrate including an integrated circuit is provided. At least one via layer is formed on the package substrate. The semiconductor chip is mounted on the package substrate. A passivation layer is formed to mold the via layer and the semiconductor chip. Passive devices are formed on the passivation layer. In this case, the first electrode and the second electrode of the passive element are disposed on different planes above the passivation layer.

Disclosed is a method of manufacturing a semiconductor package according to another aspect of the present application for achieving the above technical problem. In the method of manufacturing the semiconductor package, first, a substrate for packaging is provided. A conductive plate having a hole pattern is formed on the substrate. At least one semiconductor chip is disposed in the hole pattern of the conductive plate. A passivation layer is formed to mold the semiconductor chip and the conductive plate. At least one via layer connected to the conductive plate is formed through the passivation layer. Passive elements are formed on the passivation layer that are electrically connected to the conductive plates through the via layers. In this case, at least one of the at least one semiconductor chip is electrically connected to the conductive plate.

According to an embodiment of the present application, a passive element may be formed on the upper surface of the passivation layer for embedding the semiconductor chip. In the related art, a passive device, which is manufactured separately and introduced into a package substrate, may be continuously manufactured after the passivation layer forming process in a package process. As a result, the process can be simplified, and the semiconductor package can be made smaller and thinner.

In addition, the area of the upper surface of the passivation layer can thereby be sufficiently used for the passive element. That is, on the upper portion of the passivation layer, each electrode layer of the passive element can be formed on a separate plane. Thus, in the case of a passive element, that is, a capacitor, sufficient capacitance can be obtained, and in the case of an inductor, sufficient inductance can be secured. For example, when applied to a wireless chip package, it is possible to easily implement a frequency filter, EMC, a wireless antenna, etc. in a reduced package area and volume than conventional.

1 is a schematic view of a semiconductor package according to an embodiment of the present application.
2 is a diagram schematically illustrating a semiconductor package according to another exemplary embodiment of the present application.
3 is a schematic view of a semiconductor package according to another embodiment of the present application.
4 is a flowchart schematically illustrating a method of manufacturing a semiconductor package according to an embodiment of the present application.
5 to 9 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor package according to an embodiment of the present application.
10 is a flowchart schematically illustrating a method of manufacturing a semiconductor package according to an embodiment of the present application.
11 to 17 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor package according to another embodiment of the present application.
18 to 24 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor package according to another embodiment of the present application.

Embodiments of the present application will now be described in more detail with reference to the accompanying drawings. However, the techniques disclosed in this application are not limited to the embodiments described herein but may be embodied in other forms. It should be understood, however, that the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device. It is to be understood that when an element is described as being located on another element, it is meant that the element is directly on top of the other element or that additional elements can be interposed between the elements . It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. In the drawings, the same reference numerals denote substantially the same elements.

In addition, singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and the terms "comprise" or "having" include features, numbers, steps, operations, components, and parts described. Or combinations thereof, it is to be understood that they do not preclude the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

In addition, in carrying out a method or a manufacturing method, each process constituting the method may occur differently from the stated order unless the context clearly indicates a specific order. That is, each process may occur in the same order as described, may be performed substantially concurrently, or may be performed in the opposite order.

As used herein, "top" or "bottom" is relatively described at the viewer's point of view, and in some cases, the "top" is replaced by "bottom", and the "bottom" may be interchanged with "top". It is a concept.

The term package substrate as used herein may be extended to mean a substrate on which the semiconductor chip is mounted or the semiconductor chip die itself. As an example, the package substrate can be broadly interpreted as a chip die of an active element. The package substrate may be made of various materials. That is, semiconductor materials such as silicon, germanium, gallium arsenide, and the like, ceramic materials such as glass, glass, quartz, metal carbide, organic materials such as polymers, and the like. In addition, a package substrate may mean not only a single layer board | substrate but a laminated multilayer board | substrate. In addition, the package substrate may mean an interposer for connecting the semiconductor chip and another substrate. The package substrate may include integrated circuits inside and on the surface.

1 is a schematic view of a semiconductor package according to an embodiment of the present application. Specifically, FIG. 1A is a cross-sectional view of a semiconductor package as an embodiment, and FIG. 1B is a perspective plan view of a semiconductor package as an embodiment.

Referring to FIG. 1A, the semiconductor package 100 molding the package substrate 110, the semiconductor chip 120 mounted on the package substrate 110, and the semiconductor chip 120 on the package substrate 110. Passivation layer 140, and a passive element 150 disposed on the passivation layer 140. In addition, the semiconductor package 100 includes a bump structure 190 disposed on the passivation layer 140 on which the passive element 150 is disposed.

As an example, the semiconductor chip 120 may be bonded to a connection pad (not shown) of the package substrate 110 using the bump 125. As another example, the semiconductor chip 120 may be bonded to a connection pad (not shown) of the package substrate 110 by a wire bonding method. The semiconductor chip 120 may be electrically connected to an integrated circuit (not shown) disposed on the package substrate 110, and the passive element 150 and the package substrate 110 mounted on the package substrate 110 through the integrated circuit. ) Can be electrically connected to an external circuit.

At least one via layer 130 is disposed in the passivation layer 140. The via layer 130 penetrates the passivation layer 140 and is electrically connected to the package substrate 110. According to an embodiment, a plurality of via layers 130 may be disposed in the passivation layer 140, and may electrically connect an electrode portion of the passive element 150 and a connection pad (not shown) of the package substrate 110. . In addition, although not illustrated, the via layer 130 may be electrically connected to the package substrate 110, the connection pad 180, and the bump structure 190.

The passive element 150 is disposed on the passivation layer 140 and is electrically connected to the package substrate 110 through the via layer 130. The passive element 150 may include, for example, an inductor or a capacitor. When the semiconductor chip 120 is a wireless chip, the passive element 150 may include, for example, a radio (RF) antenna or a frequency filter.

As shown, the passive element 150 may be a capacitor including a first electrode 152 and a second electrode 154. The first electrode 152 of the passive element 150 is electrically connected to any one of the plurality of via layers 130 and is disposed on one surface of the passivation layer 140. The first insulator layer 160 is disposed on the first electrode 152. The second electrode 154 of the passive element 150 is disposed on the first insulator layer 160, and the second electrode 154 is electrically connected to another one of the plurality of via layers 130. When the passive element 150 is a capacitor, the first insulator layer 160 may function as a dielectric layer of the capacitor.

Referring to the drawings, the first electrode 152 and the second electrode 154 of the passive element 150 are disposed on different planes, and are electrically insulated from each other by the first insulator layer 160. Referring again to FIGS. 1A and 1B, the first electrode 152 and the second electrode 154 of the passive element 150 are designed to have a sufficient area on the plane where they are respectively disposed. The first electrode 152 and the second electrode may have regions 156 overlapping each other, and may generate capacitances defined by areas of the overlapping regions 156. That is, according to the exemplary embodiment of the present application, the first electrode 152 and the second electrode 154 may be formed to have a sufficient overlap region 156 so that the passive element 150 may have sufficient capacitance. have. As a result, within the total area occupied by the semiconductor package 100, the area where the capacitor is disposed can be sufficiently secured.

In another embodiment, the passive element 150 may be applied as a wireless antenna. Although not shown, the antennas may be arranged to have a sufficient length in each separate plane. Thereby, the area | region in which the said antenna is arrange | positioned can be fully ensured within the total area which the semiconductor package 100 occupies.

The second insulator layer 170 may be disposed on the second electrode 154 of the passive element 150. The connection pads 180 may be disposed on the second insulator layer 170, and the bump structures 190 may be disposed on the connection pads 180. The bump structure 190 may be disposed to electrically connect the semiconductor package 100 to another substrate. Although not shown, the connection pad 180 may be electrically connected to the package substrate 110 or the semiconductor chip 120.

In some embodiments, the second insulator layer 170 may be omitted. When the passive element 150 is an antenna, the second insulating layer 170 may be omitted, and the second electrode 154 may be exposed to the outside. In this case, the electrode pad 180 may be disposed on the first insulator layer 160.

2 is a diagram schematically illustrating a semiconductor package according to another exemplary embodiment of the present application. Specifically, FIG. 2A is a cross-sectional view of a semiconductor package according to one embodiment, and FIG. 2B is a perspective plan view of a semiconductor package according to an embodiment.

Referring to FIG. 2A, the semiconductor package 200 is disposed on the package substrate 210, the conductive plate 215 having a hole pattern, and is mounted inside the hole pattern. Passivation layer 240 for molding at least one semiconductor chip 220, at least one semiconductor chip 220, and conductive plate 215 and a passive element 250 disposed on the passivation layer 240.

The conductive plate 215 serves as a conductive layer defining a region in which the semiconductor chip 220 is to be mounted. In an embodiment, the conductive plate 215 may be formed to surround the region where the semiconductor chip 220 is to be mounted, as shown in the plan view shown in FIG. 11 to be described later. The conductive plate 215 may have, for example, a shape having a hole pattern therein and an outer edge thereof integrally connected to each other, such as a known embedded ground plane (hereinafter referred to as EGP). The conductive plate 215 may be made of a metal material, and as an example, may include copper, aluminum, or the like. The height of the conductive plate 215 may be lower than the height of the semiconductor chip 220. The conductive plate 215 may be electrically connected to the semiconductor chip 220 through an integrated circuit embedded in the package substrate 210. In some embodiments, unlike the top view shown in FIG. 11, the outer edges of the conductive plate 215 may not be integrally connected. As long as the semiconductor chip 220 performs a function of defining a region in which the semiconductor chip 220 is to be mounted, the outer edge may be discontinuously separated. That is, the outer edge may have a shape in which a plurality of conductive patterns electrically insulated from each other are arranged discontinuously.

At least one semiconductor chip 220 is mounted inside the hole pattern of the conductive plate 215. The semiconductor chip 220 may be connected to a connection pad (not shown) of the package substrate 210 using the bump 225. Alternatively, the semiconductor chip 220 may be connected to a connection pad (not shown) of the package substrate 210 through wire bonding.

The passivation layer 210 is disposed to mold the at least one semiconductor chip 220 and the conductive plate 215, and the at least one via layer 230 is disposed inside the passivation layer 210. The via layer 230 may be disposed on the conductive plate 215 and may electrically connect the passive element 250 and the conductive plate 215.

The passive element 250 is disposed on the passivation layer 240 and is electrically connected to the package substrate 210 through the via layer 230. The passive element 250 may include, for example, an inductor or a capacitor. When the semiconductor chip 220 is a wireless chip, the passive element 250 may include, for example, a radio (RF) antenna or a frequency filter.

As shown, the passive element 250 may be a capacitor including a first electrode 252 and a second electrode 254. The first electrode 252 of the passive element 250 is electrically connected to any one of the plurality of via layers 230 and is disposed on one surface of the passivation layer 240. The first insulator layer 260 is disposed on the first electrode 252. The second electrode 254 of the passive element 250 is disposed on the first insulator layer 260, and the second electrode 254 is electrically connected to another one of the plurality of via layers 230. When the passive element 250 is a capacitor, the first insulator layer 260 may function as a dielectric layer of the capacitor. As such, the first electrode 252 and the second electrode 254 of the passive element 250 are disposed on different planes and electrically insulated from each other by the first insulator layer 260. Referring to FIGS. 2A and 2B, the first electrode 252 and the second electrode 254 of the passive element 250 are designed to have a sufficient area on the plane where they are disposed. The first electrode 252 and the second electrode may have a region 256 overlapping each other, and may have a capacitance defined by the area of the overlapping region 256. That is, according to the exemplary embodiment of the present application, in the passive element 250 as a capacitor, each of the first electrode 252 and the second electrode 254 has a sufficient overlap region 256 so as to have a sufficient overlap region 256. Can be placed. Therefore, the area in which the capacitor is disposed can be sufficiently secured within the total area occupied by the semiconductor package 200. In another embodiment, the passive element 250 may be applied as a wireless antenna. Although not shown, the antennas may be arranged to have a sufficient length in each separate plane. Thereby, the area in which the said antenna is arrange | positioned can be ensured within the total area which the semiconductor package 200 occupies.

The second insulator layer 270 may be disposed on the second electrode 254 of the passive element 250. A bump structure 290 may be disposed on an opposite surface of the surface of the package substrate 210 on which the semiconductor chip 220 is mounted. The bump structure 290 may be disposed to electrically connect the semiconductor package 200 to another external substrate. Although not shown, the connection pad 280 may be electrically connected to the passive element 250 or the semiconductor chip 220. In some embodiments, the second insulator layer 270 may be omitted. When the passive element 250 is an antenna, the second insulating layer 270 may be omitted, and the second electrode 254 may be exposed to the outside. In this case, the electrode pad 280 may be disposed on the first insulator layer 260.

3 is a schematic view of a semiconductor package according to another embodiment of the present application. The semiconductor package 300 illustrated in FIG. 3 may have the semiconductor package of FIG. 2 except that the separate package substrate 210 is not applied under the at least one semiconductor chip 320 and the conductive plate 215. Substantially the same as 200). Therefore, detailed description of the same components will be omitted to exclude the duplication.

At least one semiconductor chip 320 is provided, and a conductive plate 215 is disposed along an outer portion of the at least one semiconductor chip 320. As in the embodiment of FIG. 2, at least one semiconductor chip 320 is disposed in a hole pattern provided in the conductive plate 215.

The passivation layer 240 molds the at least one semiconductor chip 320, the conductive plate 215, and the at least one via layer 215. The passive element is disposed on the passivation layer 240.

As illustrated, the redistribution layer 370 and the third insulating layer 360 are disposed under the at least one semiconductor chip 320 and the conductive plate 215. A connection pad 380 electrically connected to the redistribution layer 370 is disposed in the fourth insulating layer 370. The connection structure 290 is disposed on the connection pad 380.

As described above, the semiconductor package according to the embodiments of the present application includes a passive element disposed on the passivation layer for embedding the semiconductor chip. In the related art, a passive device manufactured separately and introduced into a package substrate may be disposed by continuously manufacturing the passivation layer forming process in a package process. As a result, the semiconductor package can be miniaturized and thinned.

In addition, the area of the upper surface of the passivation layer can thereby be sufficiently used for the passive element. That is, each electrode layer of the passive element may be disposed on a separate plane on the passivation layer. Thus, in the case of a passive element, that is, a capacitor, sufficient capacitance can be obtained, and in the case of an inductor, sufficient inductance can be secured. For example, when applied to a wireless chip package, it is possible to easily implement a frequency filter, EMC, a wireless antenna, etc. in a reduced package area and volume than conventional.

Hereinafter, a method of manufacturing a semiconductor package according to an embodiment of the present application will be described.

4 is a flowchart schematically illustrating a method of manufacturing a semiconductor package according to an embodiment of the present application. Referring to FIG. 4, a package substrate including an integrated circuit is provided at block 410. In block 420, at least one via layer is formed on the package substrate. The via layer may be formed by, for example, an electroplating method. In block 430, a semiconductor chip is mounted on the package substrate. In block 340, a passivation layer forming the via layer and the semiconductor chip is formed. In block 450, a passive element is formed on the passivation layer. The passive element may include, for example, an inductor or a capacitor. When the semiconductor chip is a wireless chip, the passive element may include, for example, a radio (RF) antenna or a frequency filter. According to an embodiment, the first electrode and the second electrode of the passive element may be formed on the passivation layer by sputtering or plating. The first electrode and the second electrode may be formed on different planes. In some embodiments, a bump structure may be formed on the passive device.

5 to 9 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor package according to an embodiment of the present application. Referring to FIG. 5, a package substrate 110 and a semiconductor chip 120 are prepared. The package substrate 110 may include an integrated circuit. The package substrate 110 may include a chip die of the active device or may be the chip die of the active device itself. The semiconductor chip 120 may include bumps 125 on one surface thereof.

Referring to FIG. 6, at least one via layer 130 is formed on the package substrate 110. According to an embodiment, the via layer 130 may be formed by an electroplating method. Although not shown, the method of forming the via layer 130 may first deposit a seed metal layer on the package substrate 110. The seed metal layer may include, for example, titanium, titanium nitride, tungsten, or copper. The seed metal layer may be formed of a single layer or a multilayer structure. Then, a resist pattern is formed on the seed metal layer. An electroplating method fills the inside of the resist pattern with a copper layer to form a via layer. After the via layer is formed, the resist pattern is removed. The resist pattern is removed to etch away the exposed seed metal layer exposed to the lower portion. As a result, the via layer 130 may be formed on the package substrate 110.

Referring back to FIG. 6, the semiconductor chip 120 is mounted on the package substrate 110. The semiconductor chip 120 may be mounted on the package substrate 110 by bonding the bumps 125 of the semiconductor chip 120 to predetermined pads disposed on the package substrate 110.

Referring to FIG. 7, the passivation layer 140 may be formed to mold the via layer 130 and the semiconductor chip 120. The passivation layer 140 may be made of an electrically insulating material. For example, the passivation layer 140 may include an insulating resin. The passivation layer 140 may be formed using a known coating method or a deposition method. In an embodiment, after the passivation layer 140 is formed, the planarization operation may be further performed so that the height of the passivation layer 140 matches the height of the via layer 130.

Referring to FIG. 8, a passive element is formed on the passivation layer 140. In one embodiment, the passive element may include a first electrode 152 and a second electrode 154. Referring to the drawings, first, a first electrode 152 electrically connected to any one of the plurality of via layers 130 is formed. At the same time, the trench pattern layer 152-1 is formed to be electrically connected to another one of the plurality of via layers 130. As an example, the first electrode 152 and the trench pattern layer 152-1 may be formed by applying a process of depositing and patterning a copper layer by a sputtering method or a process of depositing a copper layer by an electroplating method.

 As an example, when the passive element is a capacitor, the area of the first electrode 152 may be determined based on the capacitance of the capacitor. As another example, when the passive element is an antenna, the length of the first electrode 152 may be determined based on a transmission / reception function of the antenna.

Referring to FIG. 9, a first insulating layer 160 is formed on the first electrode 152 and the trench pattern layer 152-1. The first insulating layer 160 may be formed using a known coating method or a deposition method. When the passive element is a capacitor, the first insulating layer 160 may function as a dielectric layer of the capacitor. The dielectric material or thickness of the first insulating layer 160 may be determined based on the capacitance of the capacitor. The second electrode 154 of the passive element, which is electrically connected to the trench pattern layer 152-1, is formed in and on the first insulating layer. As an example, the second electrode 154 may be formed by applying a deposition and patterning process of a copper layer by a sputtering method or a formation process of a copper layer pattern by an electroplating method. Specifically, the first insulating layer 160 is selectively etched to form a contact hole exposing the trench pattern layer 152-1, and a copper layer is formed on the upper surface of the contact hole and the first insulating layer 160. By forming, the second electrode 154 can be formed. In some other embodiments, the trench pattern layer 152-1 may not be formed at the same time as the first electrode 152. In this case, the first insulating layer 160 is selectively etched to form a contact hole directly exposing the lower via layer 130, and a copper layer is formed on the upper surface of the contact hole and the first insulating layer 160. By forming, the second electrode 154 can be formed.

When the passive element formed on the passivation layer 140 is a capacitor, the area of the second electrode 154 may be determined based on the capacitance of the capacitor. As another example, when the passive element is an antenna, the length of the second electrode 154 may be determined based on a transmission / reception function of the antenna.

Referring back to FIG. 9, a second insulating layer 170 may be formed on the second electrode 154. The second insulating layer 170 may be formed using a known coating method or a deposition method. The connection pad 180 may be formed on the second insulator layer 170. Although not shown, the connection pad 180 may be formed to be electrically connected to the integrated circuit of the package substrate 110. The bump structure 190 may be formed on the connection pad 180. The process of forming the bump structure 190 may use a known bump forming method.

In some embodiments, the process of forming the second insulator layer 170 may be omitted. When the passive element 150 is an antenna, the second electrode 154 may be formed to be exposed to the outside without the second insulating layer 170. In this case, the electrode pad 180 may be formed on the first insulator layer 160.

10 is a flowchart schematically illustrating a method of manufacturing a semiconductor package according to an embodiment of the present application. Referring to FIG. 10, a substrate for packaging is provided in a 1010 block. The substrate may be a package substrate including an integrated circuit or a carrier substrate to assist packaging. In block 1020, a conductive plate having a hole pattern is formed on the package substrate. As an example, the conductive plate may be manufactured separately and disposed on the package substrate. The conductive plate, the conductive plate may be made of a metal material, for example, may include copper, aluminum and the like. In block 1030, at least one semiconductor chip is disposed in the hole pattern of the conductive plate. In block 1040, a passivation layer is formed to mold the semiconductor chip and the conductive plate. In block 1050, at least one via layer is formed through the passivation layer and connected with the conductive plate. As an example, the at least one via layer may be formed on the conductive plate. The via layer may be formed by, for example, an electroplating method. In block 1060, a passive element is formed on the passivation layer that is electrically connected to the conductive plate through the via layer. The passive element may include, for example, an inductor or a capacitor. When the semiconductor chip is a wireless chip, the passive element may include, for example, a radio (RF) antenna or a frequency filter. According to an embodiment, the first electrode and the second electrode of the passive element may be formed on the passivation layer by sputtering or plating. The first electrode and the second electrode may be formed on different planes. In some embodiments, a bump structure may be formed on a surface opposite to the one surface of the package substrate on which the semiconductor chip is mounted. As a result, a semiconductor package substantially the same as the semiconductor package 100 illustrated in FIG. 1 may be formed.

11 to 17 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor package according to another embodiment of the present application. Referring to FIGS. 11A and 11B, a package substrate 210 is provided. The package substrate 210 may include an integrated circuit (not shown).

Referring to FIGS. 12A and 12B, a conductive plate 215 including a hole pattern 1215 is formed on the package substrate 210. The conductive plate 215 serves as a conductive layer defining the area where the semiconductor chip will be mounted. In one embodiment, the conductive plate 215 may be formed in a shape surrounding the area where the semiconductor chip is to be mounted. In one embodiment, the conductive plate 215 may be manufactured separately in a shape having a hole pattern 1215 therein and having an outer edge connected thereto, such as a known embedded ground plane (EPG). have. The conductive plate 215 may be formed of a metal material and may include, for example, copper or aluminum. The height of the conductive plate 215 may be manufactured to be lower than the height of the semiconductor chip to be mounted. As such, the conductive plate 215, which is separately manufactured, may be bonded to a predetermined region of the package substrate 210, thereby forming the conductive plate 215 on the package substrate 210. In some other embodiments, the conductive plate 215 may be formed on the package substrate 210 by applying known deposition and patterning methods.

In the drawing, the outer edge of the conductive plate 215 is formed in a rectangular shape integrally connected, but in some embodiments, the outer edge of the conductive plate 215 is formed to be physically separated into at least two or more parts. Can be. In this case, the outer edge of the conductive plate 215 may have a shape in which a plurality of conductive patterns electrically insulated from each other are disposed discontinuously. The shape of the conductive plate 215 may be formed in various shapes as long as it satisfies a requirement for defining a mounting area of the semiconductor chip in the hole pattern 1215 therein.

Referring to FIGS. 13A and 13B, at least one semiconductor chip 220 is mounted inside the hole pattern 1215 of the conductive plate 215. The semiconductor chip 220 may be mounted on the package substrate 210 by bonding the bump 225 of the semiconductor chip 220 to a predetermined pad disposed on the package substrate 210.

Referring to FIG. 14, a passivation layer 240 molding the semiconductor chip 220 and the conductive plate 215 is formed on the package substrate 210. The passivation layer 240 may be made of an electrically insulating material. For example, the passivation layer 240 may include an insulating resin. The passivation layer 240 may be formed using a known coating method or a deposition method. In an embodiment, after the passivation layer 240 is formed, the planarization operation may be further performed so that the height of the passivation layer 240 matches the height of the via layer 230.

Referring to FIG. 15, a passive element is formed on the passivation layer 240. According to an embodiment, the passive element may include a first electrode 252 and a second electrode 254. Referring to the drawings, first, at least one via layer 230 connected to the conductive plate 215 is formed through the passivation layer 240. According to one embodiment, the passivation layer 240 is selectively patterned to form a via hole pattern exposing the conductive plate 215. Then, the via hole pattern is filled with a copper film using a plating method or a printing method. The plating method may be, for example, an electroplating method or a chemical plating method. The printing method may be a screen printing method, an inkjet printing method, or the like. As a result, at least one via layer 230 may be formed.

The passive element may be formed on the passivation layer 240 to be electrically connected to the conductive plate 215 through at least one via layer 230. Specifically, first, a first electrode 252 electrically connected to any one of the plurality of via layers 230 is formed. At the same time, the trench pattern layer 252-1 that is electrically connected to another one of the plurality of via layers 230 is formed. For example, the first electrode 252 and the trench pattern layer 252-1 may be formed by applying a deposition and patterning process of a copper layer by a sputtering method or a formation process of a copper layer pattern by an electroplating method. As an example, when the passive element is a capacitor element, the area of the first electrode 252 may be determined based on the capacitance of the capacitor element. As another example, when the passive element is an antenna, the length of the first electrode 252 may be determined based on a transmission / reception function of the antenna.

Referring to FIG. 15 again, a first insulating layer 260 is formed on the first electrode 252 and the trench pattern layer 252-1. When the passive element is a capacitor element, the first insulating layer 260 may function as a dielectric layer of the capacitor element. The dielectric material or thickness of the first insulating layer 260 may be determined based on the capacitance of the capacitor device.

Referring to FIG. 16, a second electrode 254 of the passive element electrically connected to the trench pattern layer 252-1 is formed on the first insulating layer 260. As an example, the second electrode 254 may be formed by applying a deposition and patterning process of a copper layer by a sputtering method or a deposition process of a copper layer by an electroplating method. Specifically, the first insulating layer 260 is selectively etched to form a contact hole exposing the trench pattern layer 252-1, and a copper layer is formed on the upper surface of the contact hole and the first insulating layer 260. By forming, the second electrode 254 can be formed.

In some other embodiments, the trench pattern layer 252-1 may not be formed at the same time as the first electrode 252. In this case, the first insulating layer 260 is selectively etched to form a contact hole directly exposing the lower via layer 230, and a copper layer is formed on the upper surface of the contact hole and the first insulating layer 260. By forming, the second electrode 254 can be formed.

When the passive element formed on the passivation layer 240 is a capacitor element, the area of the second electrode 254 may be determined based on the capacitance of the capacitor element. As another example, when the passive element is an antenna, the length of the second electrode 254 may be determined based on a transmission / reception function of the antenna. Referring again to FIG. 16, a second on the second electrode 254 may be determined. The insulating layer 270 may be formed. The second insulating layer 270 may be formed using a known coating method or a deposition method. In some embodiments, the process of forming the second insulator layer 270 may be omitted. When the passive element 250 is an antenna, the second electrode 254 may be formed to be exposed to the outside without the second insulating layer 270.

Referring to FIG. 17, a connection pad 280 may be formed on a surface opposite to the one surface of the package substrate 210 on which the semiconductor chip 220 is mounted. Although not shown, the connection pad 280 may be formed to be electrically connected to the integrated circuit of the package substrate 210. The bump structure 290 may be formed on the connection pad 280. The process of forming the bump structure 290 may use a known bump forming method. As a result, a semiconductor package substantially the same as the semiconductor package 200 illustrated in FIG. 2 may be formed.

18 to 24 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor package according to another embodiment of the present application. Referring to FIGS. 18A and 18B, a carrier substrate 310 including an adhesive layer 312 on one surface is prepared.

Referring to FIG. 19, a conductive plate 215 having a hole pattern 1215 is formed on the adhesive layer 312 of the carrier substrate 310. A conductive plate 215 having a hole pattern 1215 defining a position of the semiconductor chip is separately manufactured, and the conductive plate 215 is attached onto the adhesive layer 312.

Referring to FIGS. 20A and 20B, at least one semiconductor chip 220 is disposed in the hole pattern 1215 of the conductive plate 215. The semiconductor chip 220 may be disposed by bonding the semiconductor chip 220 onto the adhesive layer 312 of the carrier substrate 310.

Referring to FIG. 21, a passivation layer 240 molding the semiconductor chip 220 and the conductive plate 215 is formed on the package substrate 210. Then, a passive element is formed on the passivation layer 240. A process of forming the via layer 230, the first electrode 252, the trench pattern layer 252-1, the second electrode 254, the first insulating layer 260, and the second insulating layer 270 is illustrated in FIG. It is substantially the same as in the above-described embodiment with reference to FIG. 15 and FIG. 16.

Referring to FIG. 22, after the passive element is formed on the passivation layer 240, a structure including the passive element, the conductive plate 215, and the semiconductor chip 320 and the carrier substrate 310 are separated from each other. . Specifically, the carrier substrate 310 is peeled from the structure at an interface between one surface of the passivation layer 240 and the carrier substrate 310 of the adhesive layer 312.

Referring to FIG. 23, a third insulating layer pattern 360 for forming a redistribution layer is formed on one surface of the separated passivation layer 240. The third insulating layer pattern 360 may be formed of a photosensitive resist pattern.

Referring to FIG. 24, the redistribution pattern 370 is formed using the third insulating layer pattern 360. The redistribution pattern 370 may be formed by, for example, a plating method or a printing method. The plating method may be, for example, an electroplating method or a chemical plating method. The printing method may be, for example, a screen printing method or an inkjet printing method. The fourth insulating layer 390 is formed on the redistribution pattern 370. The fourth insulating layer 390 is partially patterned to sequentially form a connection pad 380 and a bump structure 290 electrically connected to a portion of the redistribution pattern 370. As a result, a semiconductor package substantially the same as the semiconductor package 300 illustrated in FIG. 3 may be formed.

According to the manufacturing method of the embodiments of the present application as described above, the passive element can be formed on the upper surface of the passivation layer for embedding the semiconductor chip. In the related art, a passive device, which is manufactured separately and introduced into a package substrate, may be continuously manufactured after the passivation layer forming process in a package process. As a result, the process can be simplified, and the semiconductor package can be made smaller and thinner.

In addition, the area of the upper surface of the passivation layer can thereby be sufficiently used for the passive element manufacture. That is, on the upper portion of the passivation layer, each electrode layer of the passive element can be formed on a separate plane. Thus, in the case of a passive element, that is, a capacitor, sufficient capacitance can be obtained, and in the case of an inductor, sufficient inductance can be secured. Thus, for example, when applied to a wireless chip package, it is possible to easily implement a frequency filter, EMC, wireless antenna, etc. in a reduced package area and volume than in the prior art.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It can be understood that

Reference Signs List 100: semiconductor package, 110: package substrate, 120: semiconductor chip, 125: bump, 130: via layer, 140: passivation layer, 150: passive element, 152: first electrode of passive element, 152-1: trench pattern layer 154: second electrode of the passive element, 156: region where the first electrode and the second electrode overlap, 160: first insulator layer, 170: second insulator layer, 180: connection pad, 190: bump structure,
200: semiconductor package, 210: package substrate, 215: conductive plate, 220: semiconductor chip, 225: bump, 230: via layer, 240: passivation layer, 250: passive element, 252: first electrode of passive element, 252- DESCRIPTION OF SYMBOLS 1 Trench pattern layer, 254: 2nd electrode of a passive element, 256: 1st electrode and 2nd electrode overlapping area | region, 260: 1st insulator layer, 270: 2nd insulator layer, 280: connection pad, 290: Bump structure, 1215: hole pattern.

Claims (21)

A package substrate;
A semiconductor chip mounted on the package substrate;
A passivation layer molding the semiconductor chip on the package substrate; And
A passive element electrically connected to the package substrate through a via layer formed through the passivation layer and disposed on the passivation layer,
The first electrode and the second electrode of the passive element are disposed on different planes above the passivation layer.
Semiconductor package. The method according to claim 1,
And the package substrate comprises a chip die of an active device or the package substrate is a chip die of an active device. The method according to claim 1,
The passive device includes a semiconductor package including an inductor or a capacitor. The method according to claim 1,
The passive element comprises a radio (RF) antenna or a frequency filter. The method according to claim 1,
The at least one via layer is disposed in the passivation layer, and the via layer electrically connects the first and second electrodes of the passive element and the package substrate. The method according to claim 1,
Further comprising a bump structure disposed on top of the passivation layer in which the passive element is disposed
Semiconductor package. At least one semiconductor chip;
A conductive plate disposed along an outer portion of the semiconductor chip;
A passivation layer molding the semiconductor chip and the conductive plate;
A passive element disposed on the passivation layer and electrically connected to the conductive plate through at least one via layer formed in the passivation layer,
The first electrode and the second electrode of the passive element are disposed on different planes
Semiconductor package. The method of claim 7, wherein
The passive device includes a semiconductor package including an inductor or a capacitor. The method of claim 7, wherein
The passive element includes a semiconductor filter or an antenna of an RF device. The method of claim 7, wherein
The at least one semiconductor chip is disposed in the hole pattern provided in the conductive plate. The method of claim 7, wherein
The via layer is disposed on the conductive plate. The method of claim 7, wherein
And a redistribution pattern and a bump structure disposed on the opposite side of the surface of the package substrate. In the manufacturing method of a semiconductor package,
(a) providing a package substrate comprising an integrated circuit;
(b) forming at least one via layer on the package substrate;
(c) mounting a semiconductor chip on the package substrate;
(d) forming a passivation layer for molding the via layer and the semiconductor chip; And
(e) forming a passive element on the passivation layer,
The first electrode and the second electrode of the passive element are formed on different planes above the passivation layer.
Method of manufacturing a semiconductor package. The method of claim 13,
(e) step
(e1) forming a first electrode layer of the passive element electrically connected to any one of the via layers on the passivation layer;
(e2) forming an insulating layer on the first electrode layer; And
(e3) forming a second electrode layer of the passive element electrically connected to the other of the via layers on the insulating layer;
Method of manufacturing a semiconductor package. 15. The method of claim 14,
Steps (e1) and (e3)
Depositing and patterning a copper layer by sputtering or depositing a copper layer by electroplating
Method of manufacturing a semiconductor package. The method of claim 13,
step (b)
(b1) depositing a seed metal layer on the package substrate;
(b2) forming a resist pattern on the seed metal layer;
(b3) forming a via layer by filling the inside of the resist pattern with a copper layer by an electroplating method; And
(b4) removing the resist pattern and etching the exposed seed metal layer. The method of claim 13,
And forming a bump structure on top of the passivation layer on which the passive element is disposed.
Method of manufacturing a semiconductor package. In the manufacturing method of a semiconductor package,
(a) providing a substrate for packaging;
(b) forming a conductive plate having a hole pattern on the substrate;
(c) disposing at least one semiconductor chip inside the hole pattern of the conductive plate;
(d) forming a passivation layer for molding the semiconductor chip and the conductive plate;
(e) forming at least one via layer through the passivation layer to connect with the conductive plate;
(f) forming a passive element on the passivation layer that is electrically connected with the conductive plate through the via layer;
The first electrode and the second electrode of the passive element are formed on different planes above the passivation layer.
Method of manufacturing a semiconductor package. 19. The method of claim 18,
step (f)
(f1) forming a first electrode layer of the passive element electrically connected to any one of the via layers on the passivation layer;
(f2) forming an insulating layer on the first electrode layer; And
(f3) forming a second electrode layer of the passive element on the insulating layer that is electrically connected to the other of the via layers.
Method of manufacturing a semiconductor package. 19. The method of claim 18,
(e) step
(e1) selectively etching the passivation layer to form a via hole pattern exposing the conductive plate; And
(e2) filling the via hole pattern with a copper film by plating or printing;
Method of manufacturing a semiconductor package. 19. The method of claim 18,
After the passive element is formed on the passivation layer, a structure including the passive element, the conductive plate, and the semiconductor chip and the substrate are separated from each other at an interface between one surface of the passivation layer and the substrate. Making a step;
Forming a redistribution layer on the one surface of the separated passivation layer; And
And forming a connection pad and a bump structure on a portion of the redistribution layer.
Method of manufacturing a semiconductor package.

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