KR20130072854A - Semiconductor memory system - Google Patents

Semiconductor memory system Download PDF

Info

Publication number
KR20130072854A
KR20130072854A KR1020110140459A KR20110140459A KR20130072854A KR 20130072854 A KR20130072854 A KR 20130072854A KR 1020110140459 A KR1020110140459 A KR 1020110140459A KR 20110140459 A KR20110140459 A KR 20110140459A KR 20130072854 A KR20130072854 A KR 20130072854A
Authority
KR
South Korea
Prior art keywords
test
pattern
controller
data storage
storage unit
Prior art date
Application number
KR1020110140459A
Other languages
Korean (ko)
Inventor
양형균
이형동
권용기
문영석
김성욱
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110140459A priority Critical patent/KR20130072854A/en
Publication of KR20130072854A publication Critical patent/KR20130072854A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

Abstract

PURPOSE: A semiconductor memory system is provided to improve the reliability of the semiconductor memory system by performing tests of each component and a connection state. CONSTITUTION: Multiple semiconductor memories are laminated in a data storage unit. An interposer connects a logic die (40-1) and a controller. The controller is arranged on the interposer and controls the data storage unit. The logic die is connected to the data storage unit. The logic die generates a test pattern, outputs the test pattern to the data storage unit according to a test mode or to the controller through the interposer, receives a return pattern signal outputted from the data storage unit or the controller, and compares the test pattern and the return pattern signal. [Reference numerals] (41) Test patter generator; (42) Output selector; (43) Input selector; (44,45) Receiver for memory; (46) Transmitter for controller; (47) Receiver for controller; (48) Comparator

Description

Semiconductor Memory System

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor memory system.

FIG. 1 illustrates a system in package, which is one of the general semiconductor memory systems. The system in package includes a circuit board 10, an interposer 20, a controller 30, and a logic die 40. ), And a data storage unit 50.

The circuit board 10 is configured to be a substrate of a system in package.

The interposer 20 is disposed on the circuit board 10.

The controller 30 is disposed on the interposer 20.

The logic die 40 is disposed on the interposer 20.

The data store 50 is disposed on the logic die 40.

The interposer 20 is configured to transfer a signal between the controller 30 and the logic die 40.

The logic die 30 is configured to transfer a signal between the interposer 20 and the data storage 50.

The data storage unit 50 may have a configuration in which a plurality of memories are stacked.

As described above, in a general system-in-package, the components are stacked on each other, so that package balls of the components do not protrude to the outside, so a probing test, that is, a pin of a test device Can not be tested to contact the package ball. Therefore, in a package that is a general system, it is not possible to test each configuration and test connection status.

The present invention provides a semiconductor memory system capable of performing a test and a connection state test of each component of the semiconductor memory system.

In an embodiment, a semiconductor memory system includes a data storage unit in which a plurality of semiconductor memories are stacked, a controller for controlling the data storage unit, a logic die connected to the data storage unit, and the logic. An interposer connecting between a die and the controller, wherein the logic die generates a test pattern and outputs the test pattern to the data storage unit or to the controller through the interposer according to a test mode. And receiving a return pattern signal output from the data storage unit or the controller, and comparing the test pattern with the return pattern signal.

The semiconductor memory system according to the embodiment of the present invention can perform the test of each component and the connection state test to increase the reliability of the semiconductor memory system.

1 is a block diagram illustrating a general semiconductor memory system;
2 is a block diagram of a logic die according to an embodiment of the present invention.

As disclosed in FIG. 1, a semiconductor memory system according to an embodiment of the present invention may include a circuit board 10, an interposer 20, a controller 30, a logic die 40, and data. The storage unit 50 may be included.

The circuit board 10 is configured to be a substrate of a system in package.

The interposer 20 is disposed on the circuit board 10.

The controller 30 is disposed on the interposer 20 and controls the data storage unit 50.

The logic die 40 is disposed on the interposer 20.

The data store 50 is disposed on the logic die 40.

The interposer 20 is configured to transfer a signal between the controller 30 and the logic die 40.

The logic die 40 is configured to transfer a signal between the interposer 20 and the data storage 50.

The data storage unit 50 may have a configuration in which a plurality of memories are stacked.

Replacing the logic die 40 shown in FIG. 1 with the logic die 40-1 according to the embodiment of the present invention shown in FIG. 2 results in a semiconductor memory system according to the present invention.

The logic die 40-1 constituting the semiconductor memory system according to an exemplary embodiment of the present invention generates a test pattern Test_pt during a test, and stores the test pattern Test_pt according to a test mode in the data storage unit 50. Output to the controller 30 through the interposer 20. In addition, the logic die 40-1 receives the return pattern signals int_test_pt_re and ext_test_pt_re output from the data storage unit 50 or the controller 30. The test pattern Test_pt and the return pattern signal ( int_test_pt_re, ext_test_pt_re). In this case, the return pattern signals int_test_pt_re and ext_test_pt_re include an internal test return pattern int_test_pt_re output from the data storage unit 50 and an external test return pattern ext_test_pt_re output from the controller 30.

The logic die 40-1 may include, for example, a test pattern generator 41, an output selector 42, an input selector 43, a memory transmitter 44, a memory receiver 45, and a controller. A transmitter 46 and a controller receiver 47. In this case, the circuit board 10 may further include a join test action group (JTAG) circuit 10-1.

The test pattern generator 41 generates the test pattern Test_pt. For example, the test pattern generator 41 may generate the test pattern Test_pt in response to an output signal of the JTAG circuit 10-1. In this case, the test pattern Test_pt may be a signal that changes every time the clock transitions.

The output selector 42 receives the test pattern Test_pt and stores it as a first storage pattern store_pt1, and stores the first storage pattern store_pt1 according to a test mode signal Test_mode as an internal test pattern int_test_pt. ) Or as an external test pattern (ext_test_pt). For example, when the test mode signal Test_mode is enabled, the output selector 42 stores the test pattern Test_pt as the first storage pattern store_pt1, and at the same time, the first storage pattern store_pt1. ) Is output to the controller transmitter 46 as the external test pattern ext_test_pt. In addition, when the test mode signal Test_mode is disabled, the output selector 42 stores the test pattern Test_pt as the first storage pattern store_pt1, and simultaneously stores the first storage pattern store_pt1. The internal test pattern (int_test_pt) is outputted to the memory transmitter 44. The output selector 42 receives a flip-flop for receiving and storing the test pattern Test_pt and the output of the flip-flop in response to the test mode signal Test_mode. Alternatively, the controller may be implemented as a de-multiplexer for selectively outputting to the controller transmitter 46.

The memory transmitter 44 transmits the internal test pattern int_test_pt to the data storage unit 50 (see FIG. 1).

The controller transmitter 46 transmits the external test pattern ext_test_pt to the controller 30 through the interposer 20 (see FIG. 1).

The memory receiving unit 45 receives the output signal of the data storage unit 50 and outputs it as an internal test return pattern int_test_pt_re.

The controller receiving unit 47 receives an output signal of the controller 30 input through the interposer 20 and outputs the output signal as an external test return pattern ext_test_pt_re.

The input selector 43 receives and stores the internal test return pattern int_test_pt_re or the external test return pattern ext_test_pt_re according to the test mode signal Test_mode, and stores the stored signal as a second storage pattern store_pt2. Output For example, when the test mode signal Test_mode is enabled, the input selector 43 receives and stores the external test return pattern ext_test_pt_re and outputs the stored signal as the second storage pattern store_pt2. do. In addition, when the test mode signal Test_mode is disabled, the input selector 43 receives and stores the internal test return pattern int_test_pt_re and outputs the stored signal as the second storage pattern store_pt2. The input selector 43 selects the external test return pattern ext_test_pt_re or the internal test return pattern int_test_pt_re in response to the test mode signal Test_mode and receives the selected multiplexer. It can be implemented as a flip-flop that stores the input signal.

The comparison unit 48 compares the first storage pattern store_pt1 and the second storage pattern store_pt2 and outputs a result signal. For example, the comparison unit 48 enables the result signal when the first storage pattern store_pt1 and the second store pattern store_pt2 are the same, and otherwise, the result signal result. Disable it.

The semiconductor memory system according to the embodiment of the present invention configured as described above operates as follows.

When the logic die 40 and the controller 30 are tested, the test mode signal Test_mode is enabled and a test pattern Test_pt is generated in the test pattern generator 41 using a JTAG circuit.

Since the test mode signal Test_mode is enabled, the output selector 42 stores the test pattern Test_pt as the first storage pattern store_pt1 and simultaneously outputs the external test pattern ext_test_pt.

The controller transmitter 46 transmits the external test pattern ext_test_pt to the controller 30 through the interposer 20.

The transceiver 30 of the controller 30 receives the external test pattern ext_test_pt and outputs it to the logic die 40 through the interposer 20 again.

The controller receiver 47 receives an output signal of the controller 30 input through the interposer 20 and outputs the output signal as an external test return pattern ext_test_pt_re.

Since the test mode signal Test_mode is enabled, the input selector 43 receives the external test return pattern ext_test_pt_re and stores and outputs it as a second storage pattern store_pt2.

The comparator 48 compares the first storage pattern store_pt1 and the second storage pattern store_pt2 to determine whether they are the same.

When the test mode signal Test_mode is enabled, it may be tested whether the controller 30 and the logic die 40 are well connected through the interposer 20.

When the logic die 40 and the data storage unit 50 are tested, the test mode signal Test_mode is disabled and a test pattern Test_pt is generated in the test pattern generator 41 using a JTAG circuit. .

Since the test mode signal Test_mode is enabled, the output selector 42 stores the test pattern Test_pt as the first storage pattern store_pt1 and simultaneously outputs the internal test pattern int_test_pt.

The memory transmitter 44 transmits the internal test pattern int_test_pt to the data storage 50.

The transceiver of the data storage unit 50 receives the internal test pattern int_test_pt and outputs it to the logic die 40 again.

The memory receiving unit 45 receives the output signal of the data storage unit 50 and outputs it as an internal test return pattern int_test_pt_re.

Since the test mode signal Test_mode is disabled, the input selector 43 receives the internal test return pattern int_test_pt_re and stores and outputs it as a second storage pattern store_pt2.

The comparison unit 48 compares the first storage pattern store_pt1 and the second storage pattern store_pt2 to determine whether they are the same.

When the test mode signal Test_mode is disabled, the data storage unit 50 and the logic die 40 may be tested for good connection.

Therefore, the semiconductor memory system according to the embodiment of the present invention can perform the test of each component and the connection state test to increase the reliability of the semiconductor memory system.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

Claims (5)

A data storage unit in which a plurality of semiconductor memories are stacked;
A controller for controlling the data storage;
A logic die connected to the data storage unit; And
An interposer connecting between the logic die and the controller,
The logic die generates a test pattern, outputs the test pattern to the data storage unit or the controller through the interposer according to a test mode, and outputs a return pattern signal output from the data storage unit or the controller. And receiving the input and comparing the test pattern with the return pattern signal. The method of claim 1,
The logic die
A test pattern generator which generates the test pattern;
An output selection unit which receives the test pattern and stores the first test pattern as a first storage pattern and outputs the first storage pattern as an internal test pattern or an external test pattern according to the test mode;
A memory transmitter for transmitting the internal test pattern to the data storage unit;
A controller transmitter configured to transmit the external test pattern to the controller through the interposer;
A memory receiving unit which receives an output signal of the data storage unit and outputs it as an internal test return pattern;
A controller receiving unit for receiving an output signal of the controller input through the interposer and outputting the output signal as an external test return pattern;
An input selector configured to receive and store the internal test return pattern or the external test return pattern according to the test mode, and output the stored signal as a second storage pattern;
And a comparator for comparing the first storage pattern with the second storage pattern and outputting a resultant signal. 3. The method of claim 2,
Further includes a test setting circuit,
The test setting circuit is characterized in that the JTAG (Joint Test Action Group) circuit,
And the test pattern generation unit generates the test pattern in response to an output signal of the test setting circuit. The method of claim 1,
The test pattern is
A semiconductor memory system, characterized in that the signal changes in level every time the clock transitions. 3. The method of claim 2,
The comparing unit
And determining whether the first storage pattern is the same as the second storage pattern.
KR1020110140459A 2011-12-22 2011-12-22 Semiconductor memory system KR20130072854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110140459A KR20130072854A (en) 2011-12-22 2011-12-22 Semiconductor memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110140459A KR20130072854A (en) 2011-12-22 2011-12-22 Semiconductor memory system

Publications (1)

Publication Number Publication Date
KR20130072854A true KR20130072854A (en) 2013-07-02

Family

ID=48987427

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110140459A KR20130072854A (en) 2011-12-22 2011-12-22 Semiconductor memory system

Country Status (1)

Country Link
KR (1) KR20130072854A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9140743B2 (en) 2014-01-16 2015-09-22 SK Hynix Inc. Semiconductor system that tests the connectivity between a metal and a bump that are formed in the upper portion of a penetrating electrode
US11393549B2 (en) 2020-03-20 2022-07-19 SK Hynix Inc. Memory device and memory system including test control signal generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9140743B2 (en) 2014-01-16 2015-09-22 SK Hynix Inc. Semiconductor system that tests the connectivity between a metal and a bump that are formed in the upper portion of a penetrating electrode
US11393549B2 (en) 2020-03-20 2022-07-19 SK Hynix Inc. Memory device and memory system including test control signal generating circuit

Similar Documents

Publication Publication Date Title
US9406401B2 (en) 3-D memory and built-in self-test circuit thereof
KR102066661B1 (en) Integrated circuit for reconstructing values of flip-flops connected scan-chain using jtag interface, method thereof, and devices having same
US9881693B2 (en) Selectors on interface die for memory device
US8607103B2 (en) Transmission/reception device, transmission device, reception device, and data transmission/reception method
KR20150097074A (en) Test circuit and semiconductor apparatus including the same
US9135132B2 (en) Method of testing a device under test, device under test, and semiconductor test system including the device under test
US9229057B2 (en) Pattern synthesis apparatus and semiconductor test system having the same
US10262753B2 (en) Auxiliary test device, test board having the same, and test method thereof
US20060179373A1 (en) Device and method for JTAG test
TWI660183B (en) Component inspection method, probe card, interposer and inspection device
US20130207685A1 (en) Semiconductor integrated circuit
JP2014085348A5 (en)
US9998350B2 (en) Testing device and testing method
CN101923897A (en) SIC (semiconductor integrated circuit) and the method for testing that is used for SIC (semiconductor integrated circuit)
KR101959894B1 (en) Semiconductor integrated circuit and method of measuring internal voltage thereof
CN106291313B (en) Method and apparatus for testing integrated circuits
US9043662B2 (en) Double data rate memory physical interface high speed testing using self checking loopback
US20080104458A1 (en) Semiconductor memory, system, testing method for system
KR20130072854A (en) Semiconductor memory system
KR20160006542A (en) Stacked semiconductor package
US20080028104A1 (en) Semiconductor device and operation control method of semiconductor device
CN106896317B (en) Circuit debugging method and circuit debugging system executed by scan chain of scan test
KR100898029B1 (en) Apparatus for testing semiconductor and method thereof
CN108155979B (en) Detection equipment
KR20140026182A (en) Semiconductor memory apparatus

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination