KR20130072009A - Semiconductor memory device and operating method thereof - Google Patents

Semiconductor memory device and operating method thereof Download PDF

Info

Publication number
KR20130072009A
KR20130072009A KR1020110139547A KR20110139547A KR20130072009A KR 20130072009 A KR20130072009 A KR 20130072009A KR 1020110139547 A KR1020110139547 A KR 1020110139547A KR 20110139547 A KR20110139547 A KR 20110139547A KR 20130072009 A KR20130072009 A KR 20130072009A
Authority
KR
South Korea
Prior art keywords
memory cell
cell array
dummy
normal
word line
Prior art date
Application number
KR1020110139547A
Other languages
Korean (ko)
Inventor
원형식
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110139547A priority Critical patent/KR20130072009A/en
Publication of KR20130072009A publication Critical patent/KR20130072009A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Landscapes

  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: Semiconductor memory device and driving method thereof are provided to improve reliability of data by detecting an undesired connection state between neighboring memory cell arrays and by reinforcing the connection state. CONSTITUTION: A normal memory cell array (210) is accessed in response to an external address. A dummy memory cell array (220) has a dummy word line and stores data scheduled in a memory cell of its own in a test mode. A dummy word line control unit (240) controls activation of the dummy word line in a test mode. A data analysis unit (260) analyzes data stored in the normal memory cell array and data stored in the dummy memory cell array and detects a state of the normal memory cell array. [Reference numerals] (230) Normal word line control unit; (240) Dummy word line control unit; (260) Data analysis unit

Description

Semiconductor memory device and driving method therefor {SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device in which memory cells for storing data are arranged in an array form.

Generally, semiconductor memory devices, including DDR Double Data Rate Synchronous DRAM (SDRAM), have more than tens of millions of memory cells for storing data. Memory cells are regularly arranged in a memory region inside a semiconductor memory device to form a memory cell array. Such a set of memory cell arrays is called a "memory cell mat". Here, the memory cell array includes word lines corresponding to the plurality of memory cells as well as the plurality of memory cells.

1 is a block diagram illustrating a memory area of a conventional semiconductor memory device.

Referring to FIG. 1, a semiconductor memory device includes a plurality of memory cell mats, and the first and second memory cell mats 110 and 120 are representatively illustrated for convenience of description. Subsequently, a sense amplifier 130 is disposed between the plurality of memory cell mats.

Hereinafter, a first memory cell mat 110 of a plurality of memory cell mats will be described as a representative.

The first memory cell mat 110 includes a normal memory cell array 111 and a dummy memory cell array 112. The normal memory cell array 111 refers to a memory cell array accessed by an externally input address, and the dummy memory cell array 112 refers to a memory cell array additionally disposed to protect the normal memory cell array 111. do. As shown in the figure, the dummy memory cell array 112 is disposed at the edge of the normal memory cell array 111 and is not used at all in the normal operation or the test operation.

Meanwhile, as the degree of integration of semiconductor memory devices develops, the spacing between memory cell arrays provided in a plurality of memory cell mats also decreases. The reduced spacing between the memory cell arrays means that adjacent memory cell arrays can be connected undesirably. If the adjacent memory cell arrays are undesiredly connected, the semiconductor memory device may not perform a stable data storage operation, which may cause a decrease in data reliability.

It is an object of the present invention to provide a semiconductor memory device capable of detecting an unwanted connection state between adjacent memory cell arrays.

According to an aspect of the present invention, a semiconductor memory device includes a normal memory cell array accessed in response to an external address; A dummy memory cell array having a dummy word line and configured to store predetermined data in its memory cell in a test mode; And a dummy word line controller for controlling whether the dummy word line is activated in a test mode.

Preferably, the apparatus further includes a redundant memory cell array for replacing a defective memory cell array among the normal memory cell arrays.

According to another aspect of the present invention, a method of operating a semiconductor memory device includes a normal memory cell array and a dummy memory cell array, wherein the predetermined data is stored in the normal memory cell array in a test operation mode. Making; Activating a dummy word line of the dummy memory cell array disposed adjacent to the normal memory cell array; Storing test data corresponding to data stored in the normal memory cell array in the dummy word line; And analyzing the data stored in the normal memory cell array and the data stored in the dummy memory cell array to detect a state of the normal memory cell array.

The test data may include data having a polarity opposite to that stored in the normal memory cell array.

According to another aspect of the present invention, a semiconductor memory device is a semiconductor memory device having a plurality of memory cell mat having an open bit line structure, disposed in the memory cell mat, the data is stored in the normal mode and the test mode A normal memory cell array; And first and second dummy memory cell arrays disposed at edges of the memory cell mat and activated in the test mode to store predetermined data and deactivated in the normal mode.

The memory device may further include a third dummy memory cell array which is inactivated in the test mode, wherein the third dummy memory cell is disposed at an edge of a memory cell mat including the first and second dummy memory cell arrays. It is done.

The semiconductor memory device according to an embodiment of the present invention can detect and reinforce unwanted connection states between adjacent memory cell arrays.

By detecting and reinforcing an unwanted connection state between adjacent memory cell arrays, an effect of increasing the reliability of data stored in the memory cell array may be obtained.

1 is a block diagram illustrating a memory area of a conventional semiconductor memory device.
2 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to an embodiment of the present invention.
3 is a block diagram illustrating a memory region configuration of a semiconductor memory device having an open bit line structure.
4 is a block diagram illustrating a semiconductor memory device having an open bit line structure according to an embodiment of the present invention.
FIG. 5 is a diagram for describing the circuit operation of FIG. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

FIG. 2 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to an exemplary embodiment of the present invention. For the convenience of description, one memory cell mat 250 is represented.

Referring to FIG. 2, the memory cell mat 250 is disposed near the normal memory cell array 210 and the normal memory cell array 210 accessed by the address ADD, and the test signal TM is activated in the test mode. A dummy memory cell array 220 in which predetermined data is stored. The normal memory cell array 210 and the dummy memory cell array 220 include normal word lines WL1 and WL2 and dummy word lines DWL1 and DWL2, respectively. Here, whether the normal word lines WL1 and WL2 of the normal memory cell array 210 are activated by the normal word line controller 230 receiving the address ADD is controlled, and the dummy of the dummy memory cell array 220 The word lines DWL1 and DWL2 are controlled by the dummy word line controller 240 receiving the test signal TM. The data analyzer 260 analyzes data stored in the memory cell mat 250 to detect a state of the normal memory cell array.

In FIG. 2, the dummy memory cell array 220 is disposed at an upper edge of the memory cell mat 250 as an example. It also includes disposed at the bottom edge of the mat (250).

In the case of the conventional semiconductor memory device, the dummy memory cell array 112 (refer to FIG. 1) is used only as a protective film for protecting the normal memory cell array 111 and no other application is used. However, in the semiconductor memory device according to the exemplary embodiment of the present invention, the dummy memory cell array 220 may be used to detect an unwanted connection state between the memory cell arrays in the test mode. In other words, for example, when the normal memory cell array corresponding to the first normal word line WL1 and the dummy memory cell array corresponding to the second dummy word line DWL2 are undesirably connected, a conventional method of detecting the same may be used. There was no. However, the semiconductor memory device according to the embodiment of the present invention can detect the same through the following operations.

Hereinafter, a test operation of a semiconductor memory device according to an embodiment of the present invention will be described.

First, the test data is stored in the memory cell arrays corresponding to the first and second normal word lines WL1 and WL2 in the test mode. Thereafter, the second dummy word line DWL2 is activated, and test data corresponding to data stored in the normal memory cell array is stored in the dummy memory cell array corresponding to the second dummy word line DWL2. For example, assuming that data stored in the normal memory cell array corresponding to the first normal word line WL1 is logic 'high', the dummy memory cell array corresponding to the second dummy word line WL2 may be connected to the normal memory cell array. The logic 'low', which is data of opposite polarity to the stored data, may be stored. The data analyzer 260 of the semiconductor memory device according to an exemplary embodiment of the present invention may store data stored in the normal memory cell array corresponding to the first normal word line WL1 and the second dummy word line DWL2 through the above operation. The state of the normal memory cell array is detected by analyzing data stored in the dummy memory cell array corresponding to the data array.

In addition, the first dummy word line DWL1 may be in an inactive state during a test operation, thereby protecting the dummy memory cell array corresponding to the second dummy word line DWL2, and thus, the dummy memory cell array may perform a desired operation. It is possible. Subsequently, the first and second dummy word lines DWL1 and DWL2 are inactivated during the normal operation to protect the normal memory cell array corresponding to the first normal word line WL1.

The semiconductor memory device may be divided into a folded bit line structure and an open bit line structure according to a memory cell structure.

First, a folded bit line structure is a bit line on which data is driven based on a sense amplifier disposed in a memory area of a semiconductor memory device (hereinafter referred to as a 'drive bit line'). (Eg, referred to as a 'reference bit line') are disposed in the same memory cell mat. Therefore, since the same noise is reflected in the driving bit line and the reference bit line, and these noises cancel each other, the folded bit line structure ensures stable operation against noise. In the open bit line structure, the driving bit line and the reference bit line are disposed on different memory cell mats based on the sense amplifier. Therefore, noise generated in the driving bit line and noise generated in the reference bit line are different from each other, and therefore, the open bit line structure is poor in such noise.

Subsequently, in the folded bit line structure, the unit memory cell structure is designed as 8F2, and in the open bit line structure, the unit memory cell structure is designed as 6F2. This unit memory cell structure is an element that determines the size of the semiconductor memory device. When comparing the same data storage amount, a semiconductor memory device having an open bit line structure may be designed to be smaller than a semiconductor memory device having a folded bit line structure.

The semiconductor memory device according to the embodiment of the present invention can be applied to both a semiconductor memory device having a folded bit line structure and a semiconductor memory device having an open bit line structure.

Hereinafter, an embodiment of the present invention is applied to a semiconductor memory device having an open bit line structure, and the memory cell array structure of the open bit line will be described in detail.

The semiconductor memory device stores data or outputs data according to a command required by an external controller. That is, when a data access operation is requested by an external controller, a data access operation is performed in a memory area as a word line corresponding to a row address is activated and a memory cell corresponding to a column address input thereafter is selected. Here, the number of word lines may vary for each semiconductor memory device, but generally corresponds to the number of address bits. That is, when the address bit is m (where m is a natural number), the number of word lines is designed to correspond to 2 m . Considering that the memory cell mat has a predetermined number, the number of word lines corresponding to one memory cell mat is designed to be 256, 512, etc., which can be represented by 2 m .

The description so far is for folded bit line structures and the open bit line structure is slightly different.

As described above, since the open bit line structure is inferior to noise, considering the operating margin of the sense amplifier, noise, and design efficiency, the number of word lines included in the memory cell mat of the open bit line structure is a folded bit. It is less than the number of word lines provided in the memory cell mat of the line structure. That is, the number of word lines corresponding to one memory cell mat is greater than the number that can be represented by 2 n-1 (where n is a natural number) and smaller than the number that can be represented by 2 n . 420 and so on. Accordingly, the open bit line structure inevitably causes an additional memory cell array when compared to the folded bit line structure, which is referred to as a 'spare memory cell array'.

3 is a block diagram illustrating a memory region configuration of a semiconductor memory device having an open bit line structure. For convenience of explanation, a semiconductor memory device having a normal word line of 8K is taken as an example.

Referring to FIG. 3, a semiconductor memory device having an open bit line structure includes first to twenty-second memory cell mats 310 and a sense amplifier 320. An array of 8K normal memory cells and a dummy memory cell array for protecting the same are disposed in the first to twenty-second memory cell mats 310, and the spare memory cell array described above is disposed. In general, a spare memory cell array is used as a redundant memory cell array for repairing a defective memory cell.

4 is a block diagram illustrating a semiconductor memory device having an open bit line structure according to an embodiment of the present invention. For convenience of description, one memory cell mat 410 of the plurality of memory cell mats will be described as a representative.

Referring to FIG. 4, the memory cell mat 410 may include a normal memory cell array 411 corresponding to the first and second normal word lines WL1 and WL2, and first to third dummy word lines DWL1 and DWL2. The dummy memory cell array 412 corresponding to DWL3 is disposed. As can be seen, the dummy memory cell array 412 is disposed at the edge of the memory cell mat 412.

First, the normal memory cell array 411 stores desired data in the normal mode and the test mode. In addition, the dummy memory cell array 412 is inactivated in the normal mode and activated in the test mode to store predetermined data. The normal word line controller 420 controls whether a plurality of normal word lines including the first and second normal word lines WL1 and WL2 are activated in response to the address ADD, and the dummy word line controller 430 is activated. In response to the test signal TM, controls whether the first to third dummy word lines DWL1, DWL2, and DWL3 are activated. Finally, the data analyzer 440 analyzes data stored in the memory cell mat 410 to detect a state of the normal memory cell array.

4 illustrates an example in which the dummy memory cell array 412 is disposed at an upper edge of the memory cell mat 410. However, in the semiconductor memory device according to the exemplary embodiment of the present invention, the dummy memory cell array 412 is a memory cell. It also includes disposed at the bottom edge of the mat (410).

In the exemplary embodiment of the present invention, the memory cell arrays corresponding to the first and second dummy word lines DWL1 and DWL2 are activated in the test mode to store test data. The reason for performing this operation is as follows.

FIG. 5 is a diagram for describing the circuit operation of FIG. 4.

FIG. 5 illustrates the first and second normal word lines WL1 and WL2 and the first to third dummy word lines DWL1, DWL2 and DWL3 of FIG. 4, and memory cell arrays corresponding to the respective word lines. Is shown.

Hereinafter, a test operation of a semiconductor memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4 and 5.

First, predetermined test data is stored in a memory cell array corresponding to the first normal word line WL1 in the test mode. That is, predetermined test data is stored in the '0' memory cell of FIG. 5. Thereafter, the first and second dummy word lines DWL1 and DWL2 are activated, and predetermined test data is stored in the dummy memory cell arrays corresponding to the first and second dummy word lines DWL1 and DWL2. That is, predetermined data is stored in the memory cells '1', '2', '3', and '4' of FIG. 5. For example, if logic 'high' is stored in memory cell '0', logic 'low' is stored in memory cells '1', '2', '3' and '4'.

As shown in FIG. 5, the '0' memory cell corresponding to the first normal word line WL1 is disposed adjacent to the '1', '2', '3', and '4' memory cells in the open bit line structure. In the embodiment of the present invention, since it is possible to store predetermined test data in memory cells '1', '2', '3', and '4', the memory cells '0' and '1', '2' It is possible to detect an unwanted connection state of a dummy memory cell array comprising '3', '4' memory cells.

Subsequently, the data analyzer 440 of the semiconductor memory device according to an exemplary embodiment of the present invention may store data and first and second dummy data stored in the normal memory cell array corresponding to the first normal word line WL1 through the above operation. The state of the normal memory cell array is detected by analyzing data stored in the dummy memory cell arrays corresponding to the word lines DWL1 and DWL2.

In addition, the third dummy word line DWL3 may be maintained in an inactive state during a test operation, thereby protecting the dummy memory cell array corresponding to the first dummy word line DWL1 so that the dummy memory cell array may perform a desired operation. It is possible. Subsequently, the first to third dummy word lines DWL1, DWL2, and DWL3 are inactivated during a normal operation to protect the normal memory cell array corresponding to the first normal word line WL1.

On the other hand, methods for detecting unwanted connection states between adjacent memory cell arrays may vary. In embodiments of the present invention, for example, the voltage level of data stored in a '0' memory cell may be detected to prevent unwanted connection between adjacent memory cell arrays. It is possible to detect the connection state.

As described above, the semiconductor memory device according to the embodiment of the present invention is capable of detecting an unwanted connection state between adjacent memory cell arrays. Therefore, the detection result can be reinforced for unwanted connection, which can increase the reliability of data stored in the memory cell array.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

210: normal memory cell array 220: dummy memory cell array
230: normal word line control unit 240: dummy word line control unit
250: memory cell mat 260: data analysis unit

Claims (21)

A normal memory cell array accessed in response to an external address;
A dummy memory cell array having a dummy word line and configured to store predetermined data in its memory cell in a test mode; And
Dummy word line controller for controlling whether the dummy word line is activated in a test mode
And the semiconductor memory device.
The method of claim 1,
And a redundancy memory cell array for replacing the defective memory cell array among the normal memory cell arrays.
The method of claim 1,
And a data analyzer configured to analyze data stored in the normal memory cell array and data stored in the dummy memory cell array to detect a state of the normal memory cell array.
The method of claim 1,
And a normal word line controller configured to control whether a normal word line of the normal memory cell array is activated in response to the external address.
The method of claim 1,
And the dummy memory cell array is inactivated in a normal mode.
The method of claim 1,
The dummy memory cell array,
A first dummy memory cell array inactivated in the test mode; And
And a second dummy memory cell array in which predetermined data is stored in the test mode.
The method according to claim 6,
And the second dummy memory cell array is disposed between the first dummy memory cell array and the normal memory cell array.
The method of claim 1,
And the dummy memory cell array is disposed at an edge of a memory cell mat including the normal memory cell array.
The method of claim 1,
And the dummy memory cell array is disposed adjacent to the normal memory cell array.
The method of claim 1,
And the predetermined data stored in the dummy memory cell array includes data having a polarity opposite to that stored in the normal memory cell array.
In the method of operating a semiconductor memory device comprising a normal memory cell array and a dummy memory cell array,
Storing predetermined data in the normal memory cell array in a test mode of operation;
Activating a dummy word line of the dummy memory cell array disposed adjacent to the normal memory cell array;
Storing test data corresponding to data stored in the normal memory cell array in the dummy word line; And
Detecting a state of the normal memory cell array by analyzing data stored in the normal memory cell array and data stored in the dummy memory cell array
Wherein the semiconductor memory device is a semiconductor memory device.
The method of claim 11,
And the dummy memory cell array is disposed at an edge of a memory cell mat including the normal memory cell array.
The method of claim 11,
And the test data includes data of opposite polarity to data stored in the normal memory cell array.
The method of claim 11,
And the dummy memory cell array is disposed separately from a redundant memory cell array for replacing a defective memory cell array among the normal memory cell arrays.
In a semiconductor memory device having a plurality of memory cell mat having an open bit line structure,
A normal memory cell array disposed in the memory cell mat and storing data in a normal mode and a test mode; And
First and second dummy memory cell arrays disposed at edges of the memory cell mat and activated in the test mode to store predetermined data and deactivated in the normal mode
And the semiconductor memory device.
16. The method of claim 15,
The first and second dummy memory cell arrays each include a dummy word line, and further comprising a dummy word line controller for controlling whether the dummy word line is activated in the test mode.
16. The method of claim 15,
And a redundancy memory cell array for replacing the defective memory cell array among the normal memory cell arrays.
16. The method of claim 15,
And a data analyzer configured to analyze data stored in the normal memory cell array and data stored in the first and second dummy memory cell arrays to detect the normal memory cell array state.
16. The method of claim 15,
And the data stored in the first and second dummy memory cell arrays have polarities opposite to those stored in the normal memory cell array.
16. The method of claim 15,
And a third dummy memory cell array deactivated in the test mode, wherein the third dummy memory cell is disposed at an edge of a memory cell mat including the first and second dummy memory cell arrays. Memory device.
21. The method of claim 20,
And the third dummy memory cell array is inactivated in a normal mode.
KR1020110139547A 2011-12-21 2011-12-21 Semiconductor memory device and operating method thereof KR20130072009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110139547A KR20130072009A (en) 2011-12-21 2011-12-21 Semiconductor memory device and operating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110139547A KR20130072009A (en) 2011-12-21 2011-12-21 Semiconductor memory device and operating method thereof

Publications (1)

Publication Number Publication Date
KR20130072009A true KR20130072009A (en) 2013-07-01

Family

ID=48986864

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110139547A KR20130072009A (en) 2011-12-21 2011-12-21 Semiconductor memory device and operating method thereof

Country Status (1)

Country Link
KR (1) KR20130072009A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150118486A (en) * 2014-04-14 2015-10-22 삼성전자주식회사 Memory device, memory system and operating method of memory device
US10510429B2 (en) 2017-10-27 2019-12-17 Samsung Electronics Co., Ltd. Memory device performing test on memory cell array and method of operating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150118486A (en) * 2014-04-14 2015-10-22 삼성전자주식회사 Memory device, memory system and operating method of memory device
US10510429B2 (en) 2017-10-27 2019-12-17 Samsung Electronics Co., Ltd. Memory device performing test on memory cell array and method of operating the same

Similar Documents

Publication Publication Date Title
EP3154060B1 (en) Apparatuses and methods for targeted refreshing of memory
US7975170B2 (en) Memory refresh system and method
US7613060B2 (en) Methods, circuits, and systems to select memory regions
KR102405054B1 (en) Memory device and method for operating memory device
KR20140002928A (en) Cell array and memory device including the same
US10453549B2 (en) Memory device including virtual fail generator and memory cell repair method thereof
KR20160132243A (en) Semiconductor memory device
KR101343557B1 (en) Semiconductor device and method for test the same
US8913451B2 (en) Memory device and test method thereof
KR102420897B1 (en) Memory module, memory system inculding the same, and operation method thereof
JP2016024837A (en) Semiconductor device
CN103456369B (en) Repair control circuit and the semiconductor integrated circuit using repair control circuit
KR20130072009A (en) Semiconductor memory device and operating method thereof
US9607718B2 (en) Semiconductor memory device and test operation method thereof
US9589668B2 (en) Semiconductor memory device for performing test operation of circuits related to repair scheme and operating method thereof
US20050259485A1 (en) Apparatus and method for testing a memory device
US9064605B2 (en) Semiconductor system and method for reparing the same
US20160064062A1 (en) Semiconductor memory device and refresh operating method
KR102122821B1 (en) Repair analyzing system based on fault information storage table and repair analyzing method thereof
KR102384769B1 (en) Semiconductor device
US10297304B1 (en) Memory device and operating method thereof
KR102345541B1 (en) Memory device including redundancy column and redundancy peripheral logic
US9761329B2 (en) Built-in self-test (BIST) circuit and associated BIST method for embedded memories
US11183261B2 (en) Test device for memory, method for detecting hardware failure in memory device, and test apparatus of memory array
KR20230162371A (en) Memory system and test method of memory system

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application