In a clocked system, it is very important that the duty of the clock is accurately controlled. The duty of the clock refers to the ratio of the high pulse width to the low pulse width of the clock. In particular, DDR (Double Data Rate) synchronous memory devices use a clock to strobe data, two bits in succession during one clock period in synchronization with the rising and falling edges of the clock. Since the data of I / O is inputted / outputted, if the duty of the clock does not maintain 50%, the margin of data is not secured and the input / output data may be distorted.
On the other hand, the clock is generated in an external clock generator and transferred to an internal circuit using a transmission line. In this case, the 'high' and 'low' pulse widths of the clock are different due to mismatches of the clock generator, external noise introduced during the transmission process, and amplitude attenuation of the electrical signal on the transmission line. The duty of is very likely to be distorted. To solve this problem, a duty corrector circuit (DCC) is used to correct the duty.
1 is a diagram illustrating a conventional duty correction circuit.
The duty cycle correction circuit illustrated in FIG. 1 includes a duty cycle corrector 10, a phase separator 20, and a duty detector 30.
The duty cycle corrector 10 corrects the duty of the input clock ICLK in response to the duty control code CODE <0: N> to generate the output clock DCLK. Specifically, the duty cycle corrector 10 may be designed to increase / decrease the high pulse width of the input clock ICLK step by step when the duty control code CODE <0: N> increases / decreases step by step.
The phase separator 20 divides the output clock DCLK output from the duty compensator 10 into a rising clock RCLK and a falling clock FCLK. The rising clock RCLK is a clock that is activated 'high' in the 'high' section of the output clock DCLK, and the polling clock FCLK is a clock that is activated 'high' in the 'low' section of the output clock DCLK. to be.
The duty detector 30 detects the duty by comparing the size of the activation period of the rising clock RCLK and the activation period of the falling clock FCLK, and detects the duty according to the result. The duty control code CODE <0: N> The output is adjusted to the duty cycle corrector 10. In detail, the duty detector 30 up-counts the duty control code CODE <0: N> when the high pulse width of the rising clock RCLK is smaller than the high pulse width of the falling clock FCLK, and conversely rises. If the high pulse width of the clock RCLK is wider than the high pulse width of the falling clock FCLK, it may be designed to down count the duty control code CODE <0: N>. When the high pulse width of the rising clock RCLK and the high pulse width of the falling clock FCLK are the same, the duty detector 30 does not change the duty control code CODE <0: N> and locks the lock. Can be designed to On the other hand, if the difference between the high pulse width of the rising clock RCLK and the high pulse width of the falling clock FCLK is less than or equal to a predetermined value, the high pulse width of the rising clock RCLK and the high pulse width of the falling clock FCLK will be described below. Is considered to be the same.
FIG. 2 is a timing diagram illustrating a duty correction operation of the conventional duty correction circuit shown in FIG. 1. For convenience of explanation, it is assumed that the high pulse width of the input clock ICLK is reduced by ΔD1 due to noise introduced during the transmission process, such that the high pulse width is narrower than the low pulse width. And (2) when the duty control code CODE <0: N> increases / decreases step by step, it is assumed that the duty correction unit 10 is designed to increase / decrease the high pulse width of the input clock ICLK step by step. , ③ The duty detector 30 up-counts the duty control code CODE <0: N> if the high pulse width of the rising clock RCLK is smaller than the high pulse width of the falling clock FCLK, and vice versa. If the high pulse width of RCLK is wider than the high pulse width of the falling clock FCLK, it is assumed that the duty control code CODE <0: N> is designed to down count.
When the input clock ICLK whose duty is misaligned is input to the duty cycle corrector 10, the duty cycle corrector 10 is in response to the duty control code CODE <0: N> having an initial value. Generate an output clock DCLK with the same phase. Therefore, the high pulse width of the output clock DCLK is 2 * ΔD1 narrower than the low pulse width.
The phase separator 20 divides the output clock DCLK into a rising clock RCLK and a falling clock FCLK. At this time, the high pulse width of the rising clock RCLK is 2 * ΔD1 narrower than the high pulse width of the falling clock FCLK.
When the rising clock RCLK and the falling clock FCLK are input to the duty detector 30, the duty detector 30 compares the high pulse width of the rising clock RCLK with the high pulse width of the falling clock FCLK. The duty control code CODE <0: N> is adjusted according to the comparison result. That is, the duty detector 30 up-counts the duty control code CODE <0: N> because the high pulse width of the rising clock RCLK is narrower than the high pulse width of the falling clock FCLK. Output as (10).
The duty cycle corrector 10 corrects the duty of the input clock ICLK in response to the input duty control codes CODE <0: N>. That is, the duty cycle corrector 10 increases the high pulse width of the input clock ICLK in response to the up counted duty control code CODE <0: N> to generate the output clock DCLK.
The above process is performed until the output clock DCLK generated by the duty compensator 10 is input to the phase separator 20 again, and the high pulse width and the low pulse width of the output clock DCLK are the same. Is repeated.
When the high pulse width and the low pulse width of the output clock DCLK are the same (that is, when the high pulse width of the rising clock RCLK and the high pulse width of the falling clock FCLK are the same), the duty detector 30 The duty control code CODE <0: N> is locked so that the duty control code CODE <0: N> is no longer changed.
As a result, when the duty cycle correction is completed, as shown in FIG. 2, the output clock DCLK having the same high pulse width and low pulse width is output from the duty cycle corrector 10.
However, the output clock DCLK output from the conventional duty compensating circuit passes through internal circuits, such as a control circuit and a driver, which are located behind the duty compensating circuit, so that the duty of the output clock DCLK may be shifted again. As a result, the circuit that finally uses the output clock DCLK (hereinafter referred to as a “target circuit”) uses a clock having a different duty, and thus has a problem in that data margins are not secured as described above.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.
3 is a diagram illustrating a duty cycle correction circuit according to an exemplary embodiment of the present invention.
The duty cycle correction circuit may include a first duty cycle corrector 100, a second duty cycle corrector 200, and a duty detection circuit 300.
The first duty compensator 100 corrects the duty of the input clock ICLK in response to the first code CODE1 <0: N> to generate the output clock DCLK. That is, the duty of the input clock ICLK may be distorted due to external noise, attenuation of the amplitude of the signal, etc. while the input clock ICLK is transmitted to the first duty compensator 100. The step 100 corrects the duty distortion of this input clock ICLK occurring in the front of the duty cycle correction circuit in response to the first code CODE1 <0: N>. Hereinafter, for convenience of description, the duty distortion of the clock generated at the front end of the duty cycle correction circuit is referred to as 'first duty distortion'.
Meanwhile, the first duty compensator 100 adjusts the duty by adjusting a slew rate of the input clock ICLK or a method of correcting the duty by increasing or decreasing the overall voltage level of the input clock ICLK. It can be designed in a variety of ways. For example, the first duty compensator 100 is designed to correct the duty of the input clock ICLK by adjusting the overall voltage level of the input clock ICLK in response to the first code CODE1 <0: N>. In this case, when the overall voltage level of the input clock ICLK increases in response to the first code CODE1 <0: N>, the high pulse width of the input clock ICLK increases (low pulse width decreases), and conversely, When the overall voltage level of the input clock ICLK is lowered in response to one code CODE1 <0: N>, the high pulse width of the input clock ICLK is reduced (the low pulse width is increased).
The first duty compensator 100 is designed to correct the duty of the input clock ICLK by adjusting the slew rate of the input clock ICLK in response to the first code CODE1 <0: N>. In this case, when the slew rate of the input clock ICLK increases in response to the first code CODE1 <0: N>, the high pulse width of the input clock ICLK increases (low pulse width decreases), and conversely, the first When the slew rate of the input clock ICLK decreases in response to the code CODE1 <0: N>, the high pulse width of the input clock ICLK is reduced (the low pulse width is increased).
Meanwhile, when the first code CODE1 <0: N> increases / decreases step by step, the first duty compensator 100 may be designed to increase / decrease the high pulse width of the input clock ICLK step by step. have. Alternatively, the first duty compensator 100 may be designed to increase / decrease the low pulse width of the input clock ICLK step by step when the first code CODE1 <0: N> is gradually increased / decreased. have.
The second duty compensator 200 corrects the duty of the output clock DCLK in response to the second code CODE2 <0: N> to generate the feedback clock FBCLK. In detail, the second duty compensator 200 may be designed to increase / decrease the high pulse width of the output clock DCLK in response to the second code CODE2 <0: N>. Alternatively, the second duty compensator 200 may be designed to increase / decrease the low pulse width of the output clock DCLK in response to the second code CODE2 <0: N>. Here, the second code CODE2 <0: N> is a code generated in response to the duty change of the output clock DCLK and may be an externally input code. In detail, even if the output clock DCLK is corrected to 50% duty by the duty correction circuit, noise and a signal that flows through the internal circuits such as a driver and a control circuit that exist after the duty correction circuit are present. The duty of the output clock DCLK may be shifted again due to amplitude attenuation or the like. The second code CODE2 <0: N> may be an external input code generated by reflecting such a change in the duty of the output clock DCLK generated after the duty cycle correction circuit. Hereinafter, for convenience of description, the duty distortion of the clock generated after the duty cycle correction circuit is referred to as a 'second duty distortion'.
The second duty compensator 200 adjusts the slew rate of the output clock DCLK like the first duty compensator 100 described above to correct the duty or the overall voltage level of the output clock DCLK. It can be designed in various ways, such as by increasing or decreasing the value to compensate for the duty. The second duty compensator 200 may be designed to perform a duty compensating operation in response to the mode signal MODE. The mode signal MODE is a signal indicating a correction mode and a normal mode. Specifically, the mode signal MODE indicates a correction mode when the mode signal MODE is at a high level, and the mode signal MODE. If is low level can be designed to indicate the normal mode (normal mode). That is, the second duty compensator 200 performs the above-described duty correction operation in the correction mode (when the mode signal MODE is high level), and in the normal mode (the mode signal MODE is low level). May be designed to not perform a duty correction operation.
The duty detection circuit 300 detects the duty of the feedback clock FBCLK and generates a first code CODE1 <0: N>. In detail, the duty detection circuit 300 may be designed to detect a difference between the high pulse width and the low pulse width of the feedback clock FBCLK and adjust the first code CODE1 <0: N> according to the result. . The duty detection circuit 300 may be designed to perform a duty detection and a first code CODE1 <0: N> generation in response to the mode signal MODE. In detail, the duty detection circuit 300 performs a duty detection and a first code CODE1 <0: N> generation operation in a correction mode (when the mode signal MODE is at a high level), and in a normal mode. (When the mode signal MODE is at a low level), the first code CODE1 <0: N> may be designed to be output without changing.
3 illustrates a case in which the duty detection circuit 300 includes a phase separation unit 310 and a duty detection unit 350 as an embodiment of the duty detection circuit 300 for convenience of description.
The phase separator 310 divides the feedback clock FBCLK output from the second duty compensator 200 into a rising clock FB_RCLK and a falling clock FB_FCLK. Here, the rising clock FB_RCLK is a clock that is activated in the high period of the feedback clock FBCLK, and the falling clock FB_FCLK is a clock that is activated in the low period of the feedback clock FBCLK.
The duty detector 350 compares the magnitude of the high pulse width of the rising clock FB_RCLK and the high pulse width of the falling clock FB_FCLK and adjusts the first code CODE1 <0: N> according to the comparison result. Output to duty correction unit 100. In detail, the duty detector 350 up counts the first code CODE1 <0: N> if the high pulse width of the rising clock FB_RCLK is smaller than the high pulse width of the falling clock FB_FCLK, and conversely, If the high pulse width of the clock FB_RCLK is wider than the high pulse width of the falling clock FB_FCLK, the first code CODE1 <0: N> may be designed to down count. If the high pulse width of the rising clock FB_RCLK and the high pulse width of the falling clock FB_FCLK are the same, the duty detector 350 is designed to lock the first code CODE1 <0: N> without changing it. Can be. The duty detector 350 may be designed to perform a duty detection and a first code CODE1 <0: N> generation in response to the mode signal MODE. In detail, the duty detector 350 performs a duty detection and a first code CODE1 <0: N> generation operation in a correction mode (when the mode signal MODE is at a high level), and in a normal mode. (When the mode signal MODE is at a low level), the first code CODE1 <0: N> may be designed to be output without changing.
The overall operation of the duty cycle correction circuit shown in FIG. 3 will be described.
First, the operation of the duty cycle correction circuit in the normal mode (when the mode signal MODE is at a low level) will be described. In the normal mode (when the mode signal MODE is at a low level), the second duty cycle corrector 200 does not operate. The duty detection circuit 300 outputs the first code CODE1 <0: N> without changing it. The first duty compensator 100 adjusts the duty of the input clock ICLK in response to the fixed first code CODE1 <0: N> to generate the output clock DCLK.
4A and 4B, the duty correction operation of the duty correction circuit shown in FIG. 3 in the correction mode (when the mode signal MODE is at a high level) will be described. In the following description, for convenience of description, the input clock ICLK decreases the high pulse width by ΔD1 due to the first duty distortion, and the high pulse width is narrower than the low pulse width. Assume a case where the high pulse width is reduced by ΔD2. If the first code CODE1 <0: N> is increased / decreased step by step, the first duty compensator 100 increases / decreases the high pulse width of the input clock ICLK step by step, It is assumed that the step 200 is designed to increase / decrease the high pulse width of the output clock DCLK in response to the second code CODE2 <0: N>. If the high pulse width of the rising clock FB_RCLK is smaller than the high pulse width of the falling clock FB_FCLK, the duty detection unit 350 of the duty detection circuit 300 selects the first code CODE1 <0: N>. If the high pulse width of the rising clock FB_RCLK is wider than the high pulse width of the falling clock FB_FCLK, it is assumed that the first code CODE1 <0: N> is down counted.
4A shows that when the second code CODE2 <0: N> is not externally input in the correction mode (when the mode signal MODE is at a high level) (the second duty corrector 200 outputs the output clock DCLK). Is a timing diagram showing the duty correction operation of the duty cycle correction circuit in the case of outputting without the duty cycle).
In the initial duty correction stage, since the first code CODE1 <0: N> input to the first duty cycle corrector 100 has an initial value, the first duty cycle corrector 100 is in phase with the input clock ICLK. This same output clock DCLK is generated. That is, the high pulse width of the output clock DCLK is 2 * ΔD1 narrower than the low pulse width.
The second duty compensator 200 performs a duty compensating operation of the output clock DCLK in response to the high level mode signal MODE. In detail, the second duty compensator 200 corrects the duty of the output clock DCLK in response to the second code CODE2 <0: N>, and the second code CODE2 <0: 2> is external. Since it is not input from, it generates a feedback clock FBCLK in phase with the output clock DCLK. Therefore, the high pulse width of the feedback clock FBCLK is 2 * ΔD1 narrower than the low pulse width.
The phase separator 310 of the duty detection circuit 300 divides the input feedback clock FBCLK into a rising clock FB_RCLK and a falling clock FB_FCLK. The rising clock FB_RCLK has a high pulse pulse width that is 2 * ΔD1 narrower than the low pulse pulse width, and the falling clock FB_FCLK has a high pulse pulse width that is 2 * ΔD1 wider than the low pulse pulse width.
The duty detection unit 350 of the duty detection circuit 300 performs a duty detection of the feedback clock FBCLK and a first code CODE1 <0: N> in response to the high level mode signal MODE. do. Specifically, the duty detector 350 compares the high pulse width of the rising clock FB_RCLK and the high pulse width of the falling clock FB_FCLK and adjusts the first code CODE1 <0: N> according to the result. do. That is, since the high pulse width of the rising clock FB_RCLK is narrower than the high pulse width of the falling clock FB_FCLK, the duty detector 350 up-counts the first code CODE1 <0: N> to generate the first pulse. Output to duty correction unit 100.
When the first code CODE1 <0: N> output from the duty detector 350 is input to the first duty compensator 100, the first duty compensator 100 may count up the first code CODE1. <0: N>) increases the high pulse width of the input clock ICLK to generate the output clock DCLK.
In addition, the output clock DCLK generated by the first duty compensator 100 is input to the second duty compensator 200. The above-described duty compensation process includes a high pulse width and a falling clock of the rising clock FB_RCLK. The high pulse width of FB_FCLK) is repeated until the same.
When the high pulse width of the rising clock FB_RCLK and the high pulse width of the falling clock FB_FCLK are the same, the duty detector 350 locks without changing the first code CODE1 <0: N> any more. do.
As a result, when the duty cycle correction is completed, as shown in FIG. 4A, the high pulse width of the input clock ICLK is adjusted to increase by ΔD1 to generate an output clock DCLK having the same high pulse width and low pulse width.
Now, when the second code CODE2 <0: N> is externally input in the correction mode (when the mode signal MODE is at the high level) together with FIG. 4B, the second duty compensator 200 outputs the output clock ( The duty cycle correcting operation of the duty cycle correction circuit in the case of correcting the duty of DCLK) will be described. For convenience of description, it is assumed that the second code CODE2 <0: N> is generated by reflecting that the high pulse width of the output clock DCLK is reduced by ΔD2 due to the second duty distortion.
In the initial duty correction stage, since the first code CODE1 <0: N> input to the first duty cycle corrector 100 has an initial value, the first duty cycle corrector 100 is in phase with the input clock ICLK. This same output clock DCLK is generated. That is, the high pulse width of the output clock DCLK is 2 * ΔD1 narrower than the low pulse width.
The second duty compensator 200 performs a duty compensating operation of the output clock DCLK in response to the high level mode signal MODE. Specifically, the high pulse width of the output clock DCLK is reduced by ΔD2 in response to the externally input second code CODE2 <0: N>. Therefore, the high pulse width of the feedback clock FBCLK generated by the second duty compensator 200 is 2 * (ΔD1 + ΔD2) narrower than the low pulse width.
When the feedback clock FBCLK is input to the phase separator 310, the phase separator 310 divides the feedback clock FBCLK into a rising clock FB_RCLK and a falling clock FB_FCLK. The high pulse width of the rising clock FB_RCLK is 2 * (ΔD1 + ΔD2) narrower than the low pulse width. The high pulse width of the falling clock FB_FCLK is 2 * (ΔD1 + ΔD2) wider than the low pulse width.
The duty detector 350 performs duty detection of the feedback clock FBCLK and generation of the first code CODE1 <0: N> in response to the high level mode signal MODE. In detail, the duty detector 350 compares the high pulse width of the rising clock FB_RCLK and the high pulse width of the falling clock FB_FCLK and adjusts the first code CODE1 <0: N> according to the result. . As a result, since the high pulse width of the rising clock FB_RCLK is smaller than the high pulse width of the falling clock FB_FCLK, the duty detector 350 up counts the first code CODE1 <0: N> to determine the first duty compensation. Output to the government (100).
When the first code CODE1 <0: N> output from the duty detector 350 is input to the first duty compensator 100, the first duty compensator 100 may be an up counted first code CODE1. <0: N>) increases the high pulse width of the input clock ICLK to generate the output clock DCLK.
The output clock DCLK generated by the first duty compensator 100 is input to the second duty compensator 200 again, and the high pulse width of the rising clock FB_RCLK and the high pulse of the falling clock FB_FCLK are output. The duty correction process described above is repeated until the widths are the same.
When the high pulse width of the rising clock FB_RCLK and the high pulse width of the falling clock FB_FCLK are the same, the duty detector 350 locks without changing the first code CODE1 <0: N> any more. do.
As a result, when the duty cycle correction is completed, as shown in FIG. 4B, the high pulse width of the input clock ICLK is adjusted to increase by (ΔD1 + ΔD2) so that the high pulse width is 2 * ΔD2 wider than the low pulse width. The output clock DCLK is generated.
Therefore, even when a second duty distortion occurs in which the high pulse width of the output clock DCLK is narrowed by ΔD2 while the output clock DCLK is transmitted to the target circuit through a driver, a control circuit, and the like that exist after the duty correction circuit. Since the duty cycle of the input clock ICLK is corrected to generate the output clock DCLK by reflecting the second duty distortion during the duty cycle correction process, the output clock DCLK having a 50% duty is input to the target circuit.
5 is a diagram illustrating a duty cycle correction circuit according to another exemplary embodiment of the present invention.
The duty cycle correction circuit may include a first duty cycle corrector 100, a duty detection circuit 300, and a second duty cycle corrector 250. The duty cycle correcting circuit illustrated in FIG. 5 has the second duty cycle correcting unit 250 positioned at a 'path through which the clock is transmitted to the outside of the duty cycle correcting circuit'. There is a difference from the duty cycle correction circuit shown in FIG. 3 located at the 'feedback path'.
The first duty compensator 100 corrects the duty of the input clock ICLK in response to the first code CODE1 <0: N> to generate the first output clock DCLK1. The first duty compensator 100 is similar in configuration and operation to the first duty compensator 100 described above with reference to FIG. 3.
The duty detection circuit 300 detects the duty of the first output clock DCLK1 and generates a first code CODE1 <0: N>. Specifically, the duty detection circuit 300 is designed to detect a difference between the high pulse width and the low pulse width of the first output clock DCLK1 and adjust the first code CODE1 <0: N> according to the result. Can be. 5 illustrates a case in which the duty detection circuit 300 includes a phase separation unit 310 and a duty detection unit 350 as an embodiment of the duty detection circuit 300 for convenience of description. The duty sensing circuit 300 illustrated in FIG. 5 differs from the sense of detecting the duty of the first output clock DCLK1 instead of the feedback clock FBCLK, and is configured with the duty sensing circuit 300 described above with reference to FIG. 3. The operation is similar.
The second duty compensator 250 corrects the duty of the first output clock DCLK1 in response to the second code CODE2 <0: N> to generate the second output clock DCLK2. In detail, the second duty compensator 250 may be designed to increase / decrease the high pulse width of the first output clock DCLK1 in response to the second code CODE2 <0: N>. Alternatively, the second duty compensator 250 may be designed to increase / decrease the low pulse width of the first output clock DCLK1 in response to the second code CODE2 <0: N>. The second code CODE2 <0: N> is a code generated in response to the duty change of the second output clock DCLK2 and may be an externally input code. Specifically, even when the second output clock DCLK2 is corrected to 50% by the duty correction circuit, the second output clock DCLK2 is subjected to an internal circuit such as a driver, a control circuit, etc., located behind the duty correction circuit, and then the target circuit. The duty of the second output clock DCLK2 may be shifted again due to noise introduced in the process of being transmitted to the signal, attenuation of the amplitude of the signal, and the like. The second code CODE2 <0: N> is a code generated by reflecting such a duty change (= second duty distortion) of the second output clock DCLK2 occurring at the rear end of the duty cycle correction circuit. Can be. Meanwhile, the second duty cycle corrector 250 adjusts the duty by adjusting the slew rate of the first output clock DCLK1 or corrects the duty by increasing or decreasing the overall voltage level of the first output clock DCLK1. It can be designed in a variety of ways.
The overall operation of the duty cycle correction circuit shown in FIG. 5 will be described.
First, the operation of the duty cycle correction circuit in the normal mode (when the mode signal MODE is at the low level) will be described. In the normal mode (when the mode signal MODE is at the low level), the duty detection circuit 300 outputs the first code CODE1 <0: N> without changing it. The first duty compensator 100 adjusts the duty of the input clock ICLK in response to the fixed first code CODE1 <0: N> to generate the first output clock DCLK1. The second duty compensator 250 adjusts the duty of the first output clock DCLK1 in response to the second code CODE2 <0: N> to generate the second output clock DCLK2.
6A and 6B, the duty correction operation of the duty correction circuit shown in Fig. 5 will be described in the case of the correction mode (when the mode signal MODE is at the high level). Hereinafter, for convenience of description, the input clock ICLK has a high pulse width reduced by ΔD1 due to the first duty distortion, and the high pulse width is narrower than the low pulse width, and the second output clock DCLK2 has a second duty. Assume that the high pulse width is reduced by ΔD 2 due to the distortion. If the first code CODE1 <0: N> is increased / decreased step by step, the first duty compensator 100 increases / decreases the high pulse width of the input clock ICLK step by step, It is assumed that the step 250 is designed to increase / decrease the high pulse width of the first output clock DCLK1 in response to the second code CODE2 <0: N>. If the high pulse width of the rising clock FB_RCLK is smaller than the high pulse width of the falling clock FB_FCLK, the duty detection unit 350 of the duty detection circuit 300 selects the first code CODE1 <0: N>. If the high pulse width of the rising clock FB_RCLK is wider than the high pulse width of the falling clock FB_FCLK, it is assumed that the first code CODE1 <0: N> is down counted.
FIG. 6A illustrates that when the second code CODE2 <0: N> is not externally input in the correction mode (when the mode signal MODE is at a high level), the second duty cycle correcting unit 250 outputs the first output clock. Is a timing diagram showing the duty correction operation of the duty cycle correction circuit in the case of outputting without correcting the duty of DCLK1.
In the initial duty correction stage, since the first code CODE1 <0: N> input to the first duty cycle corrector 100 has an initial value, the first duty cycle corrector 100 is in phase with the input clock ICLK. This same first output clock DCLK1 is generated. That is, the high pulse width of the first output clock DCLK1 is 2 * ΔD1 narrower than the low pulse width.
When the first output clock DCLK is input to the second duty compensator 250, since the second code CODE2 <0: N> is not externally input, the second duty compensator 250 is configured to be the first. The second output clock DCLK2 having the same phase as the output clock DCLK1 is generated.
On the other hand, when the first output clock DCLK1 is input to the phase separator 310 of the duty detection circuit 300, the phase separator 310 converts the first output clock DCLK1 to the rising clock RCLK and the falling clock. Divide by (FCLK). At this time, the rising clock RCLK has a high pulse width narrower by 2 * ΔD1 than the low pulse width, and the falling clock FCLK has a high pulse width 2 * ΔD1 wider than the low pulse width.
The duty detection unit 350 of the duty detection circuit 300 generates a duty detection of the first output clock DCLK1 and generates a first code CODE1 <0: N> in response to the high level mode signal MODE. Do this. Specifically, the duty detector 350 compares the high pulse width of the rising clock RCLK and the high pulse width of the falling clock FCLK and adjusts the first code CODE1 <0: N> according to the result. do. That is, since the high pulse width of the rising clock RCLK is narrower than the high pulse width of the falling clock FCLK, the duty detector 350 up counts the first code CODE1 <0: N> to display the first duty beam. Output to the government (100).
When the first code CODE1 <0: N> output from the duty detector 350 is input to the first duty compensator 100, the first duty compensator 100 may count up the first code CODE1. In response to < 0: N >, the high pulse width of the input clock ICLK is increased to generate the first output clock DCLK1.
In addition, the first output clock DCLK1 generated by the first duty compensator 100 is input to the second duty compensator 200, and the above-described duty compensation process is performed by polling the high pulse width of the rising clock RCLK. The high pulse width of the clock FCLK is repeated until the same.
When the high pulse width of the rising clock RCLK and the high pulse width of the falling clock FCLK are the same, the duty detector 350 does not change the first code CODE1 <0: N> and locks the lock. do.
As a result, when the duty cycle correction is completed, as shown in FIG. 6A, the high pulse width of the input clock ICLK is adjusted to be further increased by ΔD1 by the first duty corrector 100 to increase the high pulse width and the low pulse width. The same first output clock DCLK1 is generated. In addition, since the second code CODE2 <0: N> is not input to the second duty compensator 250, a second phase having the same phase as that of the first output clock DCLK1, that is, having a high pulse width and a low pulse width is the same. The output clock DCLK2 is generated by the second duty compensator 250.
Now, when the second code CODE2 <0: N> is externally input in the correction mode (when the mode signal MODE is at a high level) together with FIG. 6B, the second duty compensator 250 outputs the first output. The duty correction operation of the duty correction circuit in the case of correcting and outputting the duty of the clock DCLK1 will be described. For convenience of description, it is assumed that the second code CODE2 <0: N> is generated by reflecting that the high pulse width of the second output clock DCLK2 is reduced by ΔD2 due to the second duty distortion.
In the initial duty correction stage, since the first code CODE1 <0: N> input to the first duty cycle corrector 100 has an initial value, the first duty cycle corrector 100 is in phase with the input clock ICLK. This same first output clock DCLK1 is generated. That is, the high pulse width of the first output clock DCLK1 is 2 * ΔD1 narrower than the low pulse width.
The second duty compensator 250 increases the high pulse width of the first output clock DCLK1 by ΔD2 in response to an externally input second code CODE2 <0: N>. As a result, the high pulse width of the second output clock DCLK2 generated by the second duty compensator 250 is 2 * (ΔD1-ΔD2) narrower than the low pulse width.
On the other hand, when the first output clock DCLK1 is input to the phase separator 310 of the duty detection circuit 300, the phase separator 310 replaces the first output clock DCLK1 with the rising clock RCLK and the falling clock. Divide by (FCLK). The high pulse width of the rising clock RCLK is 2 * ΔD1 narrower than the low pulse width. The high pulse width of the falling clock FCLK is 2 * ΔD1 wider than the low pulse width.
The duty detection unit 350 of the duty detection circuit 300 generates a duty detection of the first output clock DCLK1 and generates a first code CODE1 <0: N> in response to the high level mode signal MODE. Do this. Specifically, the duty detector 350 compares the high pulse width of the rising clock RCLK and the high pulse width of the falling clock FCLK and adjusts the first code CODE1 <0: N> according to the result. do. Therefore, since the high pulse width of the rising clock RCLK is narrower than the high pulse width of the falling clock FCLK, the duty detection unit 350 up counts the first code CODE1 <0: N> to display the first duty beam. Output to the government (100).
When the first code CODE1 <0: N> generated by the duty detector 350 is input to the first duty compensator 100, the first duty compensator 100 may be configured to calculate the up-counted first code ( In response to CODE1 <0: N>, the high pulse width of the input clock ICLK is increased to generate the first output clock DCLK1.
In addition, the first output clock DCLK1 generated by the first duty compensator 100 is input to the second duty compensator 250, and the above-described duty compensation process is performed by polling a high pulse width of the rising clock RCLK. The high pulse width of the clock FCLK is repeated until the same.
When the high pulse width of the rising clock RCLK and the high pulse width of the falling clock FCLK are the same, the duty detector 350 does not change the first code CODE1 <0: N> and locks the lock. do.
As a result, when the duty cycle correction is completed, as illustrated in FIG. 6B, the high pulse width of the input clock ICLK is adjusted to be further increased by ΔD1 by the first duty corrector 100 to increase the high pulse width and the low pulse width. The same first output clock DCLK1 is generated. The second duty cycle corrector 250 increases the high pulse width of the first output clock DCLK1 by ΔD2 in response to the second code CODE2 <0: N>, so that the high pulse width is 2 than the low pulse width. The second output clock DCLK2, which is wider than ΔD 2, is generated by the second duty compensator 250.
Accordingly, the second duty that the high pulse width of the second output clock DCLK2 is narrowed by ΔD2 while the second output clock DCLK2 is transmitted to the target circuit through a driver, a control circuit, and the like that exist after the duty cycle correction circuit. Even if distortion occurs, the second output clock DCLK2 is generated by correcting the duty of the first output clock DCLK1 by reflecting the second duty distortion during the duty cycle, so that the target circuit has a duty of 50%. The output clock DCLK2 is input.
So far, the case in which the duty cycle correction circuit according to the present invention corrects the duty of the clock has been described. However, this is merely an example, and the duty cycle correction circuit according to the present invention is not only used for clocks but also for various types of integrated circuit chips in which the duty of a specific signal (ratio of a high pulse width to a low pulse width of a signal) needs to be kept constant. Can be used to correct the duty of a particular signal.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.
