KR20130050829A - Etchant composition and manufacturing method for thin film transistor using the same - Google Patents

Abstract

PURPOSE: An etchant composition is provided to wholly or selectively etch a semiconductor layer formed of a low resistance wire and semiconductor oxide, and to maintain initial performance by not having etching performance change for 9 days. CONSTITUTION: An etchant composition comprises an ammonium persulfate, azole-based compound, and aqueous amine compound, sulfonate-containing compound, nitrate-containing compound, and residual water and additionally comprises a fluorine-containing compound. The aqueous amine compound additionally comprises at least one selected from sulfamic acid and iminodiacetic acid. The content of the fluorine-containing compound is 0.1-2 wt%. The content of the ammonium persulfate is 0.1-25 wt%. The content of the azole-based compound is 0.01-2 wt%. The aqueous amine compound of the amine compound is 0.1-15 wt%.

Description

Etching liquid composition and method for manufacturing thin film transistor using same {ETCHANT COMPOSITION AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR USING THE SAME}

The present invention relates to an etching solution composition and a method for manufacturing a thin film transistor using the same.

Recently, as the flat panel display industry demands to realize high resolution, large area, and 3D display, a need for faster response speed is emerging. In particular, it is required to increase the movement speed of electrons in the channel portion of the TFT structure. Accordingly, low-resistance materials such as copper have been used for wiring formation, and a method of using an oxide semiconductor for increasing the electron transfer speed in the semiconductor layer has been studied.

TFTs using oxide semiconductors have attracted a lot of attention because of their excellent properties and advantages in securing mass productivity through simple structure and process. In the case of a TFT-LCD, a high-speed operating panel can be realized by using an oxide TFT having a higher mobility than that of a-Si: H TFT.

Accordingly, a technique of applying an oxide to a channel portion of a TFT and controlling an excellent taper etching profile in etching is required, and further, selective etching of a semiconductor layer is required to form a channel portion using an oxide thin film transistor.

SUMMARY OF THE INVENTION An object of the present invention is to provide an etching liquid composition capable of collectively or selectively etching a semiconductor layer formed of a low resistance wiring and an oxide semiconductor, and a method of manufacturing a thin film transistor using the same.

Another etchant composition according to one embodiment of the present invention is ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), azole compounds, water soluble amine compounds, sulfonic acid containing compounds and nitrate containing compounds and residual amounts of water.

The etchant composition may further include a fluorine-containing compound.

The fluorine-containing compound may be 0.1 wt% to 2 wt%.

The ammonium persulfate may be 0.1% to 25% by weight.

The azole compound may be 0.01% to 2% by weight.

The water soluble amine compound may be 0.1% to 15% by weight.

The sulfonic acid-containing compound may be 0.1% by weight to 5% by weight.

The nitrate-containing compound may be 0.1% to 5% by weight.

The water-soluble amine compound may include at least one of sulfamic acid and iminodiacetic acid.

The ammonium persulfate is 0.1% to 25% by weight, the azole compound is 0.01% to 2% by weight, the water-soluble amine compound is 0.1% to 15% by weight, the sulfonic acid-containing compound is 0.1% by weight To 5% by weight, and the nitrate-containing compound may be 0.1% to 5% by weight.

In another embodiment, a method of manufacturing a thin film transistor includes forming a gate electrode on a substrate, forming a gate insulating layer, a semiconductor material layer, a barrier material layer, and a metal wiring material layer on the gate electrode. Patterning a layer, the barrier material layer, and the semiconductor material layer to form a metal wiring pattern portion, a barrier pattern portion, and a semiconductor layer covering the gate electrode and the peripheral region of the gate electrode, and the metal wiring pattern portion and the barrier pattern Patterning a portion to expose the semiconductor layer positioned at a portion overlapping with the gate electrode, and the forming of the metallization pattern portion, the barrier pattern portion, and the semiconductor layer may be performed by using a first etching solution. And exposing the semiconductor layer comprises a second etch. The use comprising the bulk etch, wherein the first etchant and the second etchant has a different composition

The semiconductor layer may be formed of an oxide semiconductor.

The metal wiring material layer may include a first metal layer and a second metal layer positioned on the first metal layer, the first metal layer may include copper, and the second metal layer may include a copper manganese alloy.

The semiconductor layer may include indium gallium zinc oxide (IGZO).

The barrier material layer may include gallium zinc oxide (GZO).

The first etchant is ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), an azole compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a fluorine-containing compound, and a balance of water.

The second etching solution is ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), an azole compound, a water soluble amine compound, a sulfonic acid containing compound and a nitrate containing compound and a balance of water.

The water-soluble amine compound included in the first etchant and the second etchant may include at least one of sulfamic acid and iminodiacetic acid.

The ammonium persulfate is 0.1% to 25% by weight, the azole compound is 0.01% to 2% by weight, the water-soluble amine compound is 0.1% to 15% by weight, the sulfonic acid-containing compound is 0.1% by weight To 5% by weight, and the nitrate-containing compound may be 0.1% to 5% by weight.

Exposing the semiconductor layer positioned at a portion overlapping the gate electrode may include forming a source electrode and a drain electrode facing each other with respect to the gate electrode.

As described above, the etching liquid composition according to the exemplary embodiment of the present invention may selectively or collectively etch the oxide semiconductor film constituting the metal film and the semiconductor layer.

1 to 4 are electron scanning micrographs which appear by etching a metal film and a semiconductor layer using an etchant composition according to an embodiment of the present invention.
5 to 9 are electron scanning micrographs shown by etching the metal film and the semiconductor layer by using the etchant composition according to the comparative example.
FIG. 10 is a scanning electron microscope (SEM) photograph showing side surfaces of a metal pattern and a photo pattern manufactured by etching a metal film according to an elapsed time at room temperature storage of the etchant composition according to Example 1 of the present invention.
FIG. 11 is a scanning electron micrograph showing side surfaces of a metal pattern and a photo pattern manufactured by etching a metal film as the etchant composition according to Example 1 of the present invention is contaminated by copper (Cu) ions.
12 to 15 are cross-sectional views illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Also, when a layer is referred to as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

The etchant composition according to an embodiment of the present invention is ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), azole compounds, water-soluble amine compounds, sulfonic acid-containing compounds, nitrate-containing compounds, fluorine-containing compounds and residual water.

Ammonium persulfate is a main component for etching the wiring layer as an oxidant, and the wiring layer is etched by a reaction as in the following formula (1) to form a stable compound. In this embodiment, the wiring layer may use copper as a material.

S ₂ O ₈ ^-2 + 2Cu-> 2CuSO ₄ Formula (1).

If the content of ammonium persulfate is less than about 0.1% by weight based on the total weight of the etching solution composition, the etching solution cannot etch the wiring layer. When the content of ammonium persulfate exceeds about 25% by weight, it is difficult for the etchant to etch the etching time by etching the wiring layer too quickly. Therefore, the content of ammonium persulfate in the present embodiment is preferably about 0.1% to about 25% by weight based on the total weight of the etching liquid composition. In particular, the content of ammonium persulfate is preferably from about 5% to about 20% by weight based on the total weight of the etchant composition.

The azole compound is a 5-membered hetero ring containing a nitrogen atom and at least one non-carbon atom contained in the ring. The azole compound may control the etching rate between the upper and / or lower film quality of the copper layer by inhibiting the etching of copper in the wiring layer. The azole compound can reduce the CD skew of the metal wiring.

Specific examples of the azole compound include benzotriazole, aminotetrazole, aminotetrazole potassium salt, imidazole, pyrazole and the like.

When the content of the azole compound is less than about 0.01% by weight based on the total weight of the etching liquid composition, the etching rate between the copper film and the lower film cannot be controlled, and the straightness of the metal pattern is very low. When the content of the azole compound exceeds about 2% by weight, the etching ability of the etchant is rather inhibited by the azole compound. Therefore, the content of the azole compound is preferably about 0.01% to about 2% by weight based on the total weight of the etchant composition.

In the present embodiment, the water-soluble amine refers to a compound having a form that is soluble in water among compounds in which a hydrogen atom of ammonia (NH ₃ ) is substituted with a hydrocarbon residue, and serves as an acidity regulator in an etchant.

Generally, water-soluble amines are glycine, iminodiacetic acid, lysine, threonine, serine, asparaginic acid, parahydroxyphenyl glycine, and dihydroxyphenyl. Hydroxyethyl glycine, alanine, anthranilic acid, anthranilic acid, tryptophan, sulfamic acid, cyclohexylsulfamic acid, aliphatic amine sulfonic acid acid), taurine, taurine, aliphatic amine sulfinic acid, and aminoethanesulfinic acid. These can be used individually or in combination of 2 or more, respectively. Preferably, sulfamic acid and iminodiacetic acid may be used as the water-soluble amine.

If the content of the water-soluble amine is less than about 0.1% by weight based on the total weight of the etchant composition, the effect of copper ions may not be reduced. If the amount of the water-soluble amine is more than about 15% by weight, the metal film may be excessively etched together with ammonium persulfate to rapidly etch the metal film. The resulting metal pattern may be shorted.

Therefore, the content of the water-soluble amine is preferably about 0.1% to about 15% by weight based on the total weight of the etching liquid composition. When one compound is used alone as the water soluble amine, the content of the water soluble amine may be about 0.1% to about 15% by weight. Alternatively, when at least two or more compounds are used as a water soluble mixture, the content of the water soluble amine may be substantially the same as the sum of the contents of the compounds and the sum of the contents of the compounds may be about 0.1% to about 15% by weight. have.

For example, in this embodiment the water soluble amine may comprise from about 0.05% to about 10% by weight of sulfamic acid and from about 0.05% to about 5% by weight of iminodiacetic acid. . Accordingly, the range of sum of the content of sulfamic acid and iminodiacetic acid may be substantially the same as the content range of the water-soluble amine.

In the present embodiment, the nitrate-containing compound is a compound containing nitrate ions (NO ₃ ⁻ ), which makes an excellent tapered etching profile as an etchant in the etchant of the present composition. Examples include ammonium nitrate (NH ₄ NO ₃ ), calcium nitrate (Ca (NO ₃ ) ₂ ), zinc nitrate (Zn (NO ₃ ) ₂ ), sodium nitrate (NaNO ₃ ), aluminum nitrate (Al (NO ₃ ) ₃ ) ), Barium nitrate (Ba (NO ₃ ) ₂ ), cerium nitrate (Ce (NO ₃ ) ₃ ), copper nitrate (Cu (NO ₃ ) ₂ ), iron nitrate (Fe (NO ₃ ) ₃ ), lithium nitrate (LiNO ₃ ), magnesium nitrate (Mg (NO ₃ ) ₂ ), manganese nitrate (Mn (NO ₃ ) ₂ ), silver nitrate (Ag ₃ NO ₃ ), potassium nitrate (KNO ₃ ), etc. Composition.

If the nitrate-containing compound is less than 0.1% by weight, it may not function as an etch control agent, and when it exceeds 5% by weight, the etch rate may be lowered, which may cause problems in application of the mass production process.

In the present embodiment, the fluorine-containing compound refers to a compound containing fluoride as a main component for selectively etching an oxide semiconductor film under copper. Examples include hydrofluoric acid (HF), sodium fluoride (NaF), acidic sodium fluoride (NaHF ₂ ), ammonium fluoride (NH ₄ F), acidic ammonium fluoride (NH ₄ HF ₂ ), ammonium fluoride (NH ₄ BF ₄ ), potassium fluoride (KF), acidic potassium fluoride (KHF ₂ ), aluminum fluoride (AlF ₃ ) and boric fluoride (HBF ₄ ), lithium fluoride (LiF ₄ ), potassium fluoride (KBF ₄ ), calcium fluoride (CaF ₂ ), and the like. Can be mentioned.

When the fluorine-containing compound is 0 wt% (removed), a gallium zinc oxide film (GZO) serving as a barrier between the copper single layer, the copper manganese / copper (CuMn / Cu) multilayer, and the semiconductor layer constituting the source electrode and the drain electrode in the thin film transistor Film), and optionally an indium gallium zinc oxide film (IGZO film) is left. Also, gallium zinc oxide (GZO) and indium gallium zinc oxide constituting a single layer of copper, a manganese / copper (CuMn / Cu) multilayer film, and a semiconductor layer constituting the source / drain electrode in the range of 0.1% to 2% by weight. (IGZO) Membranes can both be etched.

If the fluorine-containing compound is less than 0.1 wt%, it is difficult to etch the indium gallium zinc oxide (IGZO) in the semiconductor layer, and if it exceeds 2 wt%, the lower insulating film is etched to cause defects.

In this embodiment, water accounts for 100% of the sum of the weight percentages of the other components except water in the total etching liquid, even if not explicitly stated. As water used for the etching solution according to the present embodiment, it is preferable to use semiconductor grade water or ultrapure water.

The range of the etchant or the etchant composition disclosed in this embodiment includes the etchant contained within the above-described weight ratio range, as well as the changed composition even if the composition is outside the numerical value of the weight ratio range or there is a substitution of some of the components shown above as an example. If it is obvious to those skilled in the art that the composition is substantially equivalent to the etchant composition, such a configuration is included.

[ Experimental Example ]

The etching solution of Examples 1 to 4 and Comparative Examples 1 to 5 with respect to the etching solution composition according to the present Example was prepared as shown in Table 1 below, and the etching characteristics thereof were compared. Examples 1 to 4, The compositions of Comparative Examples 1 to 5 are shown in Table 1 below, and all numerical values are weight ratios (wt%).

APS Azole compound Water Soluble Amine Compound1 Water soluble amine compound 2 Sulfonic acid compounds Nitrate compounds Fluoride Example 1 12 0.5 10 4 4 4 0.9 Example 2 15 0.3 5 3 4 4 0.5 Example 3 8 0.3 10 5 3 5 0.5 Example 4 12 0.5 10 4 4 4 - Comparative Example 1 12 2.5 10 4 4 4 0.9 Comparative Example 2 12 0.5 - - 4 4 0.9 Comparative Example 3 12 0.5 10 4 - 4 0.9 Comparative Example 4 12 0.5 10 4 4 - 0.9 Comparative Example 5 12 0.5 15 4 4 4 0.9

In Table 1, APS represents ammonium persulfate, water-soluble amine compound 1 represents sulfamic acid, and water-soluble amine compound 2 represents iminodiacetic acid.

Specifically, an excess of 100% of an indium gallium zinc oxide / gallium zinc oxide / copper / copper manganese (IGZO / GZO / Cu / CuMn) quadrant having a structure in which a source / drain electrode and a semiconductor layer are laminated The etching rate, CD skew and taper angle of the etchant of each Example and Comparative Example were evaluated through an etching experiment. In addition, the side cross-section of the quadruple film etched by the electron scanning micrograph was observed. The results are shown in Table 2 and FIGS. 1 to 9.

Copper Etch EPD (sec) S / D CD Skew (um) S / D taper angle (°) Whether to etch IGZO film Example 1 29 0.849 50 O Example 2 29 0.832 50 O Example 3 29 0.820 60 O Example 4 25 0.853 55 X Comparative Example 1 34 0.462 53 O Comparative Example 2 34 0.550 50 O Comparative Example 3 33 0.609 50 O Comparative Example 4 30 0.929 30 O Comparative Example 5 26 1.090 35 O

EPD (End Point Detect) is a state in which the lower layer is exposed to the etchant after etching is completed to the film to be etched by the etchant. Lower EPD values indicate more aggressive etching. The CD skew indicates the distance between the photoresist tip and the metal film tip. This distance must be within an appropriate range for the step to occur and even taper etching.

S / D wiring (source electrode / drain electrode) is located at the top of the film quality, and the wiring width is also important. If the inclination is low, the inclination becomes longer than the width of the lower part of the inclined surface, so the wiring width of the upper part of the metal becomes narrower, so it is desirable to achieve a high inclination.

In Table 2, CD Skew of each of the S / D line is preferably in the range of about 0.7 ㎛ to about 0.9 ㎛. Referring to Table 2, CD Skew of each of the S / D line formed of the etchant composition according to Examples 1 to 4 of the present invention falls within the range of about 0.7 ㎛ to about 0.9 ㎛. Although the etching liquid composition according to Comparative Examples 4 and 5 has a fast EPD, the CD Skew of the S / D line formed by using the same has an excessively large value and is not preferable because the etching width is narrowed to make the wiring width narrow.

According to the above examination, the case of forming the S / D line using the etchant composition according to Examples 1 to 4 of the present invention, the etching is relatively excellent compared to the case using the etchant composition according to Comparative Examples 1 to 5 It can be seen that the speed can be adjusted to have a taper angle of about 50 ° to about 60 °.

This range of profiles creates a high slope to maintain the wiring width of the S / D. In addition, since the CD skew is excellent, it can be seen that the straightness of the semiconductor layer pattern including the S / D line is excellent and the stability is good.

In Example 4 of Table 1, the lowermost IGZO film is selectively suppressed by the composition in which the fluorine-containing compound is removed from the composition, thereby enabling the channel portion in the semiconductor layer.

In addition, Example 1 was prepared as an etching liquid composition according to an embodiment of the present invention to verify the storage performance and the etching performance for the number of treated. Storage stability was carried out for 9 days at low temperature 10 ℃, cumulative aging was evaluated for 12 hours by contaminating 500 ppm per hour copper (Cu) ions. Table 3 below shows the results of the storage stability evaluation, and Table 4 below shows the etching results for cumulative time.

Etch Characteristics 0 day Day 3 Day 6 Day 9 EPD 29 sec 29 sec 29 sec 29 sec 100% O / E CD Skew 0.820um 0.773um 0.837um 0.797um Taper angle 50 ° 52 ° 48 ° 50 °

As shown in Table 3 and Figure 10, the etchant composition of the present invention has the advantage that can maintain the same performance as the initial there is no change in the etching characteristics until the initial low-temperature storage 9 days.

FIG. 10 is a scanning electron microscope (SEM) photograph showing side surfaces of a metal pattern and a photo pattern manufactured by etching a metal film according to an elapsed time at room temperature storage of the etchant composition according to Example 1 of the present invention.

Referring to Table 3 with FIG. 10, it can be seen that the etching solution composition according to Example 1 of the present invention has almost no change in etching characteristics until at least about 9 days. However, up to about 9 days of low temperature storage, there is an advantage that can maintain the initial performance without changing the etching characteristics.

Etch Characteristics 0 ppm / 0hr 2000ppm / 4hr 4000ppm / 8hr 6000ppm / 12hr EPD 29sec 29 sec 29 sec 29 sec 100% O / E CD Skew 0.826um 0.826um 0.843um 0.802um Taper angle 50 ° 50 ° 51 ° 52 °

Table 4 and FIG. 11 are scanning electron micrographs showing side surfaces of a metal pattern and a photo pattern manufactured by etching a metal film as the etchant composition according to Example 1 of the present invention is contaminated by Cu ions.

Referring to Table 4 together with FIG. 11, it can be seen that the etching liquid composition according to Example 1 of the present invention has almost no change in etching characteristics until the concentration of copper ions is about 6,000 ppm. That is, even if the indium gallium zinc oxide / gallium zinc oxide / copper / copper manganese (IGZO / GZO / Cu / CuMn) multiple layers including the semiconductor layer and S / D wiring is etched several times, there is an advantage that can maintain the initial etching performance .

Hereinafter, a method of manufacturing a thin film transistor using the etchant composition described above will be described.

12 to 15 are cross-sectional views illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention.

Referring to FIG. 12, a gate electrode 124 is formed on an insulating substrate 110, and a gate insulating layer 140 covering the gate electrode 124 is formed.

The semiconductor material layer 151p, the barrier material layer 160p, and the metal wiring material layer 170p are formed on the gate insulating layer 140. Here, the semiconductor material layer 151p is formed of an oxide containing at least one of indium, gallium, zinc, and tin or hafnium indium zinc oxide (HfIZO). The barrier material layer 160p may be formed of gallium zinc oxide (GZO) or indium zinc oxide (IZO).

The metal wiring material layer 170p may be formed of copper, but is not limited thereto. The metal wiring material layer 170p may be formed in a double film form including a lower film including copper and an upper film including a copper manganese alloy.

The photoresist pattern PR is formed on the metallization material layer 170p. The photoresist pattern PR has a shape covering the peripheral area of the gate electrode 124 while overlapping the gate electrode 124. At this time, the thickness at the portion overlapping with the gate electrode 124 is smaller than the thickness of the portion covering the peripheral region of the gate electrode 124. The portion where the photoresist pattern PR is thinly formed corresponds to the position where the channel portion of the thin film transistor is formed.

Referring to FIG. 13, the metallization material layer 170p, the barrier material layer 160p, and the semiconductor material layer 151p are sequentially etched using the first etchant. At this time, the metal wiring material layer 170p, the barrier material layer 160p, and the semiconductor material layer 151p positioned around the gate electrode 124 are etched to expose the gate insulating layer 140, and the gate electrode 124 is exposed. ), The photoresist pattern PR positioned at the portion overlapping with the Ns) is removed to expose the metallization material layer 170p. Here, the metal wiring pattern 170, the barrier pattern 160, and the semiconductor layer 151 covering the gate electrode 124 and the gate electrode peripheral portion are formed.

The first etchant is ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), azole compounds, water-soluble amine compounds, sulfonic acid-containing compounds, nitrate-containing compounds, fluorine-containing compounds and residual water. The above description about the etchant composition according to an embodiment of the present invention may be applied to the first etchant.

When etching with the first etchant is completed, a photoresist pattern PR ′ having a height lower than that of the photoresist pattern PR in FIG. 12 is formed.

Referring to FIG. 14, the metallization pattern portion 170 and the barrier pattern portion 160 exposed between the photoresist patterns PR ′ of FIG. 13 are sequentially etched using the second etching solution. When the metal wiring pattern unit 170 and the barrier pattern unit 160 are sequentially etched, the source electrode 173 and the drain electrode 175 facing each other are formed around the gate electrode 124, and the source electrode 173 is formed. Barrier layers 163 and 165 are formed between the semiconductor layer 151 and between the drain electrode 175 and the semiconductor layer 151, respectively.

The barrier layers 163 and 165 may prevent diffusion of components such as copper included in the source / drain electrodes 173 and 175 into the channel portion of the thin film transistor.

The second etchant is ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), azole compounds, water soluble amine compounds, sulfonic acid containing compounds, nitrate containing compounds and residual amounts of water. The information about the etchant composition according to the embodiment of the present invention described above may be applied to the second etchant.

Since the second etchant is omitted from the fluorine-containing compound as compared with the first etchant, the metallization pattern portion 170 formed of a single layer of copper or a multilayer of copper / copper manganese and the barrier pattern portion 160 formed of gallium zinc oxide (GZO) are used. May be etched, and the semiconductor layer 151 formed of indium gallium zinc oxide (IGZO) may be left.

As such, since the second etchant may selectively collectively etch the metallization pattern portion 170 and the barrier pattern portion 160, a dry etching process for etching the film corresponding to the barrier layer is unnecessary as in the related art. Therefore, the process time and cost can be lowered, and since the first and second etchant according to the present embodiment do not use hydrogen peroxide, problems such as exothermic phenomenon, deterioration of the stability of the etchant, and addition of an expensive stabilizer can be reduced. .

Referring to FIG. 15, a passivation layer 180 is formed while covering the gate insulating layer 140, the source electrode 173, the drain electrode 175, and the exposed semiconductor layer 151. The bottom layer 180 may be formed of silicon oxide or nitrogen oxide.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

110 insulated substrate 124 gate electrode
140 Gate insulating film 151 Semiconductor layer
163, 165 barrier layer
173 Source Electrode 175 Drain Electrode

Claims (20)

Ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), an azole compound, a water-soluble amine compound, a sulfonic acid-containing compound and a nitrate-containing compound and the remaining amount of the etching liquid composition. In claim 1,
Etching liquid composition further comprising a fluorine-containing compound. In claim 2,
The fluorine-containing compound is 0.1% to 2% by weight of the etchant composition. 4. The method of claim 3,
The ammonium persulfate is an etching solution composition of 0.1% by weight to 25% by weight. 5. The method of claim 4,
The azole compound is an etching solution composition of 0.01% by weight to 2% by weight. The method of claim 5,
The water-soluble amine compound is 0.1% to 15% by weight of the etchant composition. The method of claim 6,
The sulfonic acid-containing compound is 0.1 wt% to 5 wt% etching solution composition. In claim 7,
The nitrate containing compound is 0.1% to 5% by weight of the etchant composition. In claim 1,
The water-soluble amine compound is an etching solution composition comprising at least one of sulfamic acid (sulfamic acid) and iminodiacetic acid (Iminodiacetic acid). In claim 1,
The ammonium persulfate is 0.1% to 25% by weight, the azole compound is 0.01% to 2% by weight, the water-soluble amine compound is 0.1% to 15% by weight, the sulfonic acid-containing compound is 0.1% by weight To 5% by weight, the nitrate containing compound is 0.1% to 5% by weight of the etching liquid composition. Forming a gate electrode on the substrate,
Forming a gate insulating layer, a semiconductor material layer, a barrier material layer, and a metal wiring material layer on the gate electrode;
Patterning the metal wiring material layer, the barrier material layer and the semiconductor material layer to form a metal wiring pattern portion, a barrier pattern portion, and a semiconductor layer covering the gate electrode and a peripheral region of the gate electrode; and
Patterning the metallization pattern portion and the barrier pattern portion to expose the semiconductor layer positioned at a portion overlapping with the gate electrode;
The forming of the metallization pattern part, the barrier pattern part, and the semiconductor layer may include performing a batch etching using a first etchant, and exposing the semiconductor layer may include performing a batch etching using a second etchant. ,
The method of claim 1, wherein the first etchant and the second etchant have different compositions. 12. The method of claim 11,
And the semiconductor layer is formed of an oxide semiconductor. The method of claim 12,
The metallization material layer includes a first metal layer and a second metal layer on the first metal layer;
The first metal film includes copper, and the second metal film includes a copper manganese alloy. 12. The method of claim 11,
The semiconductor layer is a thin film transistor manufacturing method comprising indium gallium zinc oxide (IGZO). The method of claim 14,
And the barrier material layer comprises gallium zinc oxide (GZO). 12. The method of claim 11,
The first etchant is ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), an azole compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a fluorine-containing compound and a residual amount of water. 17. The method of claim 16,
The second etching solution is ammonium persulfate ((NH ₄ ) ₂ ) S ₂ O ₈ ; Ammonium persulfate), an azole compound, a water-soluble amine compound, a sulfonic acid-containing compound and a nitrate-containing compound and a residual amount of water. The method of claim 17,
The water-soluble amine compound included in the first etchant and the second etchant comprises at least one of sulfamic acid and iminodiacetic acid. The method of claim 18,
The ammonium persulfate is 0.1% to 25% by weight, the azole compound is 0.01% to 2% by weight, the water-soluble amine compound is 0.1% to 15% by weight, the sulfonic acid-containing compound is 0.1% by weight To 5% by weight, and the nitrate-containing compound is 0.1% to 5% by weight. 12. The method of claim 11,
Exposing the semiconductor layer positioned at a portion overlapping with the gate electrode, forming a source electrode and a drain electrode facing each other with respect to the gate electrode.

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