KR20130043924A - Interconnection unit using delayed symbol transmission - Google Patents

Interconnection unit using delayed symbol transmission Download PDF

Info

Publication number
KR20130043924A
KR20130043924A KR1020110108116A KR20110108116A KR20130043924A KR 20130043924 A KR20130043924 A KR 20130043924A KR 1020110108116 A KR1020110108116 A KR 1020110108116A KR 20110108116 A KR20110108116 A KR 20110108116A KR 20130043924 A KR20130043924 A KR 20130043924A
Authority
KR
South Korea
Prior art keywords
signal
input signal
drain
gate
delayed
Prior art date
Application number
KR1020110108116A
Other languages
Korean (ko)
Inventor
박광일
전영현
공배선
Original Assignee
삼성전자주식회사
성균관대학교산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사, 성균관대학교산학협력단 filed Critical 삼성전자주식회사
Priority to KR1020110108116A priority Critical patent/KR20130043924A/en
Publication of KR20130043924A publication Critical patent/KR20130043924A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

The present invention is directed to an interconnect portion that uses delayed symbol transmission. The interconnection unit may include: a transmission unit transmitting an input signal and an input signal delayed by one clock cycle from the input signal, a first transmission line transferring an input signal, a second transmission line transferring an input signal delayed by one clock cycle, and first and And a receiver configured to receive an input signal transmitted through the second transmission lines and an input signal delayed by one clock cycle. The receiver latches a data signal received one clock cycle before, senses a voltage difference between the input signal and the one clock cycle delayed input signal, and determines that the voltage difference between the input signal and the one clock cycle delayed input signal is less than a predetermined value. In this case, the previously received data is determined as the currently received data.

Description

Interconnection unit using delayed symbol transmission

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to an interconnection portion using delayed symbol transmission.

As VLSI technology scales down, the area of on-chip interconnections is steadily shrinking. However, global on-chip wires do not scale down because the overall chip size does not decrease as the number of functional modules in the chip increases. In line with this trend, global on-chip interconnections may be a key item in future VLSI designs.

An object of the present invention is to provide an interconnection unit using delayed symbol transmission.

According to an aspect of the present invention, an interconnection unit may include: a transmission unit transmitting an input signal and an input signal delayed by one symbol from an input signal, a first transmission line transferring an input signal, a second transmission line transferring an one symbol delayed input signal, And a receiver configured to sense and receive a voltage difference between an input signal transmitted through the first and second transmission lines and an input signal delayed by one symbol.

According to embodiments of the present invention, the one-signal delayed input signal may be set to the one-cycle delayed signal of the clock signal from the input signal.

According to embodiments of the present invention, the transmission unit may include a first driver for inputting an input signal and outputting a first transmission signal, a delay unit for delaying an input signal to output an input signal delayed by one symbol, and an input signal delayed by one symbol It may include a second driver for outputting a second transmission signal by inputting.

According to embodiments of the present invention, the first or second driver may be configured as an inverter.

According to the embodiments of the present invention, the receiver senses a voltage difference between the input signal and the one-signal delayed input signal to generate a first node signal and a second node signal, and a first node signal and a first node signal and a first node. And a second sensing unit configured to sense a voltage difference between the two node signals to generate first and second reception output signals.

According to embodiments of the present invention, the first sensing unit includes a first NMOS transistor having an input signal connected to the gate thereof, a second NMOS transistor having an input signal delayed by one symbol cycle connected to the gate thereof, and first and second signals. A third NMOS transistor having a source of NMOS transistors connected to its drain, a clock signal connected to its gate, a ground voltage connected to the source, a clock signal connected to the gate, and a power supply voltage connected to the source A first PMOS transistor connected to the drain of the first NMOS transistor and generated as a first node signal, and a clock signal to a gate thereof, a power supply voltage to a source thereof, and a second A drain of the NMOS transistor may be connected to the drain to include a second PMOS transistor generated as a second node signal.

According to embodiments of the present invention, the second sensing unit may include a first NMOS transistor having a first node signal connected to a gate thereof, a ground voltage connected to a source thereof, and a first received output signal connected to a drain thereof. A second NMOS transistor having a second node signal connected to its gate, a ground voltage connected to its source, a second receive output signal connected to its drain, a second receive output signal connected to the gate thereof, A third NMOS transistor having a ground voltage connected to the source thereof, a first NMOS transistor having a first receive output signal connected to the drain thereof, a first receive output signal connected to the gate thereof, a ground voltage connected to the source thereof, and a second receive A fourth NMOS transistor having an output signal connected to the drain thereof, a first PMOS transistor having a second previous data signal connected to the gate thereof, and a first PMOS transistor having a first received output signal connected to the drain thereof; A second PMOS transistor, the second signal being connected to the gate thereof, the second PMOS transistor connected to the drain thereof, the second receive output signal being coupled to the gate thereof, and the first receive output signal being coupled to the drain thereof. A third PMOS transistor, a fourth PMOS transistor having a first receive output signal connected to its gate, a fourth PMOS transistor having a second receive output signal connected to its drain, and a clock signal connected to the gate thereof, and a power supply voltage The fifth PMOS transistor may be connected, and sources of the first to fourth PMOS transistors may be connected to a drain thereof.

According to embodiments of the present invention, the first transmission line may be connected to a termination resistor connected to the power supply voltage, and the second transmission line may be connected to a termination resistor connected to the power supply voltage.

According to another aspect of the present invention, an interconnection unit includes: a transmission unit transmitting an input signal delayed by one clock cycle from an input signal and an input signal, a first transmission line transferring an input signal, and a second transmission unit transmitting an input signal delayed by one clock cycle Receives an input signal and one clock cycle delayed input signal transmitted through the transmission line and the first and second transmission lines, latches a data signal received one clock cycle before, and input signal and one clock cycle delayed input signal. And a sensing unit configured to sense a voltage difference between the input signal and determine the previously received data as the currently received data when the voltage difference between the input signal and the input signal delayed by one clock cycle is smaller than a predetermined value.

The interconnection unit of the present invention described above has the characteristic of reducing power consumption, peak current, and delay spread.

1A and 1B are diagrams illustrating signal waveforms transmitted to an interconnector unit of the present invention.
2 is a view illustrating an interconnector unit according to various embodiments of the present disclosure.
3A and 3B are diagrams illustrating the first and second drivers of FIG. 2.
4 is a view for explaining a receiver of FIG. 2.
5 is a signal waveform diagram illustrating an operation of the interconnection unit of FIG. 2.
6A and 6B illustrate average power consumption and peak current according to the operation of the interconnection unit of FIG. 2.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Interconnections have a latency problem. In order to solve the latency problem, a technique of inserting a repeater into the interconnection is used. In order to achieve low latency and high data throughput, the size and number of repeaters can be optimized. However, a repeater scheme with repeaters of equally large size along the wire for minimal delay results in a large layout area. Bidirectional repeaters used for bidirectional communication require additional area and power.

1A and 1B are diagrams illustrating signal waveforms transmitted to an interconnector unit of the present invention.

Typically, the interconnection portion may distort the symbol response due to intersymbol interference (hereinafter referred to as "ISI"). The receiving end of the interconnection unit may sense the received signals by comparing them with a reference voltage. The signals at the receiving end must transition at the reference voltage level with sufficient voltage margin for each symbol cycle.

Referring to FIG. 1A, an original signal waveform A and a signal waveform B of a receiver are shown. As the delay time of the signal transmission wire increases, the original signal waveform A appears as a signal waveform B at the receiving end. At the receiving end, signal sensing fails.

In order to solve this problem, as shown in FIG. 1B, an on-chip interconnector for transmitting not only the original symbol A but also the 1-cycle-delayed symbol C may be proposed as the transmission wire. As a result, constant voltage differences D1, D2, and D3 appear between the two symbols, so that a reliable sensing can be performed at the receiving end, resulting in a high data rate.

2 is a view illustrating an interconnector unit according to various embodiments of the present disclosure.

Referring to FIG. 2, the interconnection unit 20 includes a transmitter 21, first and second transmission lines 25A and 25B, and a receiver 26.

The transmitter 21 may include a first driver 22, a delay unit 23, and a second driver 24. The first driver 22 may input the input signal D N to output the first transmission signal DO N. The first transmission signal DO N may be transmitted to the first transmission line 25A.

Delay unit 23 may output the input signal (D N) for one symbol cycle by the delayed input signal (D N -1) to delay. One symbol cycle may mean one cycle of the clock signal CLK. The second driver 24 may input the input signal D N -1 delayed by one symbol cycle to output the second transmission signal DO N -1 . The second transmission signal DO N -1 may be transmitted to the second transmission line 25B.

The first transmission signal DO N transmitted to the first transmission line 25A may be provided as the first input signal RI of the receiver 26. The first transmission line 25A may be connected to the first termination resistor 27 connected to the power supply voltage VDD.

The second transmission signal DO N- 1 transmitted to the second transmission line 25B may be provided as a second input signal RIB of the receiver 26. The second transmission line 25B may be connected to the second termination resistor 28 connected to the power supply voltage VDD.

The receiver 26 may compare and sense the first input signal RI and the second input signal RIB.

3A and 3B are diagrams illustrating the first and second drivers 22 and 24 of FIG. 2.

Referring to FIG. 3A, the first driver 22 may include a PMOS transistor 31 connected between a power supply voltage VDD and a first transmission signal DO N , a first transmission signal DO N , and a ground voltage. And an NMOS transistor 32 connected between the VSSs. Gates of the PMOS transistor 31 and the NMOS transistor 32 may be connected to an input signal D N. The first driver 22 may be configured as an inverter.

Referring to FIG. 3B, the second driver 24 includes a PMOS transistor 33 connected between the power supply voltage VDD and the second transmission signal DO N- 1 , and the second transmission signal DO N -1. ) And the NMOS transistor 34 connected between the ground voltage VSS. Gates of the PMOS transistor 33 and the NMOS transistor 34 may be connected to the input signal D N −1 delayed by one symbol cycle. The second driver 24 may be configured as an inverter.

4 is a diagram for explaining the receiver 26 of FIG. 2.

Referring to FIG. 4, the receiver 26 may include a first sensing unit 40 and a second sensing unit 50. The receiver 26 may be configured as a double-tail latch type sense amplifier. The receiver 26 may obtain the speed and the offset voltage regardless of the input common mode voltage. The receiver 26 may implement hysteresis by forward feedback the previously received data signals LO and LOB. When the voltage difference between the received symbols is smaller than the specified value, the receiver 26 may determine the previously received data LO and LOB as currently received data.

The first sensing unit 40 may generate a first node signal NA and a second node signal NB by sensing a voltage difference between the first input signal RI and the second input signal RIB. The first sensing unit 40 may include first to third NMOS transistors 41, 42, and 45 and first and second PMOS transistors 43 and 44.

The first NMOS transistor 41 may input the first input signal RI to the gate thereof, and the second NMOS transistor 42 may input the second input signal RIB to the gate thereof. Sources of the first and second NMOS transistors 41 and 42 may be connected to a drain of the third NMOS transistor 45. In the third NMOS transistor 45, a clock signal CLK may be connected to a gate thereof, and a ground voltage VSS may be connected to a source thereof.

The drain of the first NMOS transistor 41 may be connected to the drain of the first PMOS transistor 43 and may be generated as the first node signal NA. The drain of the second NMOS transistor 42 may be connected to the drain of the second PMOS transistor 44 and may be generated as the second node signal NB. Gates of the first and second PMOS transistors 43 and 44 may be connected to a clock signal CLK, and sources thereof may be connected to a power supply voltage VDD.

The second sensing unit 50 may sense the voltage difference between the first node signal NA and the second node signal NB to generate the first and second reception output signals RO and ROB. The second sensing unit 50 may include first to fourth NMOS transistors 51, 52, 56, and 58 and first to fifth PMOS transistors 53, 54, 55, 57, and 59. Can be.

The first NMOS transistor 51 may have a first node signal NA connected to a gate thereof, and the second NMOS transistor 52 may have a second node signal NB connected thereto. Sources of the first and second NMOS transistors 51 and 52 may be connected to a ground voltage VSS. A drain of the first NMOS transistor 51 may be connected to the first receive output signal RO, and a drain of the second NMOS transistor 52 may be connected to the second receive output signal ROB.

The third NMOS transistor 56 may have a second receive output signal ROB connected to its gate, and the fourth NMOS transistor 58 may have a first receive output signal RO connected to its gate. Sources of the third and fourth NMOS transistors 56 and 58 may be connected to the ground voltage VSS. The drain of the third NMOS transistor 56 may be connected to the first receive output signal RO, and the drain of the fourth NMOS transistor 58 may be connected to the second receive output signal ROB.

The first PMOS transistor 53 may be connected to the gate of the second previous data signal LOB, and the second PMOS transistor 54 may be coupled to the gate of the first previous data signal LO. Sources of the first and second PMOS transistors 53 and 54 may be connected to a drain of the fifth PMOS transistor 59. A drain of the first PMOS transistor 53 may be connected to the first receive output signal RO, and a drain of the second PMOS transistor 54 may be connected to the second receive output signal ROB.

The third PMOS transistor 55 may be connected to a gate of the second receive output signal ROB, and the fourth PMOS transistor 57 may be connected to a gate thereof of the first receive output signal ROB. Sources of the third and fourth PMOS transistors 55 and 57 may be connected to drains of the fifth PMOS transistor 59. A drain of the third PMOS transistor 55 may be connected to the first receive output signal RO, and a drain of the fourth PMOS transistor 57 may be connected to the second receive output signal ROB. The inverted clock signal CLKB is connected to a gate of the fifth PMOS transistor 59, and a ground voltage VDD is connected to a source thereof.

5 is a signal waveform diagram illustrating an operation of the interconnection unit 20 of FIG. 2.

Referring to FIG. 5, the first transmission signal DO N and the second transmission signal DO N −1 of the transmitter 21 are transmitted through the first transmission line 25A and the second transmission line 25B. The first input signal RI and the second input signal RIB of the receiver 26 are transmitted.The second transmission signal DO N -1 is a signal delayed by one symbol from the first transmission signal DO N. The receiver 26 senses a voltage difference between the first input signal RI and the second input signal RIB to generate a first receive output signal RO and a second receive output signal ROB. The reception output signal RO and the second reception output signal ROB are latched into the first previous data signal LO and the second previous data signal LOB in response to the clock signal CLK.

6A and 6B illustrate average power consumption and peak current according to the operation of the interconnection unit of FIG. 2.

In FIG. 6A, since the repeater scheme (-■-■-■ -marking) has full-rail swing and large parasitic capacitance, power consumption can be increased in proportion to the switching activity factor. On the other hand, the interconnection portion 20,-▲-▲-▲ -marks of the present invention is a reduced voltage swing without additional parasitic capacitance, indicating power consumption less dependent on the switching activity. That is, the power consumption can be reduced to about 61.6% of the power consumption according to the switching activity factor. In Figure 6b, the peak current of the interconnection portion of the present invention can be seen to be reduced by 52.1% compared to the conventional repeater scheme.

The delay spread characteristics of the interconnection unit and the interconnection unit 20 (FIG. 2) of the present invention implemented by a conventional repeater scheme according to PVT (Process, Voltage, Temperature) can be summarized as shown in Table 1. have.

Repeat Scheme Invention (FIG. 2) Improvement Slow process
90 ℃, VDD = 1.1V +380 ps +143 ps 62.4% Fast process
0 ℃, VDD = 1.3V -173 ps -70 ps 59.5% Total Delay Spread 553 ps 213 ps 61.5%

Therefore, the interconnector 20 (FIG. 2) of the present invention may have a characteristic of reducing power consumption, peak current, and delay spread.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

A transmitter for transmitting an input signal and an input signal delayed by one symbol from the input signal;
A first transmission line carrying the input signal;
A second transmission line carrying the one symbol delayed input signal; And
And a receiver configured to sense and receive a voltage difference between the input signal transmitted through the first and second transmission lines and the one symbol delayed input signal. The method of claim 1, wherein the one symbol delayed input signal is
And a signal delayed by one cycle of the clock signal from the input signal. The apparatus of claim 1,
A first driver for inputting the input signal to output a first transmission signal;
A delay unit for delaying the input signal and outputting the one symbol delayed input signal; And
And a second driver for inputting the one-signal delayed input signal and outputting a second transmission signal. The method of claim 3, wherein the first or second driver is
An interconnector unit comprising an inverter. The method of claim 1, wherein the receiving unit
A first sensing unit configured to generate a first node signal and a second node signal by sensing a voltage difference between the input signal and the first symbol delayed input signal; And
And a second sensing unit configured to sense a voltage difference between the first node signal and the second node signal to generate first and second reception output signals. The method of claim 5, wherein the first sensing unit
A first NMOS transistor having the input signal connected to its gate;
A second NMOS transistor having the one symbol delayed input signal connected to a gate thereof;
A third NMOS transistor having a source of the first and second NMOS transistors connected to a drain thereof, a clock signal connected to the gate thereof, and a ground voltage connected to the source thereof;
A first PMOS transistor connected to the gate of the clock signal, a power supply voltage to a source thereof, and a drain of the first NMOS transistor connected to the drain thereof to generate the first node signal; And
The clock signal is connected to a gate thereof, a power supply voltage is connected to a source thereof, and a drain of the second NMOS transistor is connected to the drain thereof, the second PMOS transistor being generated as the second node signal. Interconnection part which is characterized by. The method of claim 5, wherein the second sensing unit
A first NMOS transistor connected at a gate thereof to the first node signal, at a source thereof to a ground voltage, and at a drain thereof to the first received output signal;
A second NMOS transistor coupled to the gate of the second node signal, coupled to the source thereof, and coupled to the drain thereof, of the second received output signal;
A third NMOS transistor connected at a gate thereof to the second receive output signal, at a source thereof to the ground voltage, and at a drain thereof to the first receive output signal;
A fourth NMOS transistor connected at a gate thereof to the first receive output signal, at a source thereof to the ground voltage, and at a drain thereof to the second receive output signal;
A first PMOS transistor coupled to a gate thereof with a second previous data signal and coupled to the drain thereof;
A second PMOS transistor having a first previous data signal connected to a gate thereof and the second received output signal connected to a drain thereof;
A third PMOS transistor coupled to the gate thereof with the second receive output signal connected to the drain thereof;
A fourth PMOS transistor having the first receive output signal connected to a gate thereof, and the second receive output signal connected to a drain thereof; And
And a fifth PMOS transistor, wherein the clock signal is connected to a gate thereof, a power supply voltage is connected to a source thereof, and sources of the first to fourth PMOS transistors are connected to a drain thereof. part. The method of claim 1, wherein the first transmission line
And a termination resistor connected to the power supply voltage. The method of claim 1, wherein the second transmission line
And a termination resistor connected to the power supply voltage. A transmitter for transmitting an input signal and an input signal delayed by one clock cycle from the input signal;
A first transmission line carrying the input signal;
A second transmission line for transmitting the input signal delayed by one clock cycle; And
Receive the input signal and the one clock cycle delayed input signal transmitted through the first and second transmission lines, latch a data signal received before the one clock cycle, and delay the input signal and the one clock cycle delayed And a receiver configured to sense a voltage difference between an input signal and determine the previously received data as currently received data when the voltage difference between the input signal and the input signal delayed by one clock cycle is smaller than a predetermined value. Interconnector portion characterized by.
KR1020110108116A 2011-10-21 2011-10-21 Interconnection unit using delayed symbol transmission KR20130043924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110108116A KR20130043924A (en) 2011-10-21 2011-10-21 Interconnection unit using delayed symbol transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110108116A KR20130043924A (en) 2011-10-21 2011-10-21 Interconnection unit using delayed symbol transmission

Publications (1)

Publication Number Publication Date
KR20130043924A true KR20130043924A (en) 2013-05-02

Family

ID=48656565

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110108116A KR20130043924A (en) 2011-10-21 2011-10-21 Interconnection unit using delayed symbol transmission

Country Status (1)

Country Link
KR (1) KR20130043924A (en)

Similar Documents

Publication Publication Date Title
KR101965788B1 (en) Single-ended configurable multi-mode driver
US8624632B2 (en) Sense amplifier-type latch circuits with static bias current for enhanced operating frequency
US8334709B2 (en) Level shifter
US10200025B2 (en) Pulse-amplitude modulated hybrid comparator circuit
US9099990B2 (en) High speed communication interface with an adaptive swing driver to reduce power consumption
Lee et al. Current-mode transceiver for silicon interposer channel
Lee et al. An 80 mV-swing single-ended duobinary transceiver with a TIA RX termination for the point-to-point DRAM interface
US20130099822A1 (en) Cml to cmos conversion circuit
US20150155875A1 (en) Lvds driver
US20080238519A1 (en) Signaling circuit and method for integrated circuit devices and systems
JP4957405B2 (en) Signal waveform equalization circuit and reception circuit
US8994403B2 (en) Apparatus and method for signal transmission over a channel
KR100801058B1 (en) Signaling circuit reducing skew, Method there-of and System including the circuit
US7558980B2 (en) Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers
US7190193B1 (en) Method and apparatus for a differential driver with voltage translation
KR20130043924A (en) Interconnection unit using delayed symbol transmission
US5633602A (en) Low voltage CMOS to low voltage PECL converter
Mroszczyk et al. Ultra-low swing CMOS transceiver for 2.5-D integrated systems
Seetharaman Design and analysis of novel interconnects with network-on-chip LVDS transmitter for low delay
US11949425B2 (en) Digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture with tunable impedance control and transition glitch reduction techniques
US20240106431A1 (en) Receivers for high density and low latency chip-to-chip links
US11831153B1 (en) High-bandwidth signal driver/receiver
US20230058343A1 (en) Nmos low swing voltage mode tx driver
US20240005966A1 (en) Data receiving circuit, data receiving system, and memory device
Sridhar et al. Comprehensive study on the signaling schemes in on chip interconnects

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination