KR20130043047A - High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A high electron mobility transistor and a manufacturing method thereof are provided to minimize the change of a gate threshold voltage by accurately controlling the thickness of a material layer. CONSTITUTION: A channel layer(34) includes a 2DEG channel and a depletion region. A first channel supply layer(36) is formed on the channel layer. A depletion layer(40) is formed in a part of the first channel supply layer and the depletion region. The depletion region is formed between a source electrode and a drain electrode to face each other. A gate(44) is formed on the depletion layer.

Description

High Electron Mobility Transistor having reduced threshold voltage variation and method of manufacturing the same

One embodiment of the present invention relates to a power device and a method for manufacturing the same, and more particularly, to a high electron mobility transistor having a reduced threshold voltage variation and a method for manufacturing the same.

High Electron Mobility Transistors (HEMTs) are one of the power devices. HEMT includes compound semiconductors having different polarization rates, and a 2-dimensional electron gas (2DEG), which is used as a carrier, is formed in the channel layer. If the thickness of the AlGaN barrier layer is formed in the HEMT, the concentration of 2DEG can be increased in the channel layer, thereby increasing the current at turn-on, that is, the ON current. However, when the thickness of the AlGaN barrier layer is thick, the energy band of the AlGaN barrier layer due to the depletion layer formed between the gate and the AlGaN barrier layer is small. Therefore, 2DEG may not be completely removed from the channel layer under the gate, and thus, the E-mode operation of the HEMT may be difficult.

In such a HEMT, a recess may be formed in the AlGaN barrier layer under the gate to completely remove the 2DEG from the channel layer under the gate. However, in the etching process for forming the recess, the thickness of the AlGaN barrier layer remaining under the recess after the recess may vary for each HEMT. Accordingly, a threshold voltage Vth for turning on may vary for each HEMT, which may be one of the causes of the deterioration of reliability of the HEMT operation.

One embodiment of the present invention provides a HEMT that can reduce the threshold voltage variation for each product.

One embodiment of the present invention provides a method of manufacturing such a HEMT.

An HEMT according to an embodiment of the present invention is formed on a substrate including a compound semiconductor, and includes a channel layer including a 2DEG channel and a depletion area, and a channel layer corresponding to the 2DEG channel. A first channel supply layer formed, a depletion layer formed on the depletion region of the channel layer and a partial region of the first channel supply layer, and a depletion region formed on the first channel supply layer, Source and drain electrodes facing each other, and a gate formed on the depletion layer.

In this HEMT, a second channel supply layer having a polarization lower than that of the first channel supply layer is provided on a depletion region of the channel layer and a partial region of the first channel supply layer, and the depletion layer includes It may be provided on the second channel supply layer.

The source and drain electrodes may be in contact with or spaced apart from the depletion layer.

An insulating layer may be further provided between the gate and the depletion layer.

The depletion layer may be a compound semiconductor layer having a polarization smaller than that of the first channel supply layer and doped with a p-type doping material.

The depletion layer may be a compound semiconductor layer having a polarization rate smaller than that of the first channel supply layer, and the content of the main component causing polarization varies depending on the thickness.

The first channel supply layer is doped with an n-type doping material, and may be a nitride layer including at least one of Al, Ga, and In.

The depletion layer may be doped or not doped with a p-type dopant and may include at least one of Al, Ga, and In.

The first and second channel supply layers may be compound semiconductor layers having the same composition and different composition ratios.

The thickness of the first channel supply layer may be 20 nm to 200 nm, and the thickness of the second channel supply layer may be 5-20 nm.

The gate can be a p-metal or a nitride.

The first and second channel supply layers may have the same polarization rate.

A transistor according to an embodiment of the present invention defines a channel layer including a 2DEG channel and a depletion region, an opening for exposing the depletion region, and supplies a first channel formed on the 2DEG channel. A layer, a depletion layer formed on the first channel supply layer and the depletion region, a source and drain electrode formed on the first channel supply layer and spaced apart from each other, and formed on the depletion layer. The depletion layer includes a gate electrode, and includes a compound semiconductor containing nitrogen (N) and at least one of aluminum (Al), gallium (Ga), and indium (In).

The transistor may further include a second channel supply layer between the depletion layer and the depletion region.

The polarization rate of the second channel supply layer may be smaller than the polarization rate of the first channel supply layer.

An insulating layer may be further provided between the gate electrode and the depletion layer.

The depletion layer may include a p-type dopant.

The polarization rate of the depletion layer may be smaller than the polarization rate of the first channel supply layer.

HEMT according to another embodiment of the present invention is formed on the substrate, the source electrode, the drain electrode and the gate electrode spaced apart from each other, the depletion layer formed on the gate electrode, and formed on at least a portion of the depletion layer And a channel layer formed on the depletion layer and the first channel supply layer, wherein the channel layer corresponds to a 2DEG channel corresponding to the first channel supply layer and the depletion layer. It may include a depletion region.

In the HEMT manufacturing method according to an embodiment of the present invention, a channel layer is formed on a substrate, a first channel supply layer having a greater polarization than the channel layer is formed on the channel layer, and the first channel supply layer. A portion of the channel layer is removed by forming a portion of the channel layer, and a depletion layer is formed on the first channel supply layer to cover an exposed area of the channel layer, and the depletion layer is formed on the first channel supply layer. Forming source and drain electrodes facing each other with the gap therebetween, and forming a gate on the depletion layer.

In this manufacturing method, before forming the depletion layer, a second channel supply layer is formed on the first channel supply layer to cover the exposed area of the channel layer and has a lower polarization than that of the first channel supply layer. The depletion layer may be formed on the second channel supply layer.

An insulating layer may be formed between the gate and the depletion layer.

The depletion layer may be formed of a compound semiconductor layer having a polarization smaller than that of the first channel supply layer and doped with a p-type doping material.

The depletion layer may be formed of a compound semiconductor layer having a polarization rate smaller than that of the first channel supply layer, and the content of the main component causing polarization varies depending on the thickness.

The first channel supply layer is doped with an n-type doping material, and may be a nitride layer including at least one of Al, Ga, and In.

The depletion layer may be a nitride layer that is doped or not doped with a p-type dopant and includes at least one of Al, Ga, and In.

The first and second channel supply layers may be formed of a compound semiconductor layer having the same composition and different composition ratios.

The gate may be formed of p-metal or nitride.

The depletion layer and the second channel formation layer may be formed by epitaxy.

The source and drain electrodes may be formed to be spaced apart from the depletion layer.

The surface roughness of the exposed region of the channel layer may be alleviated by wet etching before forming the depletion layer.

Polarization rates of the first and second channel supply layers may be the same.

After the channel supply layer is formed on the channel layer in the HEMT according to an embodiment of the present invention, the portion formed under the gate of the channel supply layer is completely removed. Thereafter, the depletion layer is directly grown on the channel layer from which the channel supply layer has been removed by epitaxial method, or the other channel supply layer and the depletion layer are sequentially grown in the same manner as the channel supply layer. .

Since the depletion layer or another channel supply layer and the depletion layer formed on the depletion region under the gate are grown by the epitaxy method, the thickness of the material layer formed between the gate and the channel layer can be precisely controlled. Accordingly, the thickness of the material layer formed between the gate and the channel layer may be kept constant for each HEMT within an error range. Therefore, since the change in the gate threshold voltage can be minimized for each HEMT, the operation reliability of the HEMT can be improved.

Further, since the other channel supply layer is also grown on the channel supply layer between the gate and drain electrodes, the thickness of the channel supply layer between the gate and drain electrodes becomes thicker than under the gate. Accordingly, even if there is a depletion layer between the gate and drain electrodes, the 2DEG density does not decrease in the channel layer between the gate and drain electrodes.

1 is a cross-sectional view of a HEMT according to an embodiment of the present invention.
2A to 2C are cross-sectional views illustrating a case in which the depletion layer is spaced apart from at least one of the source and drain electrodes in FIG. 1.
FIG. 3 is a cross-sectional view illustrating a case in which an insulating layer (gate insulating film) is further provided between the gate and the depletion layer in FIG. 1.
4 is a cross-sectional view of a HEMT according to another embodiment of the present invention.
5 is a cross-sectional view illustrating a case in which an insulating layer (gate insulating film) is further provided between the gate and the depletion layer in FIG. 4.
6 to 12 are cross-sectional views showing step by step the manufacturing method of the HEMT according to an embodiment of the present invention.
13 to 18 are cross-sectional views showing step by step of the manufacturing method of the HEMT according to another embodiment of the present invention.
19 to 22 are cross-sectional views illustrating a method of manufacturing an HEMT according to still another embodiment of the present invention.
FIG. 23 is a graph illustrating 2DEG and 2DHG densities between gate and drain electrodes measured in a simulation performed on HEMT according to an embodiment of the present invention.
24A to 24C are cross-sectional views illustrating a case in which the depletion layer is spaced apart from at least one of the source and drain electrodes in FIG. 4.
25A and 25B are sectional views illustrating a HEMT according to another embodiment of the present invention.
26A to 26G are cross-sectional views illustrating a method of manufacturing a HEMT according to still another embodiment of the present invention.

Hereinafter, a HEMT and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

First, an HEMT according to an embodiment of the present invention will be described.

Referring to FIG. 1, a buffer layer 32 is formed on a substrate 30. The substrate 30 may be, for example, a silicon substrate, a silicon carbide (SiC) substrate, or an aluminum oxide (eg, Al 2 O 3) substrate. The buffer layer 32 may be a compound semiconductor layer. For example, the buffer layer 32 may be a GaN layer, an AlGaN layer, or an AlGaInN layer. A seed layer may be further provided between the substrate 30 and the buffer layer 32. In this case, the seed layer may be, for example, an AlN layer, AlGaN layer. On the buffer layer 32 is a material layer 34 comprising 2DEG (G1). The material layer 34 may be a compound semiconductor layer, for example, a GaN layer. The 2DEG G1 may be located below the top surface of the material layer 34. 2DEG (G1) may be used as a channel carrier. As such, the material layer 34 includes 2DEG (G1) used as a channel carrier, and is referred to as a channel layer 34 hereinafter in the sense of a material layer including a channel. 2DEG does not exist in the partial area A1 below the upper surface of the channel layer 34. This area A1 is an area from which 2DEG is removed, hereinafter referred to as a depletion area A1. There is a first channel supply layer 36 on the channel layer 34. The thickness of the first channel supply layer 36 may be 20 nm or more, for example, 20 nm to 200 nm. The thickness of the first channel supply layer 36 may be 20 nm or less. The first channel supply layer 36 may be a compound semiconductor layer. The polarization rate and the band gap of the first channel supply layer 36 may be greater than that of the channel layer 34. This difference between the channel layer 34 and the first channel supply layer 36 causes the 2DEG (G1) to appear in the channel layer 34. The compound semiconductor of the first channel supply layer 36 may be Al _x Ga _(1-xy) In _y N. Here, x may be 0 <x≤1, y may be 0≤y <1, and 0 <x + y≤1. For example, the first channel supply layer 36 may include any one of AlN, AlGaN, AlInN, and AlGaInN. The first channel supply layer 36 is on the top surface of the channel layer 34 corresponding to the 2DEG (G1). The first channel supply layer 36 does not exist on the depletion region A1 of the channel layer 34. On the first channel supply layer 36 there is a second channel supply layer 38 covering the depletion region A1 of the channel layer 34. The second channel supply layer 38 may cover a portion of the upper surface of the first channel supply layer 36. Although less impact than the first channel supply layer 36, the second channel supply layer 38 may affect the generation of 2DEG (G1) of the channel layer 34. The thickness of the second channel supply layer 38 may be 20 nm or less, for example thicker than 1 nm and thinner than 20 nm.

As the second channel supply layer 38 is provided on the first channel supply layer 36, the thickness of the channel supply layer 36 + 38 existing on the 2DEG (G1) is formed on the depletion region A1. It is thicker than the channel supply layer 38. According to the step of the first channel supply layer 36 at the boundary of the depletion region A1, the second channel supply layer 38 is recessed on the depletion region A1. The second channel supply layer 38 may be a compound semiconductor layer. The compound semiconductor of the second channel supply layer 38 may be Al _x Ga _(1-xy) In _y N. Here, x may be 0 <x≤1, y may be 0≤y <1, and 0 <x + y≤1. The polarization rate of the second channel supply layer 38 may be smaller than that of the first channel supply layer 36. The polarization rates of the first and second channel supply layers 36 and 38 may be the same, for example, the polarization ratio of the second channel supply layer 38 is the same as that of the first channel supply layer 36. can do. The first and second channel supply layers 36, 38 may be the same compound semiconductor layer, in which case certain components of the first and second channel supply layers 36, 38, for example aluminum (Al) or indium The content of (In) may vary. For example, when both the first and second channel supply layers 36 and 38 are AlGaN layers, the aluminum content of the first channel supply layer 36 is 35% and the aluminum content of the second channel supply layer 38 is May be 20% and vice versa. The first and second channel supply layers 36 and 38 may be doped with an n-type doping material. Silicon (Si) may be used as the n-type doping material, but is not limited thereto.

There is a depletion layer 40 on the second channel supply layer 38. The deflation layer 40 may cover the recessed portion of the second channel supply layer 38 and the periphery thereof. The overall thickness of the channel supply layer 36 + 38 present over the 2DEG (G1) is thicker than the second channel supply layer 38 formed on the depletion region A1 of the channel layer 34. Therefore, the influence of the depletion layer 40 is limited to the depletion region A1, and the presence of the depletion layer 40 does not affect the density of the 2DEG (G1). The thickness of the deflation layer 40 may be, for example, 5 to 500 nm.

Although the 2DEG appears in the depletion region A1 of the channel layer 34 by the second channel supply layer 38, the 2DEG thus displayed is removed by the depletion layer 40. In this way, 2DEG does not exist in the depletion area | region A1. If present, the amount can be extremely small compared to 2DEG (G1), so the effect can be ignored. The deflation layer 40 may be a compound semiconductor layer or a nitride layer. In this case, the compound semiconductor layer may be doped with a p-type doping material, for example, may be any one of a GaN layer, AlGaN layer, AlInN layer, AlInGaN layer and InGaN layer. In the compound semiconductor layer, the InGaN layer may not include a doping material. In the case of the nitride layer of the deflation layer 40, the deflation layer 40 may be, for example, an InN layer. In this case, the InN layer may be doped with a p-type doping material, but may not include such a doping material. Magnesium (Mg) may be used as the p-type doping material, but is not limited thereto. The deflation layer 40 may also include a p-type semiconductor layer or a dielectric layer.

 The depletion layer 40 may include 2-Dimensional Hole Gas (2DHG) G2 according to a difference in polarization rate from the first channel supply layer 36. The second channel supply layer 38 may also influence the formation of 2DHG (G2). 2DHG (G2) is present near the interface between the second channel supply layer 38 and the depletion layer 40. When 2DEG (G1) is removed, when 2DHG (G2) is removed together, the space charge of the HEMT of FIG. 1 becomes overall neutral. Therefore, the HEMT of FIG. 1 may be a super junction HEMT having a much higher breakdown voltage.

Subsequently, the source electrode 42S and the drain electrode 42D are formed on the region where the second channel supply layer 38 is not formed in the first channel supply layer 36. The source electrode 42S and the drain electrode 42D face each other with the depletion region A1 interposed therebetween. The depletion region A1 of the channel layer 34 may be closer to the source electrode 42S than the drain electrode 42D. The source electrode 42S and the drain electrode 42D are in contact with the second channel supply layer 38 and the depletion layer 40.

Although not shown in the drawing, portions formed under the source electrode 42S and the drain electrode 42D in the first channel supply layer 36 are removed, so that the source electrode 42S and the drain electrode 42D are formed as the channel layer ( 34) may be formed. This case can also be applied to other embodiments to be described below.

 1, there is a gate electrode 44 on the depletion layer 40. The gate electrode 44 may be positioned on the depletion region A1 of the channel layer 34. Gate 44 may be a metal gate or a nitride gate. When the gate 44 is a metal gate, the gate 44 forms a Schottky contact with the first metal or deflation layer 40 which forms an ohmic contact with the depletion layer 40. It may be formed of a second metal. The first metal is a metal having a work function of 4.5 eV or more, and may be, for example, any one of nickel (Ni), iridium (Ir), platinum (Pt), and gold (Au). The second metal is a metal having a work function of less than 4.5 eV, and may be, for example, any one of titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), and tungsten (W). When the gate 44 is a nitride gate, the gate 44 may be formed of transition metal nitride. The transition metal nitride may be, for example, TiN, TaN or WN. In addition, the gate 44 may be a gate formed of polysilicon or germanium (Ge) including conductive impurities.

On the other hand, as shown in FIG. 2A, the depletion layer 40A may be spaced apart from the source electrode 42S and the drain electrode 42D. As shown in FIG. 2B, the depletion layer 40B may be spaced apart from the source electrode 42S and may not be spaced apart from the drain electrode 42D. In addition, as illustrated in FIG. 2C, the depletion layer 40C may be spaced apart from the drain electrode 42D and may not be spaced apart from the source electrode 42S. The source electrode 42S and the drain electrode 42D may include at least one metal or metal nitride, for example, Au, Ni, Pt, Ti, Al, Pd, Ir, W, Mo, Ta, Cu, It may include at least one of TiN, TaN and WN. The source electrode 42S and the drain electrode 42D are not limited to this.

 In addition, as shown in FIG. 3, an insulating layer 46 may be further provided between the gate 44 and the depletion layer 40 to prevent a leakage current. The insulating layer 46 may be a silicon oxide layer or a nitride layer. The insulating layer 46 can be applied to the high electron mobility transistor shown in Figs. 2A to 2C.

4 shows a high electron mobility transistor according to another embodiment of the present invention. Only parts different from those in FIG. 1 will be described.

Referring to FIG. 4, a second deflection layer 50 is disposed on a portion of the first channel supply layer 36 to cover the deflection region A1 of the channel layer 34. The thickness of the second deflection layer 50 may be, for example, 1 nm to 100 nm. The second deflection layer 50 may be a compound semiconductor layer doped with a p-type doping material, for example, a p-type AlGaN layer. The second deflection layer 50 may also be a compound semiconductor layer in which the content of the polarization causing element is gradually changed. It may be an AlGaN layer having a p doping effect. The second deflation layer 50 may include an AlInN layer or an AlInGaN layer in addition to the AlGaN layer. The second deflation layer 50 may be provided at the same position as the second channel supply layer 38 of FIG. 1. The source electrode 42S and the drain electrode 42D exist on the region where the second depletion layer 50 does not exist on the upper surface of the first channel supply layer 36. The source electrode 42S and the drain electrode 42D may be in contact with the second deflection layer 50. The gate 44 is present on the second deflection layer 50.

Meanwhile, as shown in FIG. 5, an insulating layer 46 may be further provided between the second deflection layer 50 and the gate 44.

As shown in FIG. 24A, the depletion layer 50A may be spaced apart from the source electrode 42S and the drain electrode 42D. In addition, as illustrated in FIG. 24B, the depletion layer 50B may be spaced apart from the source electrode 42S and may not be spaced apart from the drain electrode 42D. In addition, as illustrated in FIG. 24C, the depletion layer 50C may be spaced apart from the drain electrode 42D and may not be spaced apart from the source electrode 42S.

Next, a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention will be described with reference to FIGS. 6 to 11. In this process, the same reference numerals are used for the members mentioned in the description of FIGS. 1 to 5, and related descriptions are omitted.

Referring to FIG. 6, a buffer layer 32 is formed on the substrate 30. A seed layer (not shown) may be formed between the substrate 30 and the buffer layer 32. The channel layer 34 is formed on the buffer layer 32. The channel layer 34 may be formed using an epitaxy method. The first channel supply layer 36 ′ is formed on the channel layer 34. 2DEG (G1) appears below the upper surface of the channel layer 34 according to the difference in polarization rate between the first channel supply layer 36 'and the channel layer 34. The first channel supply layer 36 ′ may be formed using an epitaxy method. When the first channel supply layer 36 'is an n-type doped material layer, for example, a silicon (Si) doped material layer, the n-type doped material is grown in a process of growing the first channel supply layer 36'. Can be formed by injection. In this case, growth of the first channel supply layer 36 ′ and injection of the n-type doping material may be performed in-situ. After forming the first channel supply layer 36 ′, a mask M1 is formed on the upper surface of the first channel supply layer 36 ′. The mask M1 is formed such that a portion A2 of the upper surface of the first channel supply layer 36 ′ is exposed. After forming the mask M1, the exposed partial region A2 of the upper surface of the first channel supply layer 36 corresponds to the depletion region A1 of the channel layer 34 of FIG. 1. After forming the mask M1, the exposed region A2 of the upper surface of the first channel supply layer 36 ′ is removed. Subsequently, the mask M1 is also removed.

In this way, as shown in FIG. 7, the partial area A3 of the upper surface of the channel layer 34 is exposed. A first channel supply layer 36 ″ spaced apart from the partial region A3 is formed. In the first channel supply layer 36 ′ of FIG. 6, the exposed region A3 of the channel layer 34 is formed. 2DEG G1 disappears from the exposed area A3 of the channel layer 34 as the portion formed on the channel layer 34. The exposed area A3 of the channel layer 34 is represented by the depletion area (Fig. 1). This corresponds to A1).

The partial region A2 of the first channel supply layer 36 ′ of FIG. 6 may be removed by anisotropic dry etching, by which etching of the surface of the exposed region A3 of the upper surface of the channel layer 34 occurs. Roughness can be large. Therefore, the resultant of FIG. 7 is wet etched to reduce the surface roughness of the exposed area A3 of the upper surface of the channel layer 34. In this case, TMAH or KOH is used as a wet etching etchant. The surface roughness rms of the exposed region A3 of the channel layer 34 by the wet etching may be reduced to a level similar to that before the anisotropic dry etching of the first channel supply layer 36 ′ of FIG. 6. For example, the surface roughness of the upper surface of the channel layer 34 before the anisotropic dry etching is about 1 angstrom, and after the anisotropic dry etching, the exposed area A3 of the upper surface of the channel layer 34. ), The surface roughness increases to about 2 mm 3. However, after the wet etching, the surface roughness of the exposed area A3 is again reduced to about 1 GPa.

Next, referring to FIG. 8, after the wet etching, the second channel supply layer 38 ′ covering the exposed area A3 of the upper surface of the channel layer 34 on the first channel supply layer 36 ″. The second channel supply layer 38 'may be formed by an epitaxy method. The second channel supply layer 38' may be formed in the same composition as the first channel supply layer 36 ". However, the content of one component in the composition may be different from that of the first channel supply layer 36 ". For example, the second channel supply layer 38 'may be made of AlGaN like the first channel supply layer 36". The layer may be formed by growing the Al content to be smaller than the first channel supply layer 36 ". The exposed region A3 and the first channel supply layer 36 of the channel layer 34 may be formed. There is a step between "). This step is also transferred to the second channel supply layer 38 'as it is. Accordingly, after the second channel supply layer 38 ′ is formed, the second channel supply layer 38 ′ is formed in a recessed shape on the exposed region A3 of the channel layer 34. After the second channel supply layer 38 ′ is formed, a second channel due to a polarization difference between the second channel supply layer 38 ′ and the channel layer 34 is exposed in the exposed region A3 of the channel layer 34. 2EDG (G3) may appear. The density of the second 2DEG (G3) is lower than the 2DEG (G1) appearing in the channel layer 34 below the first channel supply layer 36 "by the first channel supply layer 36".

Next, referring to FIG. 9, a depletion layer 40 ′ is formed on the second channel supply layer 38 ′. The depletion layer 40 ′ may be formed by an epitaxy method. The recessed form of the second channel supply layer 38 'is also transferred to the depletion layer 40'. Accordingly, the depletion layer 40 ′ is formed in a recessed shape on the exposed region A3 of the channel layer 34. The second 2DEG G3 appearing in the exposed area A3 of the channel layer 34 disappears as the depletion layer 40 'is formed.

The mask M2 is formed on the depletion layer 40 '. The mask M2 covers a partial region of the depletion layer 40 ′ corresponding to the depletion region A3 of the channel layer 34 and the region around it. An area in which the source and drain electrodes are to be formed may be defined by the mask M2.

Referring to FIG. 10, the depletion layer 40 and the second channel supply layer 38 ″ around the mask M2 are sequentially etched to form the depletion layer 40 and the second channel supply layer 38. Such etching may be performed until the top surface of the first channel supply layer 36 is exposed, and after etching, the mask M2 is removed, and a portion of the first channel supply layer 36 is removed. The etching may expose the first region 36A and the second region 36B of the upper surface of the first channel supply layer 36. The first and second regions 36A and 36B may be exposed. They are spaced apart and face each other with the depletion region A3 of the channel layer 34. The first region 36A may be closer to the depletion region A3 than the second region 36B. A source electrode 42S is formed on the first region 36A and a drain electrode 42D is formed on the second region 36B as shown in Fig. 11. These source and drain electrodes 42S and 42D are formed. 10 texture Before the mask M2 is removed, the electrode material layer (not shown) is formed on the first and second regions 36A and 36B and the mask M2, and then the mask M2 is removed in a lift-off manner. Can be formed.

Referring to FIG. 11, the source electrode 42S and the drain electrode 42D are in contact with the second channel supply layer 38 and the depletion layer 40.

Meanwhile, in the etching where the upper surface of the first channel supply layer 36 of FIG. 10 is exposed, the etching may be performed until the channel layer 34 is exposed. In this case, the source electrode 42S and the drain electrode 42D may be formed on the channel layer 34.

Referring to FIG. 12, a gate 44 is formed on the depletion layer 40. An insulating layer (gate insulating film) (not shown) may be further formed between the gate 44 and the depletion layer 40.

Next, a method of manufacturing the HEMT illustrated in FIG. 2A will be described with reference to FIGS. 13 to 18. Only parts different from the manufacturing method described with reference to FIGS. 6 to 12 will be described.

Referring to FIG. 13, the process of forming the buffer layer 32, the channel layer 34, the first channel supply layer 36, and the second channel supply layer 38 on the substrate 30 is described with reference to FIGS. 6 to 8. It may be the same as the process described in.

A depletion layer 40A is formed on the second channel supply layer 38 to cover the recessed portion of the second channel supply layer 38 and a portion thereof. At this time, the area of the second channel supply layer 38 covered by the deflation layer 40A is smaller than the area of the second channel supply layer 38 covered by the deflation layer 40 in FIG. 10. In other words, the size of the deflation layer 40A of FIG. 13 is smaller than that of the deflation layer 40 of FIG. 10.

Referring to FIG. 14, a mask M3 is formed on the second channel supply layer 38 to cover the deflation layer 40A and to cover a portion of the second channel supply layer 38 around the deflection layer 40A. Next, the second channel supply layer 38 around the mask M3 is etched to expose the first channel supply layer 36 as shown in FIG. 15. After the first channel supply layer 36 is exposed, the exposed portion of the first channel supply layer 36 may be further etched within a range of thicknesses.

Referring to FIG. 16, the conductive layer 42 is formed on the exposed region of the first channel supply layer 36. The conductive layer 42 may be a material forming the source and drain electrodes 42S and 42D. The conductive layer 42 is also formed on the mask M3. After the conductive layer 42 is formed, the mask M3 is removed. In the process of removing the mask M3, the portion formed on the mask M3 of the conductive layer 42 is also removed. After the mask M3 is removed, the conductive layer 42 remaining on both sides of the depletion layer 40A is used as the source electrode 42S and the drain electrode 42D, as shown in FIG. In FIG. 16, the depletion layer 40A and the conductive layer 42 are spaced apart by the mask M3. Therefore, after the mask M3 is removed, the depletion layer 40A and the source and drain electrodes 42S and 42D are spaced apart as shown in FIG. 17. After the mask M3 is removed, the gate 44 is formed on the depletion layer 40A as shown in FIG. 18.

Next, a method of manufacturing the HEMT shown in FIG. 4 will be described with reference to FIGS. 19 to 22. Only parts different from the above-described manufacturing method will be described.

Referring to FIG. 19, a second deflection layer 50 ′ is formed on the first channel supply layer 36 to cover the exposed area A3 of the upper surface of the channel layer 34. The second deflation layer 50 may be formed by epitaxy. The portion of the second deflection layer 50 formed on the exposed region A3 of the channel layer 34 becomes recessed due to the step of the first channel supply layer 36. The mask M4 is formed on the second deflection layer 50 '. The mask M4 covers the recessed portion of the second deflection layer 50 'and surrounds it to define a region in which the source and drain electrodes are to be formed in the second deflection layer 50'. After forming the mask M4 as described above, the exposed portion of the second deflection layer 50 around the mask M4 is etched as shown in FIG. 20. This etching is performed until the first channel supply layer 36 is exposed.

Referring to FIG. 21, a conductive layer 42 is formed on a region of the first channel supply layer 36 exposed in the etching. The conductive layer 42 is also formed on the mask M4. When the mask M4 is removed after the conductive layer 42 is formed, the conductive layer 42 formed on the mask M4 is removed together with the mask M4. In this way, the conductive layer 42 remains only on the first channel supply layer 36. The conductive layer 42 remaining on the first channel supply layer 36 on both sides of the second depletion layer 50 is used as the source electrode 42S and the drain electrode 42D. The conductive layer 42 remaining on the first channel supply layer 36 is in contact with the side of the second deflection layer 50.

After removing the mask M4, a gate 44 is formed on the second deflection layer 50 as shown in FIG. 22.

Meanwhile, after removing the mask M4 in FIG. 20, another mask covering the second depletion layer 50 may be formed, and then a subsequent process may be performed. Thus, the source and drain electrodes 42S and 42D may be formed. The second deflection layer 50 may form a HEMT spaced apart from each other.

23 shows that the channel layer 34 is a GaN layer, the first channel supply layer 36 is an Al35GaN15 layer (or an Al20GaN15 layer), the second channel supply layer 38 is an Al20GaN15 layer (or Al35GaN15 layer), and a depletion layer ( When 40) is a p-GaN layer, simulation results of the density of 2DEG (G1) and 2DHG (G2) between the measured gate 44 and the source and drain electrodes 42S and 42D are shown.

In FIG. 23, the first peak P1 represents 2DEG density, and the second peak P2 represents 2DHG density.

Referring to FIG. 23, when the compositions of the first and second channel supply layers 36 and 38 are the same, it is found that the density of 2DEG and 2DHG is higher than 10 ¹⁸ / cm ³ even when the composition ratio of each layer is different. Can be. Therefore, even when the compositions of the first and second channel supply layers 36 and 38 are the same, if the composition ratio of each layer is different, the 2DEG density is high in the channel layer 34 between the gate 44 and the drain electrode 42D. It can be seen that the 2DHG density can also be maintained in the depletion layer 40 between the gate 44 and the drain electrode 42D.

25A shows a HEMT according to another embodiment of the present invention.

Referring to FIG. 25A, the HEMT includes a source electrode 110, a gate electrode 112, and a drain electrode 114 formed spaced apart from the substrate 105. The depletion layer 104 is formed on the gate electrode 112. The first channel supply layer 103 is on the side of the depletion layer 104. The channel layer 102 and the passivation layer 101 are formed on the first channel supply layer 103 and the deflation layer 104.

As shown in FIG. 25A, the first channel layer 102 includes an interface depletion region A1 with the depletion layer 104, and with the first channel supply layer 103 including 2DEG. The interface G1 may be included at the interface.

25B shows a HEMT according to another embodiment of the present invention. Only parts different from the HEMT shown in FIG. 25A will be described.

As shown in FIG. 25B, a second channel supply layer 106 is included between the depletion layer 107 and the first channel supply layer 103 instead of the depletion layer 104.

26A to 26G show step by step a method of manufacturing HEMT according to another embodiment of the present invention.

Referring to FIG. 26A, an electrode layer 116 is formed on the substrate 105. The substrate 105 may be, for example, a silicon substrate, a silicon carbide (SiC) substrate, or an aluminum substrate (eg, Al 2 O 3). However, the substrate 105 is not limited to this substrate. The electrode layer 116 may include metal or metal nitride. As shown in FIG. 26B, the electrode 116 is patterned into a source electrode 110, a gate electrode 112, and a drain electrode 114. As shown in FIG. 26C, the depletion layer 104 ′ is formed on the source electrode 110, the gate electrode 112, and the drain electrode 114. The deflation layer 104 ′ may include the same material as the deflation layer 50 described with reference to FIG. 4, but is not limited thereto.

Next, as illustrated in FIG. 26D, the depletion layer 104 ′ formed on the source electrode 110, the gate electrode 112, and the drain electrode 114 is etched back to depletion layer 104. ). As shown in FIG. 26E, a first channel supply layer 103 ′ is formed on the depletion layer 104. The first channel supply layer 103 may include the same material as the first channel supply layer 36 described with reference to FIG. 4, but is not limited thereto. As shown in FIG. 26F, the first channel supply layer 103 is formed by etching back the first channel supply layer 103 ′. The first channel supply layer 103 may partially expose the depletion layer 104.

Next, as shown in FIG. 26G, the channel layer 102 and the passivation layer 101 are sequentially formed on the first channel supply layer 103. The channel layer 102 may include the same material as the channel layer 34 described with reference to FIG. 4, but is not limited thereto. The passivation layer 101 may include an insulating material or an insulating polymer material, but is not limited thereto. In this case, the insulating material may be an oxide such as silicon oxide.

26A-26G show an example of a method of forming a HEMT comprising a depletion layer 104, but instead of forming the depletion layer 104, the depletion layer 107 as shown in FIG. 25B. It may be formed on the second channel supply layer 106.

Referring to FIG. 25B, the second channel supply layer 106 and the depletion layer 107 may each include the same material as the second channel supply layer 38 and the depletion layer 40 described with reference to FIG. 1. .

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

30: substrate 32: buffer layer
34: channel layer 36, 38, 50: first to third channel supply layer
40: depletion layer 42: conductive layer
42S: source electrode 42D: drain electrode
44: gate 50: second deflection layer
A1: Depletion area
A2: a partial region of the upper surface of the first channel supply layer 36
A3: partial region of the upper surface of the channel layer 34
G1: 2DEG G2: 2DHG
P1, P2: first and second peaks

Claims (37)

A substrate comprising a compound semiconductor;
A channel layer formed on the substrate, the channel layer including a 2DEG channel and a depletion region;
A first channel supply layer formed on the channel layer to correspond to the 2DEG channel;
A depletion layer formed on the depletion region of the channel layer and a partial region of the first channel supply layer;
Source and drain electrodes formed on one of the first channel supply layer and the channel layer and facing each other with the depletion region therebetween; And
And a gate formed on the depletion layer. The method of claim 1,
A second channel supply layer having a smaller polarization rate than the first channel supply layer is provided on the depletion region of the channel layer and a partial region of the first channel supply layer, and the depletion layer supplies the second channel supply layer. HEMT provided on the layer. 3. The method according to claim 1 or 2,
The source and drain electrodes are in contact with or spaced apart from the depletion layer. 3. The method according to claim 1 or 2,
HEMT further comprising an insulating layer between the gate and the depletion layer. The method of claim 1,
The depletion layer is a HEMT having a polarization rate smaller than that of the first channel supply layer and is a compound semiconductor layer doped with a p-type doping material. The method of claim 1,
The depletion layer is a compound semiconductor layer whose polarization rate is smaller than that of the first channel supply layer and whose content of the polarization-inducing main component varies depending on the thickness. The method of claim 1,
Wherein the first channel supply layer is doped with an n-type doping material and is a nitride layer including at least one of Al, Ga, and In. The method of claim 1,
The thickness of the first channel supply layer is 20nm ~ 200nm HEMT. 3. The method of claim 2,
The depletion layer is a HEMT that is a nitride layer containing at least one of Al, Ga, and In, which is doped or not doped with a p-type doping material. 3. The method of claim 2,
The first and second channel supply layers are compound semiconductor layers having the same composition and different composition ratios. 3. The method of claim 2,
The thickness of the first channel supply layer is 20nm ~ 200nm, the thickness of the second channel supply layer is HEMT. 3. The method according to claim 1 or 2,
Said gate is p-metal or nitride. 3. The method of claim 2,
The first and second channel supply layers have the same polarization rate. A channel layer comprising a 2DEG channel and a depletion region;
A first channel supply layer defining an opening that exposes the depletion region and formed on the 2DEG channel;
A depletion layer formed on the first channel supply layer and the depletion region;
Source and drain electrodes formed on the first channel supply layer and spaced apart from each other; And
A gate electrode formed on the depletion layer;
The depletion layer includes a compound semiconductor containing nitrogen (N) and containing at least one of aluminum (Al), gallium (Ga), and indium (In). 15. The method of claim 14,
And a second channel supply layer between the depletion layer and the depletion region. The method of claim 15,
And a polarization rate of the second channel supply layer is smaller than a polarization rate of the first channel supply layer. 15. The method of claim 14,
The transistor further comprises an insulating layer between the gate electrode and the depletion layer. 15. The method of claim 14,
And the depletion layer comprises a p-type dopant. 15. The method of claim 14,
And a polarization rate of the depletion layer is smaller than a polarization rate of the first channel supply layer. Board;
Source and drain electrodes formed on the substrate and spaced apart from each other;
A depletion layer formed on the gate electrode;
A first channel supply layer formed on at least a portion of the depletion layer; And
And a channel layer formed on the depletion layer and the first channel supply layer.
The channel layer includes a 2DEG channel corresponding to the first channel supply layer and a depletion region corresponding to the depletion layer. Forming a channel layer on the substrate;
Forming a first channel supply layer on the channel layer, the first channel supply layer having a higher polarization rate than the channel layer;
Removing a portion of the first channel supply layer to expose a portion of the channel layer;
Forming a depletion layer on the first channel supply layer to cover an exposed area of the channel layer;
Forming source and drain electrodes facing each other with the depletion layer therebetween on the first channel supply layer; And
Forming a gate on the depletion layer. 22. The method of claim 21,
Before forming the depletion layer, a second channel supply layer is formed on the first channel supply layer to cover an exposed area of the channel layer and has a polarization smaller than that of the first channel supply layer. Is formed on the second channel supply layer. The method of claim 21 or 22,
And forming an insulating layer between the gate and the depletion layer. 22. The method of claim 21,
The depletion layer has a polarization rate smaller than that of the first channel supply layer and is doped with a p-type doping material. 22. The method of claim 21,
The depletion layer is a compound semiconductor layer having a polarization rate smaller than that of the first channel supply layer, and the content of the polarization-inducing main component varies depending on the thickness. 22. The method of claim 21,
Wherein the first channel supply layer is doped with an n-type doping material, and is a nitride layer including at least one of Al, Ga, and In. 22. The method of claim 21,
The thickness of the first channel supply layer is 20nm ~ 200nm, the thickness of the deflection layer is 5 ~ 20nm manufacturing method of HEMT. 23. The method of claim 22,
The depletion layer is a nitride layer containing at least one of Al, Ga and In doped or doped with a p-type doping material. 23. The method of claim 22,
Wherein the first and second channel supply layers are compound semiconductor layers having the same composition and different composition ratios. 21. The method of claim 20,
The thickness of the first channel supply layer is 20nm ~ 200nm, the thickness of the second channel supply layer is 5 ~ 20nm manufacturing method of HEMT. The method of claim 21 or 22,
The gate is a method of manufacturing a HEMT p-metal or nitride. 22. The method of claim 21,
The depletion layer is a method for manufacturing a HEMT formed by epitaxy. 23. The method of claim 22,
And the second channel formation layer and the depletion layer are formed by an epitaxy method. The method of claim 21 or 22,
And the source and drain electrodes are spaced apart from the depletion layer. The method of claim 21 or 22,
And reducing surface roughness of the exposed area of the channel layer before forming the depletion layer. 36. The method of claim 35,
And wet etching the exposed region of the channel layer to mitigate the surface roughness. 23. The method of claim 22,
And a polarization rate of the first and second channel supply layers is the same.

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