KR20130038032A - Non-volatile memory device having vertical structure - Google Patents

Abstract

PURPOSE: A non-volatile memory device having a vertical structure is provided to reduce the resistance of a common source line by using the common source line made of metal silicide. CONSTITUTION: First insulating pillars(140) are vertically formed on the surface of a substrate(100). Cell string units(11) are arranged on both sidewalls of the first insulating pillars at both sides of a first part(1) of the substrate. An impurity region(150) is protruded on a second part(2) of the substrate among the cell string units. The impurity region includes a first high concentration impurity region(155), a low concentration impurity region(151), and a second high concentration impurity region(157). Spacers(170) are arranged in the sidewalls of the cell string units and the impurity region. A conductive line(180) is arranged on the exposed part of the impurity region among the spacers.

Description

Non-volatile memory device having vertical structure

The technical concept of the present invention relates to a nonvolatile memory device having a vertical structure, and more particularly to a nonvolatile memory device having a vertical channel structure for increasing the degree of integration.

As electronic products become smaller and smaller, high volume data processing is required. Accordingly, there is a need to increase the degree of integration of semiconductor memory devices used in such electronic products. As one of methods for improving the degree of integration of a semiconductor memory device, a nonvolatile memory device having a vertical transistor structure instead of a conventional planar transistor structure has been proposed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device having a vertical structure capable of improving the resistance of a common source line and simplifying a process in a nonvolatile memory device having a vertical structure.

According to one or more exemplary embodiments, a nonvolatile memory device having a vertical structure is provided. The nonvolatile memory device of the vertical structure may include: a first insulating pillar spaced apart from each other on a first portion of a substrate and extending perpendicular to a surface of the substrate; Cell string units arranged on both sidewalls of the first insulating pillar on both sides of the first portion of the substrate; An impurity region protrudingly arranged on a second portion of the substrate between the cell string units; Spacers arranged on sidewalls of the impurity region and the cell string unit to expose a portion of the impurity region; And a conductive line arranged on the exposed portion of the impurity region between the spacers.

In some embodiments of the present disclosure, the impurity region may include a low concentration impurity region arranged under the spacer of the second portion of the substrate; A first high concentration impurity region arranged between the low concentration impurity regions of the second portion of the substrate and having the same conductivity type as the low concentration impurity region; And a second high concentration impurity region arranged between the spacers and on the first high concentration impurity region and having the same conductivity type as the first high concentration impurity region.

In some embodiments of the present invention, the spacer is arranged over the sidewall of the cell string unit, and the conductive line is formed over the exposed portion of the impurity region corresponding to at least a portion of the sidewall of the cell string unit. Can be arranged to.

In some embodiments of the invention, the spacer is arranged on at least a portion of a side wall of the cell string unit, and the conductive line corresponds to at least a portion of the side wall of the cell string unit to expose the exposed portion of the impurity region. It can be arranged on a part.

According to another embodiment of the present invention, a nonvolatile memory device having a vertical structure is provided. The nonvolatile memory device of the vertical structure may include: a first insulating pillar spaced apart from each other on a first portion of a substrate and extending perpendicular to a surface of the substrate; Cell string units arranged on both sidewalls of the first insulating pillar on both sides of the first portion of the substrate; An impurity region arranged in a second portion of the substrate between the cell string units; Conductive lines protrudingly arranged on the impurity region of the second portion of the substrate; And a spacer arranged on sidewalls of the conductive line and the cell string unit so that the top surface of the conductive line is exposed.

In some embodiments of the present disclosure, the impurity region may include a low concentration impurity region arranged under the spacer of the second portion of the substrate; And a first high concentration impurity region arranged between the low concentration impurity regions of the second portion of the substrate and having the same conductivity type as the low concentration impurity region.

In some embodiments of the present invention, the conductive line may be a metal silicide layer.

In some embodiments of the present disclosure, the second insulating pillar may be further disposed on the conductive line.

In some embodiments of the present disclosure, the cell string unit may include: a channel layer surrounding a bottom and a side surface of the first insulating pillar and in contact with the first portion of the substrate; And a gate of the memory cell transistor arranged on the channel layer corresponding to both sidewalls of the first insulating pillar and arranged between the gate of the selection transistor and the gate of the selection transistor stacked vertically with respect to the surface of the substrate. It can include;

In some embodiments of the present disclosure, the conductive line may include a lower portion of the conductive line below the bottom of the gate arranged at the bottom of the gate of the memory cell transistor.

According to the nonvolatile memory device having a vertical structure according to the inventive concept, the common source line may be formed of metal silicide to reduce the resistance of the common source line, and may facilitate the process.

1 illustrates an arrangement of a memory cell array of a nonvolatile memory device having a vertical structure according to an exemplary embodiment of the present invention.
2A illustrates a schematic cross-sectional view of the nonvolatile memory device of FIG. 1 in accordance with some embodiments of the present invention.
2B illustrates a schematic cross-sectional view of the nonvolatile memory device of FIG. 1 in accordance with some embodiments of the present invention.
2C illustrates a schematic cross-sectional view of the nonvolatile memory device of FIG. 1 in accordance with some embodiments of the present invention.
2D illustrates a schematic cross-sectional view of the nonvolatile memory device of FIG. 1 in accordance with some embodiments of the present invention.
3 to 15 are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 2A according to an embodiment of the present invention.
16 to 18 are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 2A according to another exemplary embodiment of the present invention.
19 is a schematic block diagram of a nonvolatile memory device according to another embodiment of the present invention.
20 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.
21 is a block diagram illustrating an electronic system according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as limited by the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art. Therefore, the shapes and the like of the elements in the drawings are exaggerated in order to emphasize a clearer description, and elements denoted by the same symbols in the drawings denote the same elements.

1 illustrates an arrangement of a memory cell array of a nonvolatile memory device having a vertical structure according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the memory cell array 10 may include a plurality of NAND cell string units 11. The plurality of cell string units 11 may be arranged in a matrix form of columns and rows. The memory cell block 13 may include a plurality of cell string units 11 arranged in the same column (X direction) and / or the same row (Y direction).

Each cell string unit 11 may include a plurality of memory cells MC1-MCn, a string selecting transistor SST, and a ground selecting transistor GST. The ground select transistors GST, the plurality of memory cells MC1-MCn and the string select transistors SST constituting each of the cell string units 11 may be vertically arranged in a Z direction.

Bit lines BL1-BLm are connected to one side of the cell string unit 11 arranged in each of the memory cell blocks 13, for example, the drain of the string select transistor SST, and the cell string unit 11 A source of the other side, for example, the ground select transistor GST, may be commonly connected to a common source line CSL.

The memory cells MC1-MCn may be arranged in series between the string select transistor SST and the ground select transistor GST. Word lines WL1 -WLn may be commonly connected to gates of memory cells arranged on the same layer among the memory cells MC1 -MCn. As the word lines WL1 -WLn are driven, data may be programmed, read, and erased in the memory cells MC1 -MCn.

The string select transistor SST may be arranged between the bit lines BL1 -BLm and the memory cell MCn. The string selection transistors SST arranged in each of the memory cell blocks 13 are connected to the bit lines BL1-BLm and the memory cell transistors by string selection lines SSL1 and SSL2 connected to gates. Data transmission between (MC1-MCn) can be controlled.

In FIG. 1, a single transistor is arranged as a string select transistor SST, but a pair of transistors are arranged in series between the bit lines BL1-BLm and the memory cell transistors MC1-MCn, and the pair The string select lines SSL1 and SSL2 may be commonly connected to a gate of a transistor of.

The ground select transistor GST may be arranged between the memory cell transistors MC1-MCn and the common source line CSL. The ground selection transistors GST arranged in the memory cell block 13 are connected to the gates of the memory cell transistors MC1-MCn and the common source line by ground selection lines GSL1 and GSL2. Data transmission between (CSL) can be controlled.

In FIG. 1, a single transistor is arranged as a ground select transistor GST, but a pair of transistors are arranged in series between the memory cell transistors MC1-MCn and the ground select line GSL, and the pair of transistors are arranged in series. The string select line GSL may be commonly connected to a gate of the gate.

2A illustrates a schematic cross-sectional view of the nonvolatile memory device of FIG. 1 in accordance with some embodiments of the present invention. FIG. 2A is a schematic cross-sectional view in the longitudinal direction of the bit lines BL1-BLm of FIG. 1.

Referring to FIG. 2A, the nonvolatile memory device may include a substrate 100.

The substrate 100 may include a semiconductor substrate, for example, a group IV semiconductor substrate, a group III-V compound semiconductor substrate, or a group II-VI oxide semiconductor substrate. For example, the group IV semiconductor substrate may comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may include a bulk wafer or an epitaxial layer.

A first insulating pillar 140 extending perpendicular to the surface of the substrate 100 may be arranged on the first portion 1 of the substrate 100.

The first insulating pillar 140 may include Undoped Silica Glass (USG), Spin On Glass (SOG), or Tonen SilaZene (TOSZ). The cell string unit 11 may be vertically arranged along the side surface of the first insulating pillar 140. A channel layer 130 may be arranged to surround the bottom and side surfaces of the first insulating pillar 140 and contact the first portion 1 of the substrate 100. The channel layer 130 may include a semiconductor layer, for example, undoped polysilicon.

The cell string unit 11 may be arranged on the channel layer 130 arranged on the sidewall of the first insulating pillar 140. Each cell string unit 11 is arranged perpendicular to the surface of the substrate 100 and is arranged between the ground select transistor GST, the string select transistor SST, and the select transistors GST and SST. It may include transistors MC1-MCn.

The ground select line GSL may be connected to the gate 163 of the ground select transistor GST. The string select line SSL may be connected to the gate 167 of the string select transistor SST. Word lines WL1 -WLn may be connected to gates 165 of the memory cell transistors MC1 -MCn.

The gates 163, 165, and 167 may include metal layers. The metal film may include a tungsten film. The gates 163, 165, and 167 may further include a barrier layer. The barrier layer may include one layer selected from WN, TaN, or TiN.

Gate insulating layers 161 may be further disposed on the bottom and side surfaces of the gates 163, 165, and 167 to surround the gates 163, 165, and 167. Although not shown in the drawing, the gate insulating layer 161 may include a charge tunneling layer, a charge storage layer, and a charge blocking layer.

The charge tunneling layer may tunnel the charge into the charge storage layer in an F-N manner.

The charge storage layer may store charge in a charge trap type.

The charge blocking layer may include a high-k dielectric material.

The gate insulating layer 161 may include oxide-nitride-alumina (ONA) or oxide-nitride-oxide-alumina (ONOA).

An insulating layer 110 is formed on the channel layer 130 between the adjacent gates 163, 165, and 167 and the gate 167 of the string select transistor SST in a direction perpendicular to the surface of the substrate 100. This can be arranged. The insulating film 110 may include an oxide film or a nitride film.

Impurity regions 150 are arranged on the second portion 2 and the second portion 2 of the substrate 100 between the cell string units 11 arranged on the sidewalls of the first insulating pillar 140. Can be.

The impurity region 150 may include a first high concentration impurity region 155, a low concentration impurity region 151, and a second high concentration impurity region 157.

That is, the impurity region 150 is formed on the first high concentration impurity region 155, the low concentration impurity region 151 arranged on both sides of the first high concentration impurity region 155, and the first high concentration impurity region 155. And a second high concentration impurity region 157 formed on the substrate 100 to protrude onto the substrate 100.

The conductivity type of the first high concentration impurity region 155 and the second high concentration impurity region 157 may be N + type, and the conductivity type of the low concentration impurity region 151 may be N-type.

The second high concentration impurity region 157 fills the doped impurities with N + to fill the spacers 170 on the second portion 2 of the substrate 100 and etches the impurities through an etch back process. Can be formed.

Alternatively, a region protruding on the second portion 2 of the substrate 100 may be formed on the first high concentration impurity region 155 by using an selective etchant growth method, and an ion implantation process may be performed to form a first region. 2 high concentration impurity region 157 can be formed.

Alternatively, the undoped silicon is buried between the spacers 170, a region protruding on the second portion 2 of the substrate 100 is formed through an etch back process, and then a second ion implantation process is performed. The high concentration impurity region 157 may be formed.

The second high concentration impurity region 157 is formed to protrude on the second portion 2 of the substrate 100, thereby forming a junction leakage current in the process of forming a conductive line 180, that is, a metal silicide layer. leakage can be prevented.

In addition, since the metal silicide layer can be formed thick, the resistance of the conductive line 180 can be improved.

The impurity region 150 may serve as a common source region electrically connected to the common source line CSL of FIG. 1.

A spacer 170 may be arranged on the second portion 2 of the substrate 100 corresponding to the low concentration impurity region 151 of the impurity region 150.

The spacer 170 may include a silicon nitride film.

A conductive line 180 may be arranged on the second portion 2 of the substrate 100 between the spacers 170 to be electrically connected to the second high concentration impurity region 157.

The conductive line 180 may function as a common source line CSL. The conductive line 180 is formed on the second high concentration impurity region 157 and may include metal silicide. The metal silicide may be formed using cobalt (Co), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), or the like. .

According to the exemplary embodiment of the present invention, the conductive line 180 may be formed of metal silicide, thereby not only reducing the resistance of the conductive line 180 itself, but also forming the conductive line 180 on the first high concentration impurity region 155. Since the high concentration impurity region 157 can be easily formed, the conductive line 180 can be easily formed.

In addition, the conductive line 180 may serve as a drain region of the string select transistor SST.

The top surface of the conductive line 180 may be formed to be lower than the bottom surface of the gate 165 arranged closest to the substrate among the gates 165 of the memory cell transistors MC1-MCn to which a relatively high voltage is applied. have.

The spacer 170 may be arranged to completely cover the exposed side surfaces of the insulating layer 110, the gates 163, 165, and 167 and the gate insulating layer 161.

A second insulating pillar 175 extending perpendicular to the surface of the substrate 100 may be arranged on the conductive line 180 between the spacers 170.

The second insulating pillar 175 may include an oxide-based interlayer insulating layer, for example, a BPSG layer.

A conductive layer 135 may be further arranged on the first insulating pillar 140. A trench 125 may be arranged in a portion of the first insulating pillar 140, and a conductive layer 135 may be buried in the trench 125. The conductive layer 135 may include a doped polysilicon layer. The bit line 190 may be arranged on the substrate 100. The bit line 190 may be formed to contact the channel layer 130 and the conductive layer 135.

2B illustrates a schematic cross-sectional view of the nonvolatile memory device of FIG. 1 in accordance with another embodiment of the present invention. In FIG. 2A, the overlapping description will be omitted.

The nonvolatile memory device of the present exemplary embodiment may be formed such that the spacers 170 are arranged only on the side surfaces of the conductive lines 180.

In addition, the second insulating pillar 175 may be arranged on the spacer 170 and the conductive line 180.

2C is a schematic cross-sectional view of the nonvolatile memory device of FIG. 1 in accordance with another embodiment of the present invention. In FIG. 2A, the overlapping description will be omitted.

In the nonvolatile memory device of the present exemplary embodiment, an impurity region 150 ′ is arranged in the second portion 2 of the substrate 100, and a conductive line 180 is arranged to protrude on the impurity region 150 ′.

Unlike the FIG. 2A, the conductive line 180 protruding on the second portion 2 may extend to the lower portion of the second portion 2 and the spacer 170 of the substrate 100.

FIG. 2D illustrates a schematic cross-sectional view of the nonvolatile memory device of FIG. 1 in accordance with another embodiment of the present invention. FIG. In FIG. 2A and FIG. 2B, the above description will be omitted.

In the nonvolatile memory device of the present exemplary embodiment, an impurity region 150 ′ is arranged in the second portion 2 of the substrate 100, and a conductive line 180 is arranged to protrude on the impurity region 150 ′.

Conductive lines 180 protruding on the second portion 2 may be arranged to extend to the lower portion of the second portion 2 and the spacer 170 of the substrate 100, unlike FIG. 2B.

3 to 15 are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 2A according to an embodiment of the present invention.

Referring to FIG. 3, the sacrificial layer 105 and the insulating layer 110 may be sequentially stacked on the substrate 100. The sacrificial layer 105 may be arranged on the lowermost portion and formed on the substrate 100. The insulating layer 110 may be arranged at the top. The sacrificial layer 105 may be stacked corresponding to the number of the selection transistors SST and GST and the memory cell transistors MC1 to MCn constituting the cell string unit 11 of FIGS. 1 and 2A.

The sacrificial layer 105 may include a material having an etching selectivity with respect to the insulating layer 110. The insulating layer 110 may include a silicon oxide layer, and the sacrificial layer 105 may include a silicon nitride layer. Alternatively, the insulating layer 110 may include a silicon nitride layer, and the sacrificial layer 105 may include a silicon oxide layer.

Referring to FIG. 4, a mask pattern (not shown) for defining a channel region may be formed on the substrate 100. The sacrificial layer 105 and the insulating layer 110 are etched using the mask pattern to form a first opening 121 defining the channel region over the sacrificial layer 105 and the insulating layer 110. can do. The first opening 121 may expose the first portion 1 of the substrate 100. Next, the mask pattern may be removed. The first portion 1 of the substrate 100 in the first opening 121 may be further etched by a predetermined thickness.

Referring to FIG. 5, the channel layer 130 may be formed on the bottom and side surfaces of the first opening 121. The channel layer 130 may be formed to contact the exposed first portion 1 of the substrate 100 through the first opening 121. The channel layer 130 may include a semiconductor layer. The channel layer 130 may be formed on the bottom and side surfaces of the first opening 121 by depositing and patterning an undoped polysilicon film on the first opening 121 and the top insulating layer 110. have.

The interlayer insulating film is deposited on the substrate 100 to completely fill the first opening 121, and the interlayer insulating film is etched through a CMP or etch back process to fill the first opening 121. The first insulating pillar 140 may be formed on the layer 130. The first insulating pillar 140 may include an oxide film such as USG, TOSZ, SOG, or the like.

Next, the first insulating pillar 140 is etched by a predetermined thickness to form the trench 125, and the conductive layer 135 is formed in the trench 125.

The conductive layer 135 may be formed by depositing an N + -type polysilicon layer on the substrate 100 so that the trench 125 is embedded and etching through an etch back or CMP process.

Referring to FIG. 6, a photoresist (not shown) may be formed on the uppermost insulating layer 110, the channel layer 130, and the conductive layer 135. The photoresist may expose a portion of the uppermost insulating layer 110 corresponding to the second portion 2 of the substrate 100.

The second portion 2 of the substrate 100 may include a portion where a common source region between the first insulating pillars 140 is to be formed. By using the photoresist as a mask, the insulating layer 110 and the sacrificial layer 105 may be etched to form a second opening 123 exposing the second portion 2 of the substrate 100. . As the second openings 123 are formed, side surfaces of the sacrificial layer 105 and the insulating layer 110 may be exposed.

Referring to FIG. 7, an N-type impurity is ion-implanted into the second portion 2 of the substrate 100 exposed through the second opening 123 to form a gap between the first insulating pillars 140. A low concentration impurity region 151 may be formed in the second portion 2 of the substrate 100.

Referring to FIG. 8, the sacrificial layer 105 exposed by the second opening 123 may be removed. The sacrificial layer 105 may be removed through a wet etching process. As the sacrificial layer 105 is removed, a side opening 127 extending from the side surface of the second opening 123 may be formed. The side opening 127 may expose a portion of the channel layer 130 and the third portion 3 of the substrate 100 on both sides of the low concentration impurity region 151. The side opening 127 may define a gate formation region to be formed in a subsequent process.

9, the channel layer 130, the insulating layer 110, and the second portion 2 of the substrate 100 exposed by the side opening 127 and the second opening 123. And a dielectric film (not shown) on the third portion 3. A conductive film (not shown) may be formed on the dielectric layer (not shown) to completely fill the side opening 127 and the second opening 123.

The dielectric layer (not shown) and the conductive layer (not shown) in the second opening 123 are etched through an etch back process to form a gate dielectric layer 161 and a gate 163 arranged in the side opening 127. 165, 167 may be formed. The gate dielectric layer 161 is arranged on the bottom and side surfaces of the side opening 127, and the gates 163, 165, and 167 are completely buried in the side opening 127. Can be formed.

The gate 163 arranged at the bottom includes the gate of the ground select transistor GST of the cell string unit 11 of FIG. 1, and the gate 167 arranged at the top includes the gate of the string select transistor SST. can do. The gate 165 arranged between the gates 163 and 167 may include a control gate of the memory cell transistors MC1-MCn.

Each gate dielectric layer 161 may include a tunneling layer, a charge storage layer, and a charge blocking layer. Each gate dielectric layer 160 may include ONA or ONOA.

The gates 163, 165, and 167 may include a metal film such as a tungsten film.

Referring to FIG. 10, a spacer 170 arranged on the sidewall of the second opening 123 may be formed on the second portion 2 of the substrate 100.

The spacer 170 may be arranged to cover side surfaces of the insulating layer 110, the gate insulating layer 161, and the gates 163, 165, and 167 exposed by the second opening 123. The spacer 170 may be formed by depositing an insulating film (not shown) on the uppermost insulating film 110 including the second opening 123 and then etching the insulating film through an etch back process or the like. The insulating layer for forming the spacer 170 may include a silicon nitride layer.

Referring to FIG. 11, an N + type impurity is ion-implanted into the second portion 2 of the substrate 100 exposed through the second opening 123 to form a first high concentration impurity region 155. have.

The first high concentration impurity region 155 may be arranged in the second portion 2 of the substrate 100 between the cell string units 11. The first high concentration impurity region 155 may be formed such that the low concentration impurity regions 151 are arranged at both sides thereof.

Referring to FIG. 12, a high concentration impurity may be embedded in the second opening 123 to form a second high concentration impurity region 157 on the first high concentration impurity region 155. The second high concentration impurity region 157 may be silicon or polysilicon doped with n +.

Referring to FIG. 13, an etch back process is performed such that the second high concentration impurity region 157 protrudes to a predetermined height on the second portion 2 of the substrate 100.

The first high concentration impurity region 155, the low concentration impurity region 151, and the second high concentration impurity region 157 may serve as a common source region.

Referring to FIG. 14, a conductive line 180 may be formed on the second high concentration impurity region 157 that protrudes onto the substrate 100 in the spacer 170.

In detail, a metal layer (not shown) for forming the conductive line 180 may be formed on the entire surface of the second high concentration impurity region 157, the spacer 170, and the substrate 100.

The metal layer (not shown) may be any one of cobalt (Co), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), molybdenum (Mo), tantalum (Ta), or tungsten (W). It may include. The metal layer (not shown) may have a thickness in the range of, for example, 100 kPa to 400 kPa.

Optionally, a gapping film (not shown) may be formed over the metal layer (not shown). The capping film may maintain the thermal stability of the lower structure of the metal layer (not shown) during the silicide reaction, and may prevent oxidation of the metal layer (not shown).

Next, a heat treatment process is performed to form a conductive line 180, that is, a metal silicide layer, on the second high concentration impurity region 157.

The conductive line 180 is a group of cobalt (Co), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), molybdenum (Mo), tantalum (Ta), and tungsten (W). It may include at least one metal silicide selected from.

For example, when the metal layer (not shown) is titanium (Ti) or cobalt (Co), the first heat treatment at a temperature of 350 ℃ to 600 ℃, and second heat treatment again at a temperature of 500 ℃ to 900 ℃ stable phase (phase) metal silicide may be formed.

When the metal layer (not shown) is nickel (Ni) or a nickel alloy, a stable phase metal silicide may be formed by only one heat treatment step of 350 ° C to 650 ° C.

Next, an unreacted metal layer (not shown), for example, a sidewall of the spacer 170 and a metal layer (not shown) on the uppermost insulating layer 110 are removed by an etching method. In this case, the above-described secondary heat treatment of titanium (Ti) or cobalt (Co) may be performed after the etching step.

As in this step, the conductive line 180 formed without the photolithography process may be referred to as self-aligned silicide or salicide in that it has a self-aligned structure. The conductive line 180 may function as a common source line.

In addition, by forming the second high concentration impurity region 157 protruding onto the second portion 2 of the substrate 100 and forming the conductive line 180 thereon, a metal silicide layer is formed inside the substrate. Junction leakage can be prevented.

In addition, since the metal silicide layer may be formed thick, the resistance of the conductive line 180 may be improved, and the characteristics of the nonvolatile memory device may be improved.

In addition, since the conductive line 180 may function as a common source line, it is not necessary to form a separate metal layer on the conductive line 180, thereby simplifying the process and reducing the process cost.

In addition, by using the metal silicide as the conductive line 180 instead of the metal layer, a process of depositing a metal and etching back through anisotropic etching to form the conductive line can be omitted.

In addition, although the conductive line 180 formed on the second high concentration impurity region 157 is illustrated in FIG. 14, the conductive line illustrated in FIG. 180 may be formed.

Referring to FIG. 15, a second insulating pillar 175 is formed on the conductive line 180 to completely fill the second opening 123.

In order to form the second insulating pillar 175, an oxide film (not shown) such as BPSG is deposited on the uppermost insulating layer 110 so that the second opening 123 is embedded. Next, a second insulating pillar 175 may be formed on the oxide layer through an etch back or a CMP process.

Next, a bit line forming process may be performed on the uppermost insulating layer 110 to perform contact with the channel layer 130 and the conductive layer 135.

16 to 18 are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 2A according to another exemplary embodiment of the present invention. The overlapping descriptions described above with reference to FIGS. 3 to 15 will be omitted.

16 and 17, in order to form the second high concentration impurity region 157, the protruding region 157 a is formed on the first high concentration impurity region 155 using a selective epitaxial growth method.

Alternatively, the second opening 123 may be filled with a semiconductor material, and a protruding region 157a protruding from the substrate 100 may be formed on the first high concentration impurity region 155 through an etch back process.

Next, an N + type impurity is ion implanted into the protruding region 157a to form a second high concentration impurity region 157.

10 and 17, a protruding region is formed on the low concentration impurity region 151 formed in the second portion 2 of the substrate 100 by using the selective epitaxial growth method, and the protruding region is formed on the protruding region. N + -type impurities are ion-implanted to form a first high concentration impurity region 155 and a second high concentration impurity region 157 protruding onto the second portion 2 in the second portion 2 of the substrate 100. It may be. In addition, although the first high concentration impurity region 155 and the second high concentration impurity region 157 have been described above through separate processes, the present invention is not limited thereto, and the second high concentration impurity region 157 is formed. In the ion implantation process, the first high concentration impurity region 155 may also be formed at the same time.

Next, the conductive line 180, that is, the metal silicide layer is formed on the second high concentration impurity region 157. Since the method of forming the conductive line 180 is the same as the method described above with reference to FIG. 14, a description thereof will be omitted.

Referring to FIG. 18, a second insulating pillar 175 is formed on the conductive line 180 to completely fill the second opening 123.

The second insulating pillar 175 deposits an oxide film (not shown), such as BPSG, on the insulating film 110 so that the second opening 123 is embedded, and etches the oxide film through an etch back or CMP process. Can be formed.

Next, a bit line forming process may be performed to form a bit line 190 (see FIG. 2A) contacting the channel layer 130 and the conductive layer 135 on the uppermost insulating layer 110.

In the nonvolatile memory device according to the present embodiment, a second high concentration impurity region 158 protruding from the second portion 2 of the substrate 100 is formed, and the second high concentration impurity region 158 is electrically conductive. Forming a line 180 can simplify the process. In addition, since the resistance of the conductive line 180 may be improved by using the metal silicide layer as the conductive line 180, the characteristics of the nonvolatile memory device may be improved.

19 is a schematic block diagram of a nonvolatile memory device according to another embodiment of the present invention.

Referring to FIG. 19, in the nonvolatile memory device 700, the NAND cell array 750 may be combined with the core circuit unit 770. For example, the NAND cell array 750 may include any one of the nonvolatile memory devices described with reference to FIGS. 2A through 2D. The core circuit unit 770 may include a control logic 771, a row decoder 772, a column decoder 773, a sense amplifier 774, and a page buffer 775.

The control logic 771 may communicate with the row decoder 772, the column decoder 773, and the page buffer 775. The row decoder 772 may communicate with the NAND cell array 750 through a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. The column decoder 773 may communicate with the NAND cell array 750 through the plurality of bit lines BL. The sense amplifier 774 may be connected to the column decoder 773 when a signal is output from the NAND cell array 750, and may not be connected to the column decoder 773 when a signal is transmitted to the NAND cell array 750. .

For example, control logic 771 passes a row address signal to row decoder 772, which decodes this signal to string select line SSL, word line WL, and ground select line. The row address signal may be transferred to the NAND cell array 750 through the GSL. The control logic 771 transfers the column address signal to the column decoder 773 or the page buffer 775, and the column decoder 773 decodes the signal to pass the NAND cell array 750 through the plurality of bit lines BL. The column address signal can be transmitted to The signal of the NAND cell array 750 can be delivered to the sense amplifier 774 through the column decoder 773, amplified here and passed to the control logic 771 via the page buffer 775.

20 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.

Referring to FIG. 20, the memory card 800 may include a controller 810 and a memory 820 embedded in the housing 830. The controller 810 and the memory 820 may exchange electrical signals. For example, the memory 820 and the controller 810 may exchange data according to a command of the controller 810. Accordingly, the memory card 800 may store data in the memory 820 or output data from the memory 820 to the outside.

For example, the memory 820 may include any one of the nonvolatile memory devices described with reference to FIGS. 2A through 2D. The memory card 800 may be used as a data storage medium of various portable devices. For example, the memory card 800 may include a multimedia card (MMC) or a secure digital card (SD).

21 is a block diagram illustrating an electronic system according to an embodiment of the present invention.

Referring to FIG. 21, the electronic system 900 may include a processor 910, an input / output device 930, and a memory chip 920, which may communicate data with each other using a bus 940. have. The processor 910 may execute a program and control the electronic system 900. The input / output device 930 may be used to input or output data of the electronic system 900. The electronic system 900 may be connected to an external device, for example, a personal computer or a network, using the input / output device 930 to exchange data with the external device. The memory chip 920 may store code and data for operating the processor 910. For example, the memory chip 920 may include any one of the nonvolatile memory devices described with reference to FIGS. 2A through 2D.

The electronic system 900 may configure various electronic control devices that require the memory chip 920, and include, for example, a mobile phone, an MP3 player, navigation, and a solid state disk. : SSD), household appliances (household appliances) and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1: first part 2: second part
3: third part 11: cell string unit
100: substrate 105: sacrificial film
110: insulating film 121: first opening
123: second opening 127: side opening
130: channel layer 135: conductive layer
140: first insulating pillar 150, 150 ': impurity region
151: low concentration impurity region 155: first high concentration impurity region
157: second high concentration impurity region 161: gate dielectric film
163, 165, and 167: gate 175: second insulating pillar
180: conductive line 190: bit line

Claims (10)

A first insulating pillar spaced apart from each other on a first portion of the substrate and extending perpendicular to a surface of the substrate;
Cell string units arranged on both sidewalls of the first insulating pillar on both sides of the first portion of the substrate;
An impurity region protrudingly arranged on a second portion of the substrate between the cell string units;
Spacers arranged on sidewalls of the impurity region and the cell string unit to expose a portion of the impurity region; And
A conductive line arranged on the exposed portion of the impurity region between the spacers;
Nonvolatile memory device having a vertical structure comprising a. The method of claim 1,
The impurity region may include a low concentration impurity region arranged under the spacer of the second portion of the substrate;
A first high concentration impurity region arranged between the low concentration impurity regions of the second portion of the substrate and having the same conductivity type as the low concentration impurity region; And
A second high concentration impurity region arranged between the spacers and on the first high concentration impurity region and having the same conductivity type as the first high concentration impurity region;
Non-volatile memory device having a vertical structure comprising a. The method of claim 1,
The spacer is arranged on the entire side wall of the cell string unit,
And the conductive line is arranged on the exposed portion of the impurity region in correspondence with at least a portion of a sidewall of the cell string unit. The method of claim 1,
The spacer is arranged on at least a portion of a side wall of the cell string unit,
And the conductive line is arranged on the exposed portion of the impurity region in correspondence with at least a portion of a sidewall of the cell string unit. A first insulating pillar spaced apart from each other on a first portion of the substrate and extending perpendicular to a surface of the substrate;
Cell string units arranged on both sidewalls of the first insulating pillar on both sides of the first portion of the substrate;
An impurity region arranged in a second portion of the substrate between the cell string units;
Conductive lines protrudingly arranged on the impurity region of the second portion of the substrate; And
Spacers arranged on sidewalls of the conductive line and the cell string unit to expose an upper surface of the conductive line;
Nonvolatile memory device having a vertical structure comprising a. The method of claim 5, wherein
The impurity region may include a low concentration impurity region arranged under the spacer of the second portion of the substrate; And
A first high concentration impurity region arranged between the low concentration impurity regions of the second portion of the substrate and having the same conductivity type as the low concentration impurity region;
Non-volatile memory device having a vertical structure comprising a. 6. The method according to claim 1 or 5,
And the conductive line is a metal silicide layer. 6. The method according to claim 1 or 5,
A second insulating pillar arranged on the conductive line;
The nonvolatile memory device having a vertical structure further comprising. 6. The method according to claim 1 or 5,
The cell string unit may include a channel layer surrounding a bottom surface and a side surface of the first insulating pillar and in contact with the first portion of the substrate; And
A gate of a memory cell transistor arranged on the channel layer corresponding to both sidewalls of the first insulating pillar and arranged between the gate of the select transistor and the gate of the select transistor stacked vertically with respect to the surface of the substrate;
Non-volatile memory device having a vertical structure comprising a. The method of claim 9,
And the conductive line is arranged to be lower than a bottom surface of a gate arranged at a lowermost part of the gates of the memory cell transistors.

Images