KR20120128438A - Vertical structure non-volatile memory device, semiconductor device and system - Google Patents

Abstract

PURPOSE: A non-volatile memory device, a semiconductor device and a system of a vertical structure are provided to easily control current characteristics of a memory cell string by controlling a memory cell of the memory cell string and a threshold voltage of selection transistors. CONSTITUTION: A channel guiding layer(120b) is vertically extended on a substrate(100). A channel layer(120a) contacts one side of the channel guiding layer and is vertically extended. A plurality of gate electrodes(150) and a plurality of interlayer dielectric layers(160) are alternatively laminated along one side wall of the channel layer. An insulating region(170) is formed between channel guiding layers. A gate dielectric layer(140) is formed between the channel layer and the gate electrode.

Description

Vertical structure non-volatile memory device, semiconductor device and system

The technical idea of the present invention relates to a nonvolatile memory device having a vertical structure, and more particularly, to a nonvolatile memory device having a vertical structure having a buried channel in order to lower an initial threshold voltage.

Electronic products are getting smaller and bulkier and require higher data throughput. Accordingly, there is a need to increase the degree of integration of semiconductor memory devices used in such electronic products. As one of methods for improving the degree of integration of a semiconductor memory device, a nonvolatile memory device having a vertical transistor structure instead of a conventional planar transistor structure has been proposed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device having excellent durability, which is capable of maintaining a constant threshold voltage during a program / erase cycle by providing a channel layer having a buried channel.

An object of the present invention is to provide a nonvolatile memory device having a vertical structure having a low initial operating voltage and a low erase operation voltage.

Another object of the present invention is to provide a semiconductor device having lower initial threshold voltage of a transistor to improve erase speed and improved reliability.

Another object of the present invention is to provide a system including the nonvolatile memory device.

A nonvolatile memory device having a vertical structure of one embodiment of the present invention is provided. The vertical nonvolatile memory device may include a channel induction layer vertically stretched onto a substrate; A channel layer extending vertically in contact with one side of the channel inducing layer and including a first conductivity type impurity; And a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked along one side wall of the channel layer.

In some embodiments of the present invention, the first conductivity type impurity of the channel layer may be an n-type impurity.

In some embodiments of the present invention, the n-type impurity concentration of the channel layer may be 5 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ³ .

In some embodiments of the present disclosure, the channel induction layer may include a second conductivity type impurity that is opposite to the first conductivity type impurity or may not be doped with impurities.

In some embodiments of the present invention, the second conductivity type impurity of the channel inducing layer may be a p-type impurity.

In some embodiments, the gate dielectric layer may be formed between the channel layer, the plurality of gate electrodes, and the plurality of interlayer insulating layers and extend vertically on a substrate.

In some embodiments of the invention, a bit line connected to one end of the memory cell string; And a common source line connected to the other end of the memory cell string opposite the bit line.

The semiconductor element of one embodiment of the present invention is provided. The semiconductor device may include a channel induction layer; And a channel layer disposed on one side of the channel induction layer and including a first conductive impurity to form a buried channel.

In some embodiments of the present disclosure, the channel inducing layer layer may include a second conductivity type impurity that is opposite to the first conductivity type impurity or may be non-doped.

A system of one embodiment of the present invention is provided. The system includes a memory including the vertical nonvolatile memory device; A processor in communication with the memory via a bus; And an input / output device in communication with the bus.

According to a nonvolatile memory device having a vertical structure according to the inventive concept, current characteristics of a memory cell string may be controlled by controlling threshold voltages of a memory cell and a selection transistor of a memory cell string. This makes it possible to manufacture a nonvolatile memory device having improved reliability.

1 is an equivalent circuit diagram of a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present invention.
2 is an equivalent circuit diagram of a memory cell string of a nonvolatile memory device according to another exemplary embodiment of the present invention.
3 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a first exemplary embodiment of the present invention.
4A through 4H are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 3.
5 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a second embodiment of the present invention.
6 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a third embodiment of the present invention.
7 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a fourth embodiment of the present invention.
8 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a fifth embodiment of the present invention.
9A through 9F are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 8.
FIG. 10 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a sixth embodiment of the present invention.
11 is a schematic block diagram of a nonvolatile memory device according to another embodiment of the present invention.
12 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.
13 is a block diagram illustrating an electronic system according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing. Further, various elements and regions in the drawings are schematically drawn. Accordingly, the invention is not limited by the relative size or spacing drawn in the accompanying drawings.

1 is an equivalent circuit diagram of a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present invention. 1 illustrates an equivalent circuit diagram of a NAND flash memory device having a vertical channel structure.

Referring to FIG. 1, the memory cell array 10 may include a plurality of memory cell strings 11. Each of the plurality of memory cell strings 11 may have a vertical structure extending in a vertical direction (ie, a z direction) with respect to an extending direction (ie, x and y directions) of a main surface of a substrate (not shown). The memory cell block 13 may be configured by the plurality of memory cell strings 11.

Each of the plurality of memory cell strings 11 may include a plurality of memory cells MC1 to MCn, a string select transistor SST, and a ground select transistor GST. In each memory cell string 11, the ground select transistors GST, the plurality of memory cells MC1 to MCn, and the string select transistors SST may be vertically disposed (ie, in the z direction). Here, the plurality of memory cells MC1 to MCn may store data. The plurality of word lines WL1 to WLn may be coupled to each of the memory cells MC1 to MCn to control the memory cells MC1 to MCn coupled thereto. The number of the plurality of memory cells MC1-MCn may be appropriately selected according to the capacity of the semiconductor memory device.

On one side of the memory cell string 11 arranged in the first to mth columns of the memory cell block 13, for example, on the drain side of the string select transistor SST, a plurality of lines extending in the x direction, respectively, Bit lines BL1-BLm may be connected. In addition, a common source line CSL may be connected to the other side of each memory cell string 11, for example, a source side of the ground select transistor GST.

Word lines WL1 to WLn extending in the y direction are formed in the gates of the memory cells MC1 to MCn arranged on the same layer among the plurality of memory cells MC1 to MCn of the plurality of memory cell strings 11. Can be commonly connected. As the word lines WL1 to WLn are driven, data may be programmed, read, or erased in the plurality of memory cells MC1 to MCn.

In each memory cell string 11, the string select transistor SST may be arranged between the bit lines BL1-BLm and the memory cells MC1-MCn. In the memory cell block 13, each string select transistor SST is connected to a plurality of bit lines BL1-BLm and a plurality of memory cells MC1-MCn by a string select line SSL connected to a gate thereof. You can control the data transfer between them.

The ground select transistor GST may be arranged between the memory cells MC1 to MCn and the common source line CSL. In the memory cell block 13, each ground select transistor GST is connected between the plurality of memory cells MC1 to MCn and the common source line CSL by a ground select line GSL connected to its gate, respectively. Data transfer can be controlled.

2 is an equivalent circuit diagram of a memory cell string of a nonvolatile memory device according to another exemplary embodiment of the present invention. 2 illustrates an equivalent circuit diagram of one memory cell string 11A included in a vertical NAND flash memory device having a vertical channel structure.

In Fig. 2, the same reference numerals as in Fig. 1 mean the same elements. Therefore, detailed description thereof is omitted here.

FIG. 1 illustrates a case in which the string select transistor SST is composed of a single transistor. However, in the embodiment of FIG. 2, instead of the string select transistor SST of FIG. 1, the string select transistors SST1 and SST2 including a pair of transistors arranged in series between the bit line BL and the memory cells MC1 to MCn. ) Is arranged. In this case, a string select line SSL may be commonly connected to gates of the string select transistors SST1 and SST2. Here, the string select line SSL may correspond to the first string select line SSL1 or the second string select line SSL2 of FIG. 1.

In addition, FIG. 1 illustrates a case in which the ground select transistor GST is configured of a single transistor. However, in the embodiment of FIG. 2, instead of the ground select transistor GST, the ground select transistor GST1 including a pair of transistors arranged in series between the plurality of memory cells MC1 to MCn and the common source line CSL. , GST2) may be arranged. In this case, the ground select line GSL may be commonly connected to the gates of the ground select transistors GST1 and GST2. The ground select line GSL may correspond to the first ground select line GSL1 or the second ground select line GSL2 of FIG. 1.

The bit line BL may correspond to any one of the bit lines BL1 to BLm of FIG. 1.

3 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a first exemplary embodiment of the present invention.

In FIG. 3, some components of the memory cell string of FIG. 1 may be omitted. For example, the bit line of the memory cell string is omitted.

Referring to FIG. 3, the nonvolatile memory device 1000a extends vertically in contact with one side of the channel induction layer 120b and the channel induction layer 120b vertically extending onto the substrate 100. A channel layer 120a including a type impurity, and a transistor including a plurality of gate electrodes 150 and a plurality of interlayer insulating layers 160 alternately stacked along one sidewall of the channel layer 120a. .

As shown in FIG. 3, the memory cell strings 11 or 11A (see FIGS. 1 and 2) may include a channel layer 120a and may extend in the z direction from the substrate 100. Each memory cell string 11 or 11A may include two ground select transistors GST1 and GST2, a plurality of memory cells MC1, MC2, MC3, and MC4, and two string select transistors SST1 and SST2. .

The substrate 100 may include a substrate 100 having a main surface extending in the x direction and the y direction. The substrate 100 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may comprise silicon, germanium or silicon-germanium. The substrate 100 may be provided as a bulk wafer or an epitaxial layer.

The column-shaped channel guide layer 120b may be disposed on the substrate 100 to extend in the z direction. The channel guide layer 120b may be spaced apart from each other in the x and y directions. The channel induction layer 120b may be in direct contact with the substrate 100 at the bottom thereof to be electrically connected to the substrate induction layer 120b. The channel induction layer 120b may include a semiconductor material such as polysilicon, and the semiconductor material may include a second conductivity type impurity opposite to the first conductivity type impurity included in the channel layer 120a. It may not be doped. The second conductivity type impurity may be a p-type impurity, and the p-type impurity may be boron (B), aluminum (Al), gallium (Ga), zinc (Zn), or the like.

For example, the channel induction layer 120b may have an annular shape, and a buried insulation layer 130 may be formed in the channel induction layer 120b. The arrangement of adjacent channel guide layers 120b with the insulating region 170 therebetween may be symmetrical as shown, but the present invention is not limited thereto.

The columnar channel layer 120a may be disposed to be in contact with one side of the channel guide layer 120b so as to be perpendicular to the substrate 100, that is, extend in the z direction. The channel layer 120a may be spaced apart from each other in the x and y directions. The channel layer 120a may be formed, for example, in an annular shape. The channel layer 120a may include a semiconductor material such as polysilicon, and the semiconductor material may include a first conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity, and the n-type impurity may be phosphorus (P), arsenic (As), antimony (Sb), or the like. The n-type impurity of the channel layer 120a may be, for example, an impurity concentration of 5 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ³ .

The channel layer 120a is a buried channel, and a channel is not formed at an interface between the channel layer 120a and the gate dielectric layer 140, but a channel below the interface spaced a predetermined distance from the interface. Is formed.

Therefore, in contrast to the surface channel generated at the interface between the channel layer and the gate dielectric layer, the buried channel of the present invention is less affected by the interface trap density (N _it ), and has a low charge trap density. Since it can maintain a constant threshold voltage (Vth) during the program / erase cycle can have excellent endurance (cycling endurance) characteristics.

In addition, since the channel layer 120a is a buried channel, the initial threshold voltage may be lowered, so that the erase operation voltage is lowered, which causes the charge storage layer 144 (FIG. 4C) from the gate electrode 150. FIG. Back-tunneling, in which electrons travel, can be reduced. Therefore, the time required to perform an erase operation of the nonvolatile memory device having a vertical structure can be reduced, and the charge retention property of the charge storage layer 144 is improved, so that the data retention property of the nonvolatile memory device is improved. And reliability can be improved.

In addition, the conductive layer 190 may be formed to cover the top surface of the buried insulating layer 130 and to be electrically connected to the channel induction layer 120b. The conductive layer 190 may include doped polysilicon. The conductive layer 190 may serve as a drain region of the string select transistors SST1 and SST2.

The first string select transistors SST1 arranged in the x direction may be commonly connected to the bit line BL (see FIG. 1) through the conductive layer 190. The bit line (not shown) may be formed in a line-shaped pattern extending in the x direction, and may be electrically connected through a contact electrode (not shown) formed on the conductive layer 190. In addition, the first ground select transistors GST1 arranged in the x direction may be electrically connected to the impurity region 105 adjacent to each other.

A plurality of impurity regions 105 may be arranged to be spaced apart in the x direction with respect to each other while extending in the y direction adjacent to the main surface of the substrate 100. That is, the impurity regions 105 may be arranged one by one between the channel guide layers 120b in the x direction. The impurity region 105 may be a source region and form a PN junction with another region of the substrate 100. The common source line CSL of FIGS. 1 and 2 may be connected to the impurity region 105 in a region not shown. The impurity region 105 may include a high concentration impurity region (not shown) adjacent to and located at the center of the substrate 100, and a low concentration impurity region (not shown) disposed at both ends of the high concentration impurity region. have. An insulating region 170 may be formed on the impurity regions 105.

The insulating region 170 may be formed between the channel induction layers 120b. That is, the insulating region 170 may be formed between adjacent memory cell strings using different channel induction layers 120b.

A plurality of gate electrodes 151 to 158 may be spaced apart from the substrate 100 in the z direction along the side surface of the channel induction layer 120b. The gate electrodes 150 may be gates of the ground select transistors GST1 and GST2, the memory cells MC1, MC2, MC3, and MC4, and the string select transistors SST1 and SST2, respectively. The gate electrodes 150 may be commonly connected to adjacent memory cell strings arranged in the y direction. Gate electrodes 157 and 158 of the string select transistors SST1 and SST2 may be connected to the string select line SSL (see FIG. 1). Gate electrodes 153, 154, 155, and 156 of the memory cells MC1, MC2, MC3, and MC4 may be connected to word lines WL1, WL2, WLn−1 and WLn (see FIGS. 1 and 2). have. The gate electrodes 151 and 152 of the ground select transistors GST1 and GST2 may be connected to the ground select line GSL (see FIG. 1). The gate electrodes 150 may include a metal film, for example tungsten (W). In addition, although not shown, the gate electrodes 150 may further include a diffusion barrier (not shown). For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), or titanium. It may include any one selected from nitride (TiN).

The gate dielectric layer 140 may be disposed between the channel layer 120a and the gate electrodes 150. Although not specifically illustrated in FIG. 3, the gate dielectric layer 140 may include a tunneling insulation layer, a charge storage layer, and a blocking insulation layer that are sequentially stacked from the channel layer 120a.

The tunneling insulating layer may tunnel the charge to the charge storage layer in an F-N manner. The tunneling insulating layer may include, for example, silicon oxide. The charge storage layer may be a charge trap layer or a floating gate conductive layer. For example, the charge storage layer may include quantum dots or nanocrystals. Here, the quantum dot or nano crystal may be composed of fine particles of a conductor, for example, a metal or a semiconductor. The blocking insulating layer may include a high-k dielectric material. Here, the high dielectric constant means a dielectric having a higher dielectric constant than the oxide film.

A plurality of interlayer insulating layers 161 to 169 and 160 may be arranged between the gate electrodes 150. Like the gate electrodes 150, the interlayer insulating layers 160 may be arranged to be spaced apart from each other in the z direction and extend in the y direction. One side of the interlayer insulating layers 160 may be in contact with the gate dielectric layer 140. The interlayer insulating layers 160 may include silicon oxide or silicon nitride.

In FIG. 3, four memory cells MC1, MC2, MC3, and MC4 are illustrated as being arranged, but this is exemplary and more or fewer memory cells are arranged according to the capacity of the semiconductor memory device 1000a. May be In addition, the string select transistors SST1 and SST2 and the ground select transistors GST1 and GST2 of the memory cell strings are arranged in pairs, respectively. However, the present invention is not limited to this form, and each of the string select transistors SST and the ground select transistors GST of the memory cell string shown in FIG. 1 may exist. In addition, the string select transistor SST and the ground select transistor GST may have a different structure from those of the memory cells MC1, MC2, MC3, and MC4.

The non-volatile memory device having a three-dimensional vertical structure as in the present embodiment is provided with a channel layer 120a having a buried channel, thereby being less influenced by charge trapping density and thus having excellent durability characteristics, and having an initial threshold voltage ( Since an initial threshold voltage may be lowered, an erase operation voltage may be lowered to increase data retention characteristics and reliability of the nonvolatile memory device.

In the opposite embodiment, the channel layer 120a may be formed of a semiconductor material doped with p-type impurities, and the channel induction layer 120b may be formed of a semiconductor material doped with n-type impurities or not doped with impurities. .

4A to 4H are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 3, and are cross-sectional views of the perspective view of FIG. 3 viewed in the y direction according to a process sequence.

Referring to FIG. 4A, a plurality of sacrificial layers 181-188: 180 and a plurality of interlayer insulating layers 161-169: 160 are alternately stacked on the substrate 100. As illustrated, the sacrificial layers 180 and the interlayer insulating layers 160 may be alternately stacked on the substrate 100 starting with the first interlayer insulating layer 161. The sacrificial layers 180 may be formed of a material that can be etched with etch selectivity with respect to the interlayer insulating layers 160. That is, in the process of etching the sacrificial layers 180, the sacrificial layers 180 may be formed of a material that can be etched while minimizing the etching of the interlayer insulating layers 160. Such etch selectivity may be quantitatively expressed through a ratio of an etching rate of the sacrificial layer 180 to an etching rate of the interlayer insulating layer 160. For example, the interlayer insulating layer 160 may be at least one of a silicon oxide film and a silicon nitride film, and the sacrificial layer 180 may include an interlayer insulating layer 160 selected from a silicon film, a silicon oxide film, silicon carbide, and a silicon nitride film. It may be another material.

According to one embodiment, as shown, the thickness of the interlayer insulating layers 160 may not all be the same. The lowermost first interlayer insulating layer 161 of the interlayer insulating layers 160 may be formed to have a thin thickness, and the third interlayer insulating layer 163 and the seventh interlayer insulating layer 167 may be formed to be thick. However, the thicknesses of the interlayer insulating layers 160 and the sacrificial layers 180 may be variously modified from those shown, and the number of layers constituting the interlayer insulating layers 160 and the sacrificial layers 180 may be varied. It can also be variously modified.

Referring to FIG. 4B, first openings Ta passing through the interlayer insulating layers 160 and the sacrificial layers 180 that are alternately stacked may be formed. The first openings Ta may have a hole shape having a depth in a z direction. In addition, the first openings Ta may be isolated regions formed to be spaced apart in the x direction and the y direction (see FIG. 3).

The forming of the first openings Ta may include a predetermined mask pattern defining positions of the first openings Ta on the interlayer insulating layers 160 and the sacrificial layers 180 that are alternately stacked. Forming and anisotropically etching the interlayer insulating layers 160 and the sacrificial layers 180 using the same as an etching mask. Since the structure including two kinds of different films is etched, sidewalls of the plurality of first openings Ta may not be completely perpendicular to the top surface of the substrate 100. For example, the closer to the upper surface of the substrate 100, the width of the first openings Ta may be reduced.

The first opening Ta may be formed to expose the top surface of the substrate 100 as shown. In addition, as a result of over-etching in the anisotropic etching step, the substrate 100 under the first opening Ta may be recessed to a predetermined depth as shown.

Referring to FIG. 4C, a gate dielectric layer 140 and a channel layer 120a may be formed to uniformly cover inner walls and lower surfaces of the first openings Ta.

The gate dielectric layer 140 may include a blocking insulating layer 146, a charge storage layer 144, and a tunneling insulating layer 142. Therefore, the first openings Ta may be stacked in the above-described order. The blocking insulating layer 146, the charge storage layer 144, and the tunneling insulating layer 142 may include atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (Physical Vapor). Deposition, PVD) may be used.

Next, channel layer 120a may be formed using ALD or CVD. The channel layer 120a may include a semiconductor material such as polysilicon, and the semiconductor material may include a first conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity, and the n-type impurity may be phosphorus (P), arsenic (As), antimony (Sb), or the like. The n-type impurity of the channel layer 120a may be, for example, an impurity concentration of 5 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ³ .

Referring to FIG. 4D, an insulating layer (not shown) is formed on the channel layer 120a. The insulating layer may be an oxide film.

Next, a dry etching process is performed to etch the insulating layer (not shown) and the channel layer 120a formed on the lower surfaces of the first openings Ta, thereby exposing the gate dielectric layer 140.

Next, a wet etching process is performed to remove the tunneling insulating layer 142 formed on the lower surfaces of the first openings Ta.

Next, the wet etching process is performed to remove the charge storage layer 144 formed on the lower surfaces of the first openings Ta.

Next, a wet etching process is performed to remove the blocking insulating layer 146 formed on the lower surfaces of the first openings Ta.

By performing the dry etching process and the wet etching process, the gate dielectric layer 140 and the channel layer 120a of the bottom surfaces of the first openings Ta may be etched to expose the substrate 100, and the channel induction layer 120b. In this process, the distance between the source region and the channel layer 120a may be reduced to prevent channel disconnection under the select transistor.

Next, a channel guide layer 120b may be formed to uniformly cover the inner wall and the bottom of the first openings Ta. The channel induction layer 120b may be formed to a predetermined thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). At the bottoms of the first openings Ta, the channel induction layer 120b may be in direct contact with the substrate 100 to be electrically connected.

The channel induction layer 120b may include a semiconductor material such as polysilicon, and the semiconductor material may include a second conductivity type impurity opposite to the first conductivity type impurity included in the channel layer 120a. Or undoped. The second conductivity type impurity may be a p-type impurity, and the p-type impurity may be boron (B), aluminum (Al), gallium (Ga), zinc (Zn), or the like.

Referring to FIG. 4E, the first openings Ta may be filled with the buried insulating layer 130.

Optionally, before forming the buried insulating layer 130, a hydrogen annealing step may be further performed to heat-treat the structure in which the channel induction layer 120b is formed in a gas atmosphere containing hydrogen or deuterium. By the hydrogen annealing step, many of the crystal defects present in the channel induction layer 120b may be healed.

Next, a planarization process, such as chemical mechanical polishing, until the ninth interlayer insulating layer 169 is exposed to remove unnecessary semiconductor material and insulating material covering the uppermost ninth interlayer insulating layer 169. Polishing, CMP) or etch-back process may be performed.

A portion of the upper portion of the buried insulating layer 130 may be removed using an etching process to deposit a conductive material for forming the conductive layer 190 at the removed position. Again, by performing the planarization process, the conductive layer 190 may be formed on the buried insulating layer 130 and connected to the channel induction layer 120b. Thereafter, an etch stop layer 191 may be formed on the ninth insulating layer 169.

Referring to FIG. 4F, a second opening Tb exposing the substrate 100 may be formed. The second opening Tb may extend in the y direction (see FIG. 3). The forming of the second opening Tb may include forming an etching mask in which the second opening Tb is defined, and the interlayer insulating layers under the etching mask until the upper surface of the substrate 100 is exposed. Anisotropically etching the 160 and the sacrificial layers 180.

According to an embodiment, as shown in the drawing, the second openings Tb may be formed one by one between the channel guide layers 120b. However, the technical spirit of the present invention is not limited to this embodiment, and the relative arrangement of the channel guide layer 120b and the second opening Tb may vary.

Next, the sacrificial layers 180 (see FIG. 4E) exposed through the second openings Tb are selectively removed. By removing the plurality of sacrificial layers 180, a plurality of tunnels Lt communicating with the second opening Tb and horizontal to the substrate 100 are formed between each of the plurality of interlayer insulating layers 160. Some sidewalls of the gate dielectric layer 140 may be exposed through the tunnels Lt.

Forming the tunnels Lt may include horizontally etching the sacrificial layers 180 using an etch recipe having etch selectivity with respect to the interlayer insulating layers 160. For example, when the sacrificial layers 180 are silicon nitride and the interlayer insulating layers 160 are silicon oxide, the horizontal etching may be performed using an etchant including phosphoric acid. The etching may be an isotropic etching process including wet etching or chemical dry etch (CDE).

Referring to FIG. 4G, the second opening Tb and the tunnel Lt of FIG. 4F may be filled with a conductive material. Thereafter, the conductive material may be etched to form the third opening Tc substantially the same in width and position as the second opening Tb to expose the substrate 100. Through this, a plurality of gate electrodes 151-158: 150 surrounding the channel induction layer 120b may be formed.

By implanting impurities into the substrate 100 through the third opening Tc, an impurity region 105 adjacent to an upper surface of the substrate 100 and extending in the y direction (see FIG. 3) may be formed. The impurity may be a high concentration impurity region 105 formed by ion implantation of N + -type impurities. The process of forming the impurity region 105 is not necessarily performed in this process step, but may be performed in other process steps before or after it as necessary.

In addition, when viewed in the x direction, the present invention provides a channel layer 120a formed of a semiconductor material doped with n-type impurities on the channel induction layer 120b formed of a semiconductor material doped with or without p-type impurities. ) Is formed. In addition, the gate dielectric layer 140 and the gate electrode 150 are sequentially stacked on the channel layer 120a. In forming the channel induction layer 120b and the channel layer 120a, a buried channel may be formed in a nonvolatile memory device having a vertical structure by using a semiconductor material including different conductive impurities. .

Therefore, in contrast to the surface channel, the present invention forms a buried channel below the interface spaced apart from the interface between the channel layer 120a and the gate dielectric layer 140 by a predetermined distance d, thereby obtaining charge trapping density. It is less affected by the can have excellent durability characteristics. In addition, since an initial threshold voltage may be lowered, an erase operation voltage may be lowered to increase data retention characteristics and reliability of the nonvolatile memory device.

In the opposite embodiment, the channel layer 120a may be formed of a semiconductor material doped with p-type impurities, and the channel induction layer 120b may be formed of a semiconductor material doped with n-type impurities or not doped with impurities. have.

Referring to FIG. 4H, an insulating region 170 may be formed to fill the third opening Tc. The insulating region 170 may be made of the same material as the interlayer insulating layer 160. The insulating region 170 may be formed by a deposition and planarization process of an insulating material.

Next, a bit line contact plug 195 may be formed on the conductive layer 190 to penetrate the etch stop layer 191. The bit line contact plug 195 may be formed using a photolithography process and an etching process. A bit line 193 connecting the bit line contact plugs 195 arranged in the x direction may be formed on the etch stop layer 191 and the insulating region 170. The bit line 193 may also be formed in a line shape using a photolithography process and an etching process.

5 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a second embodiment of the present invention.

The same reference numerals as in FIG. 3 denote the same members, and thus detailed description thereof will be omitted here. Referring to FIG. 5, in the nonvolatile memory device 1000b of the present exemplary embodiment, the common source line 110 extends in the z direction on the impurity region 105 and has an ohmic contact with the impurity region 105. Can be arranged to The common source line 110 may provide a source region to ground select transistors GST1 and GST2 of memory cell strings adjacent to two channel layers 120a adjacent to each other in the x direction. The common source line 110 may extend in the y direction along the impurity region 105. The common source line 110 may include a conductive material. For example, the common source line 110 may include at least one metal material selected from tungsten (W), aluminum (Al), or copper (Cu). Although not shown in FIG. 5, a silicide layer may be interposed between the impurity region 105 and the common source line 110 to lower the contact resistance. The silicide layer (not shown) may include a metal silicide layer, such as a cobalt silicide layer.

When the impurity region 105 has a conductivity type opposite to that of the substrate 100, the impurity region 105 may be a source region of the ground select transistors GST1 and GST2. Alternatively, when the impurity region 105 has the same conductivity type as the substrate 100, the common source line 110 may operate as a pocket P well contact for an erase operation in units of memory cell blocks. It may be. In this case, by applying a high voltage to the substrate 100 through the pocket P well contact electrode, data stored in all memory cells in the corresponding memory cell block of the substrate 100 may be erased.

In the manufacturing method described above with reference to FIG. 4H, the common source line 110 forms a spacer insulating region 170 ′ on a sidewall of the third opening Tc after forming the insulating region 170, and forms a common source line. It can be formed by depositing a conductive material constituting (110). The spacer insulating region 170 ′ may be formed by filling an insulating material in the third opening Tc and then performing anisotropic etching. The substrate 100 may be recessed by overetching the substrate 100 by the anisotropic etching. Next, the common source line 110 may be formed by adding an etching process such as a deposition process and an etch back process of the conductive material.

6 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a third embodiment of the present invention.

The same reference numerals as in FIGS. 3 and 5 denote the same members, and thus detailed description thereof will be omitted here. Referring to FIG. 6, the nonvolatile memory device 1000c may anisotropically etch the channel layer 120a and etch the gate dielectric layer 140 using the spacer layer channela 120a having the bottom surface etched thereon. Thereafter, the channel induction layer 120b formed thereon may be formed.

Referring to FIG. 3, the substrate 100 is exposed by etching the gate dielectric layer 140 and the channel layer 120a at the bottom of the first openings Ta through anisotropic etching. The etching process may include anisotropically etching the channel layer 120a and etching the gate dielectric layer 140 using the spacer layer channela having a bottom surface etched therein.

Next, a channel guide layer 120b may be formed to uniformly cover inner walls and bottom surfaces of the first openings Ta. The channel induction layer 120b may be formed to contact the substrate 100, and may be electrically connected to the substrate 100.

7 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a fourth embodiment of the present invention. The same reference numerals as those in Fig. 3 denote the same members, and thus detailed description thereof will be omitted here. Referring to FIG. 7, in the nonvolatile memory device, a single crystal silicon 125 may be formed on a substrate 100, and a channel layer 120a and a channel induction layer 120b may be formed on the single crystal silicon 125. have.

Referring to the embodiment of FIG. 3, the first openings Ta and the second openings (see FIG. 4B) are formed, and a selective epitaxial growth (SEG) method is performed on the lower surface of the first openings, that is, on the substrate. The single crystal silicon 125 is grown. Next, a gate dielectric layer 140 and a channel layer 120a are formed on the single crystal silicon 125, and dry and wet etching processes are performed (see FIG. 4D) to induce a channel on the single crystal silicon 125. Form layer 120b. Unlike in FIG. 3, in the above embodiment, the single crystal silicon 125 is formed on the etched substrate 100 through selective epitaxial growth, thereby reducing contact resistance with the substrate 100, thereby providing current. Can improve the characteristics

8 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a fifth embodiment of the present invention.

In FIG. 8, some components of the memory cell string of FIG. 1 may be omitted. For example, the bit line of the memory cell string is omitted.

Referring to FIG. 8, the nonvolatile memory device 2000a extends vertically in contact with one side of the channel induction layer 225 and the channel induction layer 225 disposed on the substrate 200, and has a first conductivity. A transistor includes a channel layer 220 including a type impurity, a plurality of gate electrodes 250 and a plurality of interlayer insulating layers 260 alternately stacked along one side wall of the channel layer 220.

The substrate 200 may include a substrate 200 having a main surface extending in the x direction and the y direction. The substrate 200 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may comprise silicon, germanium or silicon-germanium. The substrate 200 may be provided as a bulk wafer or an epitaxial layer.

The column-shaped channel guide layer 225 may be disposed on the substrate 200 to extend in the z direction. The channel guide layer 225 may be spaced apart from each other in the x and y directions. The channel guide layer 225 may be formed, for example, in an annular shape. The channel induction layer 225 may include a semiconductor material such as polysilicon, and the semiconductor material may be undoped or have a conductivity type opposite to that of the first conductivity type impurities included in the channel layer 220. Conductive impurities may be included. The second conductivity type impurity may be a p-type impurity, and the p-type impurity may be boron (B), aluminum (Al), gallium (Ga), zinc (Zn), or the like.

The channel induction layer 225 may have an annular shape, for example, and a buried insulation layer 230 may be formed in the channel induction layer 225. The arrangement of adjacent channel guide layers 225 with the insulating region 270 therebetween may be symmetrical as shown, but the present invention is not limited thereto.

The columnar channel layer 220 may be disposed to be perpendicular to the substrate 200 in contact with one side of the channel guide layer 225, that is, extend in the z direction. The channel layer 220 may be spaced apart from each other in the x direction and the y direction.

The channel layer 220 may be formed, for example, in an annular shape. The channel layer 220 may include a semiconductor material such as polysilicon, and the semiconductor material may include a first conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity, and the n-type impurity may be phosphorus (P), arsenic (As), antimony (Sb), or the like. The n-type impurity of the channel layer 220 may be, for example, an impurity concentration of 5 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ³ .

The channel layer 220 is a buried channel, and a channel is not formed at an interface between the channel layer 220 and the gate dielectric layer 240, but is buried under the interface. Is formed.

In addition, the conductive layer 290 may be formed to cover the top surface of the buried insulating layer 230 and to be electrically connected to the channel induction layer 225. The conductive layer 290 may include doped polysilicon. The conductive layer 290 may serve as a drain region of the string select transistor SST.

Select transistors SST arranged in the x direction may be commonly connected to the bit line BL (see FIG. 1) through the conductive layer 290. The bit line (not shown) may be formed in a line-shaped pattern extending in the x direction, and may be electrically connected through a contact electrode (not shown) formed on the conductive layer 290. In addition, the ground select transistors GST arranged in the x direction may be electrically connected to the impurity region 205 adjacent to each other.

The impurity regions 205 may be arranged to be spaced apart in the x direction while extending in the y direction adjacent to the main surface of the substrate 200. The impurity regions 205 may be arranged one by one between the channel induction layers 225 in the x direction. The impurity region 205 may be a source region and form a PN junction with another region of the substrate 200. The common source line CSL of FIGS. 1 and 2 may be connected to the impurity region 205 on a region not shown. An insulating region 270 may be formed on the impurity regions 205.

The insulating region 270 may be formed between the channel induction layers 225. That is, the insulating region 270 may be formed between adjacent memory cell strings using different channel induction layers 225.

A plurality of gate electrodes 251 to 256 may be spaced apart from the substrate 200 in the z direction along both sides of the channel guide layer 225 in the x direction. The gate electrodes 250 may be gates of a ground select transistor GST, a plurality of memory cells MC1, MC2, MCn-1, and MCn, and a string select transistor SST, respectively. The gate electrodes 250 may be commonly connected to adjacent memory cell strings arranged in the y direction.

The gate dielectric layer 240 may be disposed between the channel layer 220 and the gate electrodes 250. The gate dielectric layer 240 may be disposed to cover the top and bottom surfaces of the gate electrodes 250.

In addition, the gate dielectric layer 240 may be disposed to cover one side surface of the interlayer insulating layers 260 that are not in contact with the channel layer 220. Although not illustrated in FIG. 8, the gate dielectric layer 240 may include a tunneling insulation layer, a charge storage layer, and a blocking insulation layer that are sequentially stacked from the channel layer 220.

A plurality of interlayer insulating layers 261-267: 260 may be arranged between the gate electrodes 250. Like the gate electrodes 250, the interlayer insulating layers 260 may be arranged to be spaced apart from each other in the z direction and extend in the y direction. One side of the interlayer insulating layers 260 may be in contact with the gate dielectric layer 240. The interlayer insulating layers 260 may include silicon oxide or silicon nitride.

In the non-volatile memory device 2000a having a three-dimensional vertical structure as in the present embodiment, a surface channel is not formed at an interface between the channel layer 220 and the gate dielectric layer 240. By forming a buried channel in which a channel is formed below a large distanced interface, the charge trap density is less affected. In addition, the low charge trapping density can maintain a constant threshold voltage (Vth) during the program / erase cycle can have excellent durability characteristics.

Also, since the buried channel can lower the initial threshold voltage, the erase operation voltage is lowered, which causes electrons to move from the gate electrode 250 to the charge storage layer 244 (see FIG. 9F). It can reduce the occurrence of back-tunneling. Therefore, the time required to perform the erase operation can be reduced, and the charge retention characteristics of the charge storage layer 244 can be improved, thereby improving data retention characteristics and reliability of the nonvolatile memory device.

9A to 9F are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of FIG. 8, and are cross-sectional views of the perspective view of FIG. 8 viewed in the y direction according to a process sequence.

Referring to FIG. 9A, a plurality of sacrificial layers 281-286 and 280 and a plurality of interlayer insulating layers 261-267 and 260 may be alternately formed on the substrate 200. The interlayer insulating layers 260 and the sacrificial layers 280 may be made of materials having etch selectivity with each other.

Referring to FIG. 9B, first openings Ta may be formed through the interlayer insulating layers 260 and the sacrificial layers 280 to expose the substrate 200. The first openings Ta correspond to regions in which a channel layer 220 (see FIG. 9C) and a channel induction layer 225 (see FIG. 9C) will be formed in a subsequent process. As shown in FIG. 8, It may be arranged in a matrix form spaced apart from each other in the x direction and the y direction.

Referring to FIG. 9C, a channel layer 220 uniformly covering inner walls and lower surfaces of the first openings Ta of FIG. 9B may be formed. The channel layer 220 may be formed to have a predetermined thickness, for example, a thickness in the range of 1/50 to 1/5 of the width of the first opening Ta using ALD or CVD.

Next, channel layer 220 may be formed using ALD or CVD. The channel layer 220 may include a semiconductor material such as polysilicon, and the semiconductor material may include a first conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity, and the n-type impurity may be phosphorus (P), arsenic (As), antimony (Sb), or the like. The n-type impurity of the channel layer 220 may be, for example, an impurity concentration of 5 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ³ .

Next, a channel induction layer 225 covering the channel layer 220 may be formed uniformly. The channel induction layer 225 may be formed to a predetermined thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

The channel induction layer 225 may include a semiconductor material such as polysilicon, and the semiconductor material may include a second conductivity type impurity having a conductivity opposite to that of the first conductivity type impurity included in the channel layer 220. Or may be undoped. The second conductivity type impurity may be a p-type impurity, and the p-type impurity may be boron (B), aluminum (Al), gallium (Ga), zinc (Zn), or the like.

In the opposite embodiment, the channel layer 220 may be formed of a semiconductor material doped with p-type impurities, and the channel induction layer 225 may be formed of a semiconductor material doped with n-type impurities or not doped with impurities. have.

Next, the first opening Ta may be filled with the buried insulating layer 230. Optionally, before forming the buried insulating layer 230, a hydrogen annealing step of heat-treating the structure in which the channel induction layer 225 is formed in a gas atmosphere containing hydrogen or deuterium may be further performed. By the hydrogen annealing step, many of the crystal defects present in the channel induction layer 225 may be healed.

Next, a planarization process may be performed to remove unnecessary semiconductor material and insulating material covering the uppermost interlayer insulating layer 267. Thereafter, an upper portion of the buried insulating layer 230 may be partially removed by using an etching process, and a material forming the conductive layer 290 may be deposited at the removed position. Again, the planarization process may be performed to form the conductive layer 290.

Referring to FIG. 9D, a second opening Tb exposing the substrate 200 may be formed. The second opening Tb may extend in the y direction (see FIG. 8).

The second opening Tb may be formed by anisotropic etching of the interlayer insulating layers 260 and the sacrificial layers 280 (see FIG. 9C) using a photolithography process. The second opening Tb corresponds to a region where the insulating region 270 is to be formed by a subsequent process and extends in the y direction. The sacrificial layers 280 exposed through the second opening Tb may be removed by an etching process, thereby forming a plurality of tunnels Lt defined above and below the interlayer insulating layers 260. Can be. Some sidewalls of the channel layer 220 may be exposed through the tunnels Lt.

Referring to FIG. 9E, the channel dielectric layer 240, the interlayer insulating layers 260, and the substrate 200 are exposed through the second openings Tb and the tunnels Lt of FIG. 9D. It can be formed to cover uniformly.

The gate dielectric layer 240 may include a tunneling insulating layer 242, a charge storage layer 244, and a blocking insulating layer 246 sequentially stacked from the channel layer 220. Next, the second openings Tb and the tunnels Lt may be filled with the conductive material 250a.

Referring to FIG. 9F, the conductive material 250a of FIG. 9E may be partially etched to form a third opening Tc. As a result, the conductive material may be embedded only in the tunnel Lt of FIG. 9E to form the gate electrode 250. The process may be performed by anisotropic etching, and the gate dielectric layer 240 formed on the upper surface of the substrate 200 may also be removed by anisotropic etching. In some embodiments, gate dielectric layers 240 formed on side surfaces of the interlayer insulating layers 260 may be removed. Thereafter, an impurity region 205 may be formed by implanting impurities into the substrate 200 through the third opening Tc.

Next, the same process as described above with reference to FIG. 4H may be performed to finally manufacture the nonvolatile memory device 2000a of FIG. 8.

FIG. 10 is a schematic perspective view illustrating a three-dimensional structure of memory cell strings of a nonvolatile memory device according to a sixth embodiment of the present invention.

The same reference numerals as in FIG. 8 denote the same members, and thus detailed description thereof will be omitted here. Referring to FIG. 10, the nonvolatile memory device 2000b may be arranged such that the common source line 210 extends in the z direction on the impurity region 205 and ohmic contact with the impurity region 205. The common source line 210 may provide a source region to ground select transistors GST of memory cell strings adjacent to two channel regions 220 adjacent to each other in the x direction. The common source line 210 may include at least one metal material selected from a conductive material, for example, tungsten (W), aluminum (Al), or copper (Cu). Although not shown in FIG. 9, a silicide layer may be interposed between the impurity region 205 and the common source line 210 to lower contact resistance. The silicide layer (not shown) may include a metal silicide layer, such as a cobalt silicide layer.

When the impurity region 205 has a conductivity type opposite to that of the substrate 200, the impurity region 205 may be a source region of the ground select transistors GST1 and GST2. Alternatively, when the impurity region 205 has the same conductivity type as the substrate 200, the common source line 210 may operate as a pocket P well contact for an erase operation in units of memory cell blocks. It may be. In this case, a high voltage is applied to the substrate 200 through the pocket P well contact electrode, so that data stored in all memory cells in the corresponding memory cell block of the substrate 200 may be erased.

In the manufacturing method described above with reference to FIG. 9F, the common source line 210 forms a spacer insulating region 270 ′ on a sidewall of the third opening Tc after forming the insulating region 270, and forms a common source line. It can be formed by depositing a conductive material constituting (210). The spacer insulating region 270 ′ may be formed by filling an insulating material in the third opening Tc and then performing anisotropic etching. The substrate 200 may be recessed by overetching the substrate 200 by the anisotropic etching. Next, the common source line 210 may be formed by adding an etching process such as a deposition process and an etch back process of the conductive material.

11 is a schematic block diagram of a nonvolatile memory device according to another embodiment of the present invention.

Referring to FIG. 11, in the nonvolatile memory device 700, the NAND cell array 750 may be combined with the core circuit unit 770. For example, the NAND cell array 750 may include any one of the nonvolatile memory devices described with reference to FIGS. 3, 5, 8, and 10. The core circuit unit 770 may include a control logic 771, a row decoder 772, a column decoder 773, a sense amplifier 774, and a page buffer 775.

The control logic 771 may communicate with the row decoder 772, the column decoder 773, and the page buffer 775. The row decoder 772 may communicate with the NAND cell array 750 through a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. The column decoder 773 may communicate with the NAND cell array 750 through the plurality of bit lines BL. The sense amplifier 774 may be connected to the column decoder 773 when a signal is output from the NAND cell array 750, and may not be connected to the column decoder 773 when a signal is transmitted to the NAND cell array 750. .

For example, control logic 771 passes a row address signal to row decoder 772, which decodes this signal to string select line SSL, word line WL, and ground select line. The row address signal may be transferred to the NAND cell array 750 through the GSL. The control logic 771 transfers the column address signal to the column decoder 773 or the page buffer 775, and the column decoder 773 decodes the signal to pass the NAND cell array 750 through the plurality of bit lines BL. The column address signal can be transmitted to The signal of the NAND cell array 750 can be delivered to the sense amplifier 774 through the column decoder 773, amplified here and passed to the control logic 771 via the page buffer 775.

12 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.

Referring to FIG. 12, the memory card 800 may include a controller 810 and a memory 820 embedded in the housing 830. The controller 810 and the memory 820 may exchange electrical signals. For example, the memory 820 and the controller 810 may exchange data according to a command of the controller 810. Accordingly, the memory card 800 may store data in the memory 820 or output data from the memory 820 to the outside.

For example, the memory 820 may include any one of the nonvolatile memory devices described with reference to FIGS. 3, 5, 8, and 10. The memory card 800 may be used as a data storage medium of various portable devices. For example, the memory card 800 may include a multimedia card (MMC) or a secure digital card (SD).

13 is a block diagram illustrating an electronic system according to an embodiment of the present invention.

Referring to FIG. 13, the electronic system 900 may include a processor 910, an input / output device 930, and a memory chip 920, which may communicate data with each other using a bus 940. have. The processor 910 may execute a program and control the electronic system 900. The input / output device 930 may be used to input or output data of the electronic system 900. The electronic system 900 may be connected to an external device, for example, a personal computer or a network, using the input / output device 930 to exchange data with the external device. The memory chip 920 may store code and data for operating the processor 910. For example, the memory chip 920 may include any one of the nonvolatile memory devices described with reference to FIGS. 3, 5, 8, and 10.

The electronic system 900 may configure various electronic control devices that require the memory chip 920, and include, for example, a mobile phone, an MP3 player, navigation, and a solid state disk. : SSD), household appliances (household appliances) and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

100, 200: substrate 105, 205: impurity region
110, 210: common source line 120a, 220: channel layer
120b, 225: channel induction layer 130, 230: buried insulation layer
140 and 240: gate dielectric layers 142 and 242: tunneling insulating layer
144, 244: charge storage layer 146, 246: blocking insulating layer
150, 250: gate electrode 160, 260: interlayer insulating layer
170, 270: insulation region 170 ', 270': spacer insulation region
180, 280: sacrificial layer 190, 290: conductive layer

Claims (10)

A channel guide layer extending vertically onto the substrate;
A channel layer extending vertically in contact with one side of the channel inducing layer and including a first conductivity type impurity; And
A plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked along one side wall of the channel layer;
Non-volatile memory device having a vertical structure comprising a transistor comprising a. The method according to claim 1,
And the first conductivity type impurity of the channel layer is an n-type impurity. The method of claim 2,
The n-type impurity concentration of the channel layer is 5 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ^{3 The} vertical structure of the nonvolatile memory device. The method according to claim 1,
And the channel inducing layer includes a second conductivity type impurity opposite to the first conductivity type impurity or is not doped with impurities. 5. The method of claim 4,
And the second conductivity type impurity of the channel inducing layer is a p-type impurity. The method according to claim 1,
A gate dielectric layer formed between the channel layer, the plurality of gate electrodes and the plurality of interlayer insulating layers, and extending vertically on a substrate;
Non-volatile memory device of the vertical structure characterized in that it further comprises. The method according to claim 1,
A bit line connected to one end of the memory cell string; And
A common source line connected to the other end of the memory cell string opposite the bit line;
Non-volatile memory device of the vertical structure characterized in that it further comprises. Channel induction layer; And
A channel layer disposed on one side of the channel induction layer and including a first conductive impurity to form a buried channel;
A semiconductor device comprising a transistor comprising a. The method of claim 8,
And the channel inducing layer layer includes a second conductivity type impurity opposite to the first conductivity type impurity or is not doped with an impurity. A memory comprising a non-volatile memory device of claim 1;
A processor in communication with the memory via a bus; And
And an input / output device in communication with the bus.

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