KR20130033985A - Method for heat-treating silicon wafer - Google Patents

Abstract

PURPOSE: A heat treating method of a silicon wafer is provided to improve the surface uniformity of a BMD size and to reduce the COP of the superficial part of a wafer. CONSTITUTION: A sliced silicon wafer of a silicon ingot is heated to a first highest temperature in the range of 1325-1400>= and is quenched with the cooling speed of 50>=/sec-250>=/sec. The silicon wafer is heated to a second highest temperature in the range of 900-1250>= and is quenched. The heating rate of the second highest temperature is 1>=/min-5>=/min. [Reference numerals] (AA) Wafer surface; (BB,HH,JJ) Surface part; (CC,II,KK) Bulk part; (DD,FF) BMD nuclei; (EE) Inner wall oxide film; (GG) Void;

Description

Heat treatment method of silicon wafer {METHOD FOR HEAT-TREATING SILICON WAFER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat treatment method for a silicon wafer which heat-treats a silicon wafer (hereinafter, simply referred to as a wafer) sliced from a silicon single crystal ingot grown by the Czochralski method (hereinafter also referred to as CZ method).

In recent years, with high integration of semiconductor devices, quality requirements for silicon wafers used as substrates have become more stringent, and COP in surface layer portions (e.g., depth areas up to 7 µm from the surface) serving as semiconductor device formation regions have become strict. In addition to the reduction of defect densities such as the like, there is also a demand for improvement in wafer strength for stress-intensive heat treatment.

As a method of reducing COP, Japanese Patent Application Laid-Open No. 6-295912 discloses that a silicon wafer is subjected to a heat treatment temperature of 1100 ° C to 1300 ° C and a heat treatment time in a hydrogen gas atmosphere or a mixed gas atmosphere of hydrogen gas and inert gas. The technique which forms a DZ (denuded zone) layer in the surface layer part of a silicon wafer by heat-processing on the conditions for 1 minute-48 hours is disclosed.

In addition, an oxygen precipitate (Balk Micro Defect, hereinafter referred to as BMD) that precipitates in the bulk portion of the wafer during the heat treatment becomes a gettering site for impurities diffused into the surface layer portion in a subsequent semiconductor device formation process, and thus wafer strength. It is said to raise.

Moreover, it is preferable that the BMD density in the said bulk part is in-plane uniform in the radial direction of a wafer. If there is a variation in the BMD density in the wafer plane, the wafer strength changes in the portion where the variation occurs, so that the slip dislocation is liable to occur in the subsequent semiconductor device formation heat treatment or the like. there is a problem.

In addition, the in-plane distribution of the BMD density in the radial direction of the wafer reflects the in-plane distribution of Grown-in defects introduced at the time of single crystal growth by the CZ method. Therefore, in order to increase the in-plane uniformity of the BMD density, it is necessary to uniformly control the in-plane distribution of Grown-in defects introduced at the time of single crystal growth.

However, such a control needs to finely control crystal heat history, growth rate, etc., such as a hot zone, and there exists a problem that it becomes very expensive.

In the single crystal growth, when an OSF region in which many oxidation-induced stacking faults (hereinafter referred to as OSFs) exist is formed, an OSF ring is generated in the radial direction of the sliced wafer. In this case, it is known that in the vicinity of the OSF ring of the wafer, there are very few BMD nuclei introduced at the time of single crystal growth, that is, there is a BMD low density region in which the BMD density greatly decreases after heat treatment.

In addition, Japanese Patent Application Laid-Open No. Hei 8-330316 discloses that the OSF ring is not generated in the wafer plane. The technique of nurturing the defect-free area | region which has a lack of an atom and a spare by balance is disclosed.

However, since the method described in JP-A-8-330316 reduces the crystal growth rate, the productivity decreases, the cost is high, and since the BMD hardly precipitates in the bulk portion, the strength of the wafer decreases. There is a problem to say.

Therefore, Japanese Patent Laid-Open No. 2006-93645 discloses a nitrogen concentration of 2.9 × 10 ¹⁴ to 5.0 × 10 as a means for increasing the in-plane uniformity of the BMD density of a wafer even when an OSF region is formed during single crystal growth. A wafer containing an OSF ring grown in a range of ¹⁵ atoms / cm 3 and oxygen concentration of 1.27 × 10 ¹⁸ to 3.0 × 10 ¹⁸ atoms / cm 3 is maintained at a temperature of 600 ° C. to 800 ° C. under a reducing gas or an inert gas atmosphere. Disclosed is a method in which a temperature rising rate of 0.5 ° C./min to 2.0 ° C./min is maintained until the heat treatment temperature is reached when charged into the heat treatment furnace and subjected to heat treatment at 1000 ° C. to 1200 ° C.

However, since the method described in Japanese Patent Laid-Open No. 2006-93645 can increase the BMD density of the BMD low density region, the in-plane nonuniformity of the BMD density due to the presence of the OSF ring is somewhat improved, but still, single crystal growth is achieved. The influence of poetry was left.

In addition, the crystal growth rate is increased while precisely controlling the crystal thermal history and growth rate of the hot zone, and the OSF ring is excluded outside, and even if the entire in-plane of the wafer is a V-rich region in which a large amount of COP is blown, the single crystal is used. Convection control (rotation speed of quartz crucible, furnace pressure, heater temperature, etc.) of the melt at the time of growth has a limit, and only this has a limit in controlling in-plane uniformly the BMD density in the radial direction of a wafer.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a heat treatment method for a silicon wafer capable of increasing in-plane uniformity of BMD density in the radial direction of the bulk portion of the wafer grown by the CZ method. do. Moreover, it aims at providing the heat processing method of the silicon wafer which can also raise in-plane uniformity of BMD size, and can further reduce COP of the surface layer part of a wafer.

In the heat treatment method of a silicon wafer according to the present invention, a silicon wafer sliced from a silicon single crystal ingot grown by a CZ method is heated to a first highest achieved temperature in a range of 1325 ° C or more and 1400 ° C or less in an oxidizing gas atmosphere. After maintaining a 1st highest achieved temperature, the process of performing the 1st heat processing which temperature-falls at the temperature-fall rate of 50 degrees C / sec or more and 250 degrees C / sec or less, and the silicon wafer which performed the said 1st heat treatment in a non-oxidizing gas atmosphere, And heating to the second highest achieved temperature in the range of 900 ° C or more and 1250 ° C or less to maintain the second highest achieved temperature, and then performing a second heat treatment to lower the temperature.

It is preferable that the temperature-fall rate in a said 1st heat processing is 120 degreeC / sec or more and 250 degrees C / sec or less.

It is preferable that the temperature increase rate to the said 2nd highest achieved temperature in a said 2nd heat processing is 1 degree-C / min or more and 5 degrees C / min or less.

According to the present invention, there is provided a heat treatment method for a silicon wafer capable of increasing the in-plane uniformity of the BMD density in the radial direction of the bulk portion of the wafer grown by the CZ method. In addition, there is provided a heat treatment method of a silicon wafer which can also increase in-plane uniformity of the BMD size and can further reduce the COP of the surface layer portion of the wafer.

1 is a conceptual flowchart (first heat treatment) in a wafer cross section for explaining the effect of the present invention.
2 is a conceptual flowchart (second heat treatment) in the cross section of the wafer for explaining the effect of the present invention.
3 is a conceptual flowchart in the cross section of the wafer for explaining the effect of the present invention in the first heat treatment when the OSF ring is present in the radial direction of the wafer.
4 is a conceptual flowchart (first heat treatment) in the cross section of the wafer for explaining the effect of the present invention when the oxygen concentration of the wafer to be heat treated is high.
5 is a conceptual flowchart (second heat treatment) in the cross section of the wafer for explaining the effect of the present invention when the oxygen concentration of the wafer to be heat treated is high.
6 is a cross-sectional conceptual view showing an example of the RTP apparatus used in the heat treatment method of the silicon wafer according to the present invention.
7 is a conceptual diagram illustrating an example of a temperature sequence of a first heat treatment by RTP.
8 is a conceptual diagram illustrating an example of a temperature sequence of a second heat treatment using the vertical heat treatment apparatus.
9 is a process flowchart showing the first embodiment of the method of manufacturing a silicon wafer with the heat treatment method of the silicon wafer according to the present invention.
10 is a process flowchart showing a second embodiment of the method of manufacturing a silicon wafer including the heat treatment method of the silicon wafer according to the present invention.
11 is a process flowchart showing a third embodiment of the method of manufacturing a silicon wafer including the heat treatment method of the silicon wafer according to the present invention.
12 is a process flowchart showing the fourth embodiment of the method of manufacturing a silicon wafer including the heat treatment method of the silicon wafer according to the present invention.
It is a process flowchart which shows the 5th aspect of the manufacturing method of the silicon wafer provided with the heat processing method of the silicon wafer which concerns on this invention.
FIG. 14 is an in-plane distribution of the BMD density in the wafer radial direction from the center of the wafer to the outer periphery in Example 1 to 3. FIG.
FIG. 15 is an in-plane distribution of the BMD density in the wafer radial direction from the center of the wafer to the outer periphery in Example 4 to 6. FIG.
FIG. 16 is an in-plane distribution of the BMD density in the wafer radial direction from the center to the outer circumference of the wafer in Example 7 to 9. FIG.
17 is an in-plane distribution of BMD density in the wafer radial direction from the center to the outer circumference of the wafer in Comparative Example 1 to 3 and Conventional Example 1. FIG.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail with reference to drawings.

In the heat treatment method of a silicon wafer according to the present invention, a silicon wafer sliced from a silicon single crystal ingot grown by a CZ method is heated to a first highest achieved temperature in a range of 1325 ° C or more and 1400 ° C or less in an oxidizing gas atmosphere. After maintaining a 1st highest achieved temperature, the process of performing the 1st heat processing which temperature-falls at the temperature-fall rate of 50 degrees C / sec or more and 250 degrees C / sec or less, and the silicon wafer which performed the said 1st heat treatment in a non-oxidizing gas atmosphere, And heating to the second highest achieved temperature in the range of 900 ° C or more and 1250 ° C or less to maintain the second highest achieved temperature, and then performing a second heat treatment to lower the temperature.

Since the present invention includes such a step, the in-plane uniformity of the BMD density in the radial direction of the bulk portion of the wafer grown by the CZ method can be improved. In addition, the in-plane uniformity of the BMD size can be increased, and the COP of the surface layer portion of the wafer can be further reduced.

1 and 2 are conceptual flowcharts in the cross section of the wafer for explaining the effect of the present invention, FIG. 1 shows the effect by the first heat treatment, and FIG. 2 shows the effect by the second heat treatment.

In the first heat treatment, in the oxidizing gas atmosphere (oxygen (O ₂ ) in FIG. 1), the maximum attained temperature is raised and maintained within a range of 1325 ° C or more and 1400 ° C or less (first highest achieved temperature). The inner wall oxide film (SiO ₂ ) is dissolved to form a void (FIG. 1B). Moreover, this void disappears by spreading as public. Or / and the void disappears by filling with a large amount of interstitial silicon (not shown) injected into the wafer by the oxidizing gas atmosphere (FIG. 1C). In addition, since the BMD nucleus introduced during the single crystal growth is heat treated within the range of the maximum attained temperature, it dissolves and disappears in the wafer (Fig. 1 (b) to (c)).

In the second heat treatment, in the non-oxidizing gas atmosphere (argon (Ar in FIG. 2)), the maximum achieved temperature is raised and maintained in the range of 900 ° C to 1250 ° C, so that oxygen in the surface layer portion of the wafer is released from the wafer surface. It diffuses and also spreads outwardly to a bulk part (FIG. 2 (b)). Therefore, BMD nuclei do not precipitate in the surface layer portion of the wafer, but precipitate in the bulk portion (FIG. 2C).

As described above, the BMD nuclei introduced at the time of single crystal growth are dissolved and extinguished in the wafer by the first heat treatment, and the BMD nuclei are newly precipitated in the bulk portion in the second heat treatment. Therefore, in the second heat treatment, the BMD nuclei can be newly precipitated and grown in a state in which the fluctuation of the BMD nuclei introduced during single crystal growth is eliminated (cancelled once). Therefore, in addition to the in-plane uniformity of the BMD density in the radial direction of the wafer, the in-plane uniformity of the BMD size can also be increased.

It is preferable that the highest achieved temperature (1st highest achieved temperature) in 1st heat processing is in the range of 1325 degreeC or more and 1400 degrees C or less.

When the first highest achieved temperature is a low temperature of less than 1325 ° C, it is difficult to dissolve and extinguish the BMD nuclei introduced during single crystal growth. Therefore, it is difficult to exclude fluctuations in the BMD nuclei introduced during single crystal growth, and it is difficult to increase the in-plane uniformity of the BMD size in addition to the in-plane uniformity of the BMD density in the radial direction of the wafer. When the said 1st highest achieved temperature exceeds 1400 degreeC, since it becomes high temperature, slip dislocations etc. tend to arise and are unpreferable.

As for the upper limit of the said 1st highest achieved temperature, it is more preferable that it is 1380 degrees C or less in order to make life longer as the heat processing apparatus to be used longer.

It is preferable that the temperature-fall rate from the said 1st highest achieved temperature in a said 1st heat processing is 50 degrees C / sec or more and 250 degrees C / sec or less.

As described above, the first heat treatment is performed in an oxidizing gas atmosphere, so that a large amount of interstitial silicon is generated, but at the same time, a pore of thermal equilibrium concentration is also generated. The vacancy together with the interstitial oxygen forms an O2-V complex. The O2-V complex then becomes a starting point for the generation of BMD nuclei in the second heat treatment.

In addition, when the temperature-falling rate is less than 50 ° C./sec, the vacancy diffuses outward and disappears during the temperature drop, so that the O 2 -V complex may not be formed.

Therefore, by making the temperature-fall rate in a 1st heat processing into 50 degreeC / sec or more, a lot of said generated voids can remain | survive in a bulk part. For this reason, in the said 2nd heat processing, generation | occurrence | production of a BMD nucleus and growth (densification of BMD density) can fully be attained.

In addition, when the said temperature-fall rate is too fast, since a slip dislocation may generate | occur | produce on a wafer for rapid temperature-fall, it is preferable that the upper limit is 250 degrees C / sec or less.

As for the temperature-fall rate in a said 1st heat processing, it is more preferable that they are 120 degreeC / sec or more and 250 degrees C / sec or less.

By setting it as such a temperature-fall rate, the BMD density in the radial direction of the bulk part of a wafer, and the in-plane uniformity of the size can further be improved.

It is preferable to perform temperature-fall in the said temperature-fall rate from the said 1st highest achieved temperature from 400 degreeC or more and 600 degrees C or less from a viewpoint of suppression of diffusion of the said lattice silicon, productivity, etc.

In addition, the heat treatment method of the silicon wafer according to the present invention can improve the BMD density and the in-plane uniformity of the size even when the OSF ring is present in the radial direction of the wafer, that is, when the BMD has a low density region in the wafer plane. .

3 is a conceptual flowchart in the cross section of the wafer for explaining the effect of the present invention in the first heat treatment when the OSF ring is present in the radial direction of the wafer.

In the wafer in which the OSF ring exists, as described above, there is a BMD low-density region in which the BMD density greatly decreases in the vicinity of the OSF ring (FIG. 3A).

In the heat treatment method of the silicon wafer according to the present invention, even if such a wafer is subjected to the first heat treatment, the COP and BMD nuclei disappear by the same mechanism as described in FIG. 1 ((b) to (c) of FIG. 3). )).

Therefore, since the fluctuation of the BMD nucleus in the BMD low density region can be eliminated, even if the OSF ring exists in the radial direction of the wafer, the in-plane uniformity of the BMD density and its size can be improved.

In the heat treatment method of the silicon wafer according to the present invention, when the oxygen concentration of the wafer to be heat-treated is high, that is, when the oxygen concentration is controlled to be high during single crystal growth, COP remains in the surface layer portion of the wafer after the first heat treatment. There is a case.

4 and 5 are conceptual flowcharts in the cross section of the wafer for explaining the effect of the present invention when the oxygen concentration of the wafer to be heat treated is high. 4 shows the effect by the first heat treatment, and FIG. 5 shows the effect by the second heat treatment.

In the first heat treatment, since oxygen contained in the oxidizing gas atmosphere diffuses inward from the wafer surface to the surface layer portion, when the oxygen concentration of the wafer to be heat treated is high, the oxygen concentration of the surface layer portion is near the solid melting limit (Fig. 4 ( a) to (b)). Therefore, in the surface layer part, the inner wall oxide film of COP becomes difficult to melt | dissolve. As a result, even if a large amount of interstitial silicon is introduced, it cannot be filled in the COP, so that the COP remains in the surface layer portion. In addition, in the BMD nuclei introduced at the time of single crystal growth, even when the oxygen concentration is high, since the BMD nuclei are small, they dissolve and disappear in the wafer (Figs. 4A to 4C).

However, as shown in FIG.4 (c), even if COP remained in the surface layer part in 1st heat processing, in 2nd heat processing, 900 degreeC or more and 1250 degrees C or less in a non-oxidizing gas atmosphere (argon in FIG. 5). The heat treatment is performed at. By this heat treatment, oxygen diffuses outward from the surface layer portion and further diffuses outward in the bulk portion, so that the oxygen concentration of the surface layer portion decreases near the solid melting limit (Fig. 5 (b)).

Therefore, since the oxygen concentration decreases in the surface layer portion by performing the second heat treatment, the inner wall oxide film of the COP present in the surface layer portion is dissolved and becomes void. Thereafter, the void disappears by rearrangement of silicon atoms ((b) to (c) of FIG. 5). 2, the BMD nuclei are not precipitated at the surface layer portion of the wafer, but are precipitated at the bulk portion (FIG. 5C).

As mentioned above, even if the oxygen concentration of the wafer to heat-process is high, the BMD density of the bulk part and the in-plane uniformity of the size can be improved, and also the COP of the surface layer part of a wafer can be reduced. can do.

In addition, the case where the oxygen concentration in this invention is high means that the oxygen concentration of a wafer is 1.2 * 10 <^18> atoms / cm <3> (old-ASTM) or more.

When the first heat treatment is performed not in an oxidizing gas atmosphere but in a non-oxidizing gas atmosphere (reducing gas atmosphere (hydrogen gas, nitrogen gas, etc.) or inert gas atmosphere (argon gas, etc.)), the BMD of the bulk portion introduced during single crystal growth The nucleus cannot be destroyed, and conversely, the BMD nucleus is grown. This is because the outward diffusion of oxygen from the surface layer portion to the bulk portion is greatly promoted.

The partial pressure of the oxygen gas in the oxidizing gas atmosphere is preferably 20% or more and 100% or less (preferably 100% oxygen gas).

By setting the partial pressure of the oxygen gas to 20% or more, a large amount of interstitial silicon can be injected into the wafer, and thus COP can be reliably reduced, which is preferable.

Moreover, it is preferable that gas other than oxygen gas in the said oxidizing gas atmosphere (except the case where the partial pressure of oxygen gas is 100%) is argon gas.

By using argon gas, formation of other films, such as nitride films, chemical reactions, etc., can be more reliably avoided.

It is preferable that the highest achieved temperature (2nd highest achieved temperature) in the said 2nd heat processing exists in the range of 900 degreeC or more and 1250 degrees C or less.

When the said 2nd highest achieved temperature is less than 900 degreeC, since it is low temperature, outward diffusion of oxygen as mentioned above becomes difficult to occur. For this reason, it is difficult to melt | dissolve the inner wall oxide film of COP which remain | survives in the surface layer part of a wafer, and it is difficult to dissipate the COP of this surface layer part.

When the said 2nd highest achieved temperature exceeds 1250 degreeC, outward diffusion of oxygen from the surface layer part of a wafer becomes large. As a result, the oxygen concentration of the surface layer portion greatly decreases, and the pinning effect of the slip dislocation caused by oxygen decreases, so that slip dislocations may occur on the wafer.

When the second heat treatment is performed not in the non-oxidizing gas atmosphere but in the oxidizing gas atmosphere described above, oxygen diffuses inwardly in the surface layer portion of the wafer. Therefore, in the case of the silicon wafer with high oxygen concentration, the oxygen concentration of the surface layer portion is maintained in a high state. Therefore, since the inner wall oxide film of the COP remaining in the surface layer portion of the wafer becomes difficult to dissolve in the second heat treatment, it is sometimes difficult to dissipate the COP in the surface layer portion.

It is preferable that the said non-oxidizing gas atmosphere is a non-oxidizing gas (preferably argon 100% gas) containing argon gas.

By using argon gas, heat treatment can be performed without formation of other films such as nitride films, chemical reactions, or the like.

It is preferable to perform the said 1st heat processing by RTP using the well-known rapid rising-temperature heat processing (RTP: Rapid Thermal Process, hereafter only called RTP) apparatus. In addition, RTP here means the high temperature rising temperature heat processing whose temperature rising and temperature-fall rate are 1 degree-C / sec or more.

6 is a cross-sectional conceptual view showing an example of the RTP apparatus used in the heat treatment method of the silicon wafer according to the present invention.

The RTP apparatus 10 shown in FIG. 6 includes a reaction chamber 20 for accommodating the wafer W and performing heat treatment, and a wafer holding part provided in the reaction chamber 20 to hold the wafer W ( 30 and a heating unit 40 for heating the wafer W. In the state where the wafer W is held by the wafer holding part 30, the first space 20a and the second space 20b are formed. The first space 20a is a space surrounded by the inner wall of the reaction chamber 20 and the surface (device formation surface) W1 side of the wafer W. As shown in FIG. The second space 20b is a space surrounded by the inner wall of the reaction chamber 20 and the back surface W2 side of the wafer W facing the surface W1 side.

The reaction chamber 20 includes a supply port 22 and a discharge port 26. The supply port 22 supplies the atmospheric gas F _A (solid arrow) into the first space 20a and the second space 20b. In addition, the discharge port 26 discharges the supplied atmosphere gas F _A from the first space 20a and the second space 20b. The reaction chamber 20 is made of, for example, quartz.

The wafer holding portion 30 holds a susceptor 32 holding the outer circumference of the back surface W2 of the wafer W in a ring shape, and the susceptor 32, with the center of the wafer W as an axis. The rotating body 34 which rotates the susceptor 32 is provided. The susceptor 32 and the rotating body 34 are comprised with SiC, for example.

The heating part 40 is comprised by the some halogen lamp 50. As shown in FIG. The halogen lamp 50 is disposed outside the reaction chamber 20 above the front surface W1 and below the rear surface W2 of the wafer W held by the wafer holding unit 30, and the halogen lamp 50 is disposed. The wafer W is heated from both sides by lamp heating by light irradiation of 50.

The heat treatment using the RTP apparatus 10 shown in FIG. 6 is performed as follows. The wafer W is introduced into the reaction chamber 20 from a wafer introduction port (not shown) provided in the reaction chamber 20, and the outer circumferential portion of the back surface W2 of the wafer W is susceptor of the wafer holding portion 30. It keeps ring shape on (32). Then, the atmosphere gas F _A is supplied from the supply port 22, and the wafer W is heated by the heating unit 40 while the wafer W is rotated.

7 is a conceptual diagram illustrating an example of a temperature sequence of a first heat treatment by RTP.

As shown in Fig. 7, a silicon wafer is held on a rotatable susceptor provided in a reaction space of a known RTP apparatus maintained at a temperature T0 (preferably 400 ° C or higher and 600 ° C or lower), and within the reaction space. Supply an oxidizing gas. Next, the temperature is rapidly raised from the temperature T0 to the temperature of the temperature ΔTu1 (° C / sec) from 1325 ° C or more to 1400 ° C or less (temperature T1), which is the first highest achieved temperature, and the time determined by the temperature T1. (t1 (sec)) Keep it constant. Thereafter, the temperature is rapidly lowered from the temperature T1 at the temperature drop rate ΔTd1 (° C./sec), and the temperature is lowered to, for example, the temperature T0.

The said temperature T0, T1 is shown below the wafer holding part 30, when the wafer W is installed in the reaction chamber 20 of the RTP apparatus 10 as shown in FIG. It is the surface temperature of the wafer W measured by the radiation thermometer which does not (the average temperature when two or more radiation thermometers are arrange | positioned in the radial direction of the wafer W).

It is preferable that the holding time t1 which maintains a said 1st highest achieved temperature is 1 second or more and 60 second or less.

When the holding time t1 is less than 1 second, it may be difficult to sufficiently dissipate the BMD nuclei and COP introduced during single crystal growth. When the said holding time t1 exceeds 60 second, productivity may fall, and also the problem (impurity diffusion, slip, etc.) resulting from other heat processing may arise.

It is preferable to perform a said 2nd heat processing by the heat processing using a vertical type heat processing apparatus. As the vertical heat treatment device, a known one (for example, a vertical heat treatment device described in JP 2001-85349 A) is used. In addition, the heat processing using the vertical type heat processing apparatus here means that it is a low speed heat processing whose temperature rising and temperature-fall rate are 15 degrees-C / min or less.

8 is a conceptual diagram illustrating an example of a temperature sequence of a second heat treatment using the vertical heat treatment apparatus.

As shown in FIG. 8, the well-known longitudinal boat which hold | maintained several sheets of silicon wafer was installed in the reaction space of the well-known longitudinal heat processing apparatus maintained at temperature T0 (preferably 400 degreeC or more and 600 degrees C or less), A non-oxidizing gas (eg argon gas) is fed into the reaction space. Next, the temperature t2 is raised from the temperature T0 to the second highest achieved temperature at 900 ° C. or more and 1200 ° C. or less (temperature T2) at a temperature raising rate ΔTu2 (° C./minute), and the time t2 determined by the temperature T2. (Minute)) After keeping it constant, it temperature-falls from temperature T2 to temperature-fall rate (DELTA) Td2 (degreeC / min), for example to temperature T0.

It is preferable that the holding time t2 which maintains a said 2nd highest achieved temperature is 1 minute or more and 120 minutes or less.

When the holding time t2 is less than 1 minute, it may be difficult to sufficiently deposit and grow BMD nuclei in the bulk portion of the wafer. In addition, when the oxygen concentration of a silicon wafer is high, the COP in the surface layer part may not fully disappear in this 2nd heat processing. When the said holding time t2 exceeds 120 minutes, productivity may fall, and also the problem (impurity diffusion, slip, etc.) resulting from other heat processing may arise.

The temperature increase rate (ΔTu2 in FIG. 8) to the second highest achieved temperature in the second heat treatment and the temperature decrease rate (ΔTd2 in FIG. 8) from the second highest achieved temperature are 5 ° C./min or more. It is preferable that it is degrees C / min or less.

By setting it as such a temperature increase rate and a temperature decrease rate, generation | occurrence | production of the slip dislocation at the time of the temperature increase of the said 2nd heat processing can be suppressed, and also BMD density can be improved further.

It is preferable that the temperature increase rate (ΔTu1 in FIG. 7) at the time of temperature rising in the said 1st heat processing is 10 degreeC / sec or more and 250 degrees C / sec or less in order to improve productivity and reduce slip generation further.

The growth of the silicon single crystal ingot by the CZ method controls the V / G value (V: pulling speed, G: average value of the temperature gradient in the crystal in the pulling axial direction in the temperature range from the silicon melting point to 1300 ° C.) It is desirable to grow a silicon single crystal ingot comprising a V-rich region in which a large number of voids (COPs) are blown.

Specifically, using a known single crystal pulling apparatus, a seed crystal is brought into contact with the liquid surface of the silicon melt, and the seed crystal is pulled while rotating the seed crystal and the quartz crucible to expand the diameter to the neck portion and the desired diameter. Form an extension. Thereafter, while maintaining the desired diameter, the V / G value is controlled to a predetermined value (for example, 0.25 mm 2 / ° C.min to 0.35 mm 2 / ° C./min) so as to form a V-rich region, thereby forming a straight body. It is carried out by forming a diameter reducing portion for reducing the diameter from the desired diameter and separating it from the silicon melt.

By performing in this way, productivity at the time of single crystal growth can be improved more.

In addition, "it contains a V-rich region" here does not exclude the above-mentioned OSF region.

Next, the manufacturing method of the silicon wafer provided with the heat processing method of the silicon wafer mentioned above is demonstrated.

9 is a process flowchart showing the first embodiment of the method of manufacturing a silicon wafer with the heat treatment method of the silicon wafer according to the present invention.

The first embodiment includes a step (S101) of growing a silicon single crystal ingot by a CZ method, a step (S102) of slicing the silicon single crystal ingot to produce a disk-shaped wafer, and a front and back surface of the produced slice wafer. A step (S103) of planarizing the surface, a step (S104) of mirror-polishing a surface which is at least a semiconductor device formation surface of the planarized wafer, the first heat treatment (S105), and the mirror-polished wafer. The process of performing 2nd heat processing S106 is included.

That is, in the first aspect, the above-described heat treatment method for a silicon wafer is performed on a mirror-polished wafer whose surface is at least a semiconductor device forming surface.

By including such a process, the silicon wafer provided with the above-mentioned effect more reliably can be obtained.

In addition, the planarization treatment includes well-known lapping treatment, one-side grinding treatment, two-side grinding treatment, and etching treatment (for etching treatment, mainly hydrofluoric acid (HF), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water ( Acid etch treatment for immersing the entire surface of the planarized wafer) in an acid etch solution obtained by mixing H ₂ O) at a constant ratio. The mirror polishing includes well-known single side polishing and double side polishing.

That is, the said mirror polishing (S104) from the said planarization process (S103) performs a double-side grinding process, for example after lapping process the front and back surface of the produced slice wafer. Then, the process of double-side polishing, the process of etching after lapping process, and the process of double-side polishing after that are included.

10 is a process flowchart showing a second embodiment of the method of manufacturing a silicon wafer including the heat treatment method of the silicon wafer according to the present invention.

In the second aspect, a step (S201) of growing a silicon single crystal ingot by the CZ method, a step (S202) of slicing the silicon single crystal ingot to produce a disk-shaped wafer, and a front and back surface of the produced slice wafer The step (S203) of planarizing the wafer, the step of performing the first heat treatment (S204) and the second heat treatment (S205) with respect to the planarized wafer, and at least a semiconductor device formation surface of the second heat-treated wafer It includes a step (S206) of mirror polishing the surface to be made.

That is, the said 2nd aspect performs the heat processing method of the silicon wafer mentioned above with respect to the wafer after the planarization process.

By including such a step, in addition to the above-described effects, even if outward diffusion of oxygen from the surface layer portion and the like in the second heat treatment are small, and COP remains in the surface layer portion, the surface layer portion can be removed in a subsequent polishing step. It is preferable because of that.

The planarized wafer to be heat-treated in the second aspect includes a lapping wafer and an etched wafer.

11 is a process flowchart showing a third embodiment of the method of manufacturing a silicon wafer including the heat treatment method of the silicon wafer according to the present invention.

In the third aspect, a step (S301) of growing a silicon single crystal ingot by the CZ method, a step (S302) of slicing the silicon single crystal ingot to produce a disk-shaped wafer, and the produced slice wafer, A step of performing the first heat treatment (S303) and a second heat treatment (S304), a step of planarizing the front and back surfaces of the slice wafer subjected to the second heat treatment (S305), and forming at least a semiconductor device of the planarized wafer It includes a step (S306) of mirror polishing the surface to be a surface.

That is, the said 3rd aspect performs the above-mentioned heat processing method of a silicon wafer with respect to a slice wafer.

By including such a process, the same effect as the above-mentioned 2nd aspect can be acquired.

12 is a process flowchart showing a fourth embodiment of the method of manufacturing a silicon wafer including the heat treatment method of the silicon wafer according to the present invention.

In the fourth aspect, a step (S401) of growing a silicon single crystal ingot by the CZ method, a step of slicing the silicon single crystal ingot (S402) to form a disk-shaped wafer, and a front and back surface of the produced slice wafer A step (S403) of planarizing the wafer, a step (S404) of performing the first heat treatment on the flattened wafer, and a step of mirror polishing the surface of at least the semiconductor device formation surface of the first heat-treated wafer (S405) and the step (S406) of performing the second heat treatment on the mirror polished wafer.

That is, in said 4th aspect, in the above-mentioned heat processing method of a silicon wafer, a 1st heat processing is performed after a planarization process, and a 2nd heat processing is performed after mirror polishing.

By including such a step, in addition to the above-described effects, even if COP remains in the surface layer portion after the first heat treatment, it can be removed in a subsequent polishing step. Thereby, burden reduction of a 2nd heat processing (heat processing temperature, shortening of heat processing time, etc.) can be aimed at.

13 is a process flowchart showing the fifth embodiment of the method of manufacturing a silicon wafer including the heat treatment method of the silicon wafer according to the present invention.

In the fifth aspect, a step (S501) of growing a silicon single crystal ingot by the CZ method, a step (S502) of slicing the silicon single crystal ingot to produce a disk-shaped wafer, and the produced slice wafer, The step (S503) of performing the first heat treatment, the step (S504) of planarizing the front and back surfaces of the first heat-treated wafer, and the step of mirror-polishing the surface to be at least a semiconductor device formation surface of the planarized wafer (S505) and the step (S506) of performing the second heat treatment on the mirror polished wafer.

That is, in said 5th aspect, in the above-mentioned heat processing method of a silicon wafer, a 1st heat processing is performed with respect to a slice wafer, and a 2nd heat processing is performed after mirror polishing.

By including such a process, the same effect as the above-mentioned 4th aspect can be acquired.

[Example]

EMBODIMENT OF THE INVENTION Hereinafter, although this invention is demonstrated further more concretely based on an Example, this invention is not limitedly interpreted by the following Example.

(Test 1)

A large number of atomic cavities (COPs) are controlled by controlling the V / G value (V: pulling rate, G: average value of the temperature gradient in the crystal in the pulling axial direction in the temperature range from the silicon melting point to 1300 ° C.) by the CZ method. When the slice was sliced, a silicon single crystal ingot including a V-rich region where an OSF ring was generated in a part of the surface of the wafer was grown. The mirror-polished silicon wafer (300 mm in diameter, thickness of 775 탆, oxygen concentration of 1.2 to 1.3 x 10 ¹⁸ atoms / cm 3) sliced from both sides sliced from the above region was introduced into a reaction space of a known RTP apparatus maintained at 400 ° C. . And in the temperature sequence as shown in FIG. 7, in the oxygen 100% gas (flow rate 20 slm) atmosphere, the temperature increase rate is 50 degreeC / sec, the holding time of the highest achieved temperature is 15 second (however, it is 30 regarding the comparative example 1). The first heat treatment was performed by changing the maximum achieved temperature and the temperature-fall rate in seconds) to fabricate a plurality of wafers having different heat treatment conditions.

Thereafter, the wafer subjected to the first heat treatment was introduced into the reaction space of a known vertical heat treatment apparatus maintained at 600 ° C. And in the temperature sequence as shown in FIG. 8, in a 100% argon gas (flow rate 30 slm) atmosphere, the temperature increase rate shall be 1-5 degreeC / min, the highest achieved temperature is 1200 degreeC, and the holding time is 1 hour, The 2nd heat processing which temperature-falls to 600 degreeC was performed at the temperature-fall rate 1-5 degree-C / min.

Moreover, as a conventional example, the wafer which performed only the said 2nd heat processing without the said 1st heat processing was produced.

Next, the BMD precipitation heat treatment (4 hours at 800 ° C. and 16 hours at 1000 ° C.) was performed on the wafer subjected to the second heat treatment in an oxygen 100% gas atmosphere. The wafer subjected to the BMD precipitation heat treatment was measured by IR topography (MO-441, manufactured by Latex Corporation), and the bulk portion (7 μm to 300 μm in depth) from the wafer surface in the radial direction from the center of the wafer to the outer periphery. BMD density and scattered light intensity in the micrometer) were evaluated. Further, from the evaluated scattered light intensity, using the formula (1), the center of the wafer (0 mm), the position (in the BMD low density region) of 110 mm in the radial direction from the center of the wafer, and the position (wafer circumference) of 145 mm The BMD size in three points was computed.

BMD size = scattered light intensity ^(1/6) x 20 ... (1)

Furthermore, the number of defects of the surface layer part from the surface of the wafer which performed the said 2nd heat processing to the depth of 5 micrometers was evaluated using the LSTD scanner MO601 by a Latex company, and the defect density was computed.

Furthermore, the slip length generated on the back surface of the wafer subjected to the second heat treatment was evaluated by X-ray topography (XRT300, manufactured by Rigaku Corporation).

Table 1 shows the test conditions and evaluation results (surface layer defect density and BMD average size) in this test, and FIGS. 14 to 17 show BMDs in the wafer radial direction from the center of the wafer to the outer periphery in each condition of the test. In-plane distribution of density is shown, respectively.

As can be seen from Table 1 and FIGS. 14 to 17, the in-plane uniformity of the BMD size in the radial direction of the wafer was obtained by performing the first heat treatment before the second heat treatment than when only the second heat treatment (the conventional example 1) was performed. It is recognized that it can improve sex.

In addition, when the highest achieved temperature of the first heat treatment is 1300 ° C. or less (Comparative Examples 1 and 2), and even when the temperature reduction rate is 25 ° C./sec (Comparative Example 3) even at 1350 ° C. (Comparative Example 3), the BMD density in the radial direction of the wafer And in-plane uniformity of the size is recognized as insufficient.

On the other hand, when it is 1325 degreeC or more and a temperature-fall rate is 50 degreeC / sec or more (9 in Example 1), it is recognized that BMD density in the radial direction of a wafer, and in-plane uniformity of the size become high. Moreover, when the temperature-fall rate is 120 degrees C / sec or more (Examples 2, 3, 5, 6, 8, 9), it is recognized that BMD density and its size become substantially flat together.

In addition, it is recognized that the defect density of the surface layer portion is low density under any condition.

In addition, the slip dislocations on the back surface of the wafer were not confirmed in all the conditions.

(Test 2)

The highest achieved temperature in the said 1st heat processing was 1325 degreeC, 1350 degreeC, and 1380 degreeC, and the temperature-fall rate (degreeC / sec) was 50 degreeC / sec. Furthermore, the 2nd highest achieved temperature was changed, and the 2nd heat processing was performed on the conditions similar to the test 1 other than that.

Next, with respect to the wafer subjected to the second heat treatment, the number of defects in the surface layer portion from the surface of the wafer subjected to the second heat treatment to a region of 5 탆 depth was determined using the LSTD scanner MO601 manufactured by Latex Corporation in the same manner as in Test 1. It evaluated and the defect density was computed.

Furthermore, the slip length generated on the back surface of the wafer subjected to the second heat treatment was evaluated by X-ray topography (XRT300, manufactured by Rigaku Corporation).

Table 2 shows the test conditions and evaluation results (surface layer defect density) in this test.

In Comparative Examples 5, 7, and 9, slip dislocations having a length of 5 mm to 10 mm were observed on the back surface of the wafer, but other conditions were not confirmed.

As can be seen from the above results, in the second heat treatment, when the maximum achieved temperature is 800 ° C. (Comparative Examples 4, 6, 8), it is recognized that the defect density of the surface layer portion is increased. In addition, when the highest achieved temperature is 1300 ° C (Comparative Examples 5, 7, 9), occurrence of slip is recognized.

On the other hand, in 2nd heat processing, when the highest achieved temperature is 900 degreeC or more and 1250 degrees C or less, it is recognized that the defect density of a surface layer part will also be less than 1.0 / cm <2>.

10 RTP unit 20 reaction chamber
30 Wafer Holder 40 Heater
T1 first highest reached temperature T2 second highest reached temperature
T3 medium temperature

Claims (4)

After the silicon wafer sliced from the silicon single crystal ingot grown by the Czochralski method is heated up to the first highest achieved temperature in the range of 1325 ° C or more and 1400 ° C or less in an oxidizing gas atmosphere, the first highest temperature is maintained. Performing a first heat treatment for lowering at a temperature lowering rate of 50 ° C / sec or more and 250 ° C / sec or less,
After heating the silicon wafer subjected to the first heat treatment to a second highest achieved temperature within a range of 900 ° C or more and 1250 ° C or less in a non-oxidizing gas atmosphere to maintain the second highest achieved temperature, the second heat treatment is performed. Process
Heat treatment method of a silicon wafer comprising a. The method for heat treatment of a silicon wafer according to claim 1, wherein the temperature-fall rate in the first heat treatment is 120 ° C / sec or more and 250 ° C / sec or less. The method of heat treatment of a silicon wafer according to claim 1, wherein the temperature increase rate up to the second highest achieved temperature in the second heat treatment is 1 ° C / minute or more and 5 ° C / minute or less. The method of heat treatment of a silicon wafer according to claim 2, wherein the temperature increase rate up to the second highest achieved temperature in the second heat treatment is 1 ° C / minute or more and 5 ° C / minute or less.

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