KR20130022600A - Liquid crystal display device and method for driving the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a method for driving the same are provided to display the gray lever of red, green, and blue light. CONSTITUTION: A light source of a backlight unit irradiates light to a display panel. A data driving unit supplies data voltage to data lines. A gate driving unit supplies gate pulse to gate lines. A first sub pixel(SUB1) displays two colors among red (R), green(G) and blue(B) for a first frame period. A second sub pixel(SUB2) displays the other color for the first frame period.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to a liquid crystal display and a driving method thereof.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

Conventional liquid crystal display device receives the white light (W) from the backlight unit (BLU) as shown in Figure 1, modulates the input light according to the gray level (Gray level) in the liquid crystal cell LC, R color filter (RC) ), G color filter (GC), and B color filter (BC) are used to output red light (R), green light (G), and blue light (B). The user receives an image of the white light W represented by the red light R, the green light G, and the blue light B output from the liquid crystal display. In the conventional LCD, not only part of the white light W emitted from the backlight unit BLU is blocked by the black matrix BM, but also the R color filter RC, the G color filter GC, and the B color filter. Since it is required to transmit (BC), there is a disadvantage that the ratio of the output light, that is, the transmittance is lower than that of the input light.

In order to improve the transmittance of the liquid crystal display, red light (R), green light (G), and blue light (B) are sequentially input as shown in FIG. 2, and are sequentially modulated in the liquid crystal cell LC, and then red light (R). A field sequential driving method for sequentially outputting green light (G) and blue light (B) has been proposed. The user receives an image of white light (W) represented by red light (R), green light (G), and blue light (B) sequentially output from the liquid crystal display. The liquid crystal display of the field sequential driving method not only removes a part of the black matrix BM but also removes color filters, and thus has an advantage of increasing transmittance as compared to the conventional liquid crystal display. However, the field sequential driving type liquid crystal display sequentially modulates the red light R, the green light G, and the blue light B in the liquid crystal cell LC according to gray levels for one frame period. Therefore, the frame frequency should be increased by three times as compared with the conventional liquid crystal display device. In this case, the response time of the liquid crystal should be faster as the frame frequency is increased, but the gray level of each of the red light R, the green light G, and the blue light B may not be correctly displayed due to the delay of the liquid crystal response time. Failure to do so may occur.

The present invention provides a liquid crystal display device and a driving method thereof capable of sufficiently displaying the gray level of each of red light, green light, and blue light with sufficient response time of a liquid crystal.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a display panel including pixels arranged in a matrix in a cell region defined by an intersection of data lines and gate lines; A backlight unit including light sources emitting light to the display panel; A data driver supplying data voltages to the data lines; And a gate driver configured to supply a gate pulse to the gate lines in synchronization with the data voltage, wherein each of the pixels sequentially displays two colors of red, green, and blue during one frame period. Subpixels; And a second sub pixel displaying a color not displayed on the first sub pixel during the one frame period.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, comprising: a display panel including pixels arranged in a matrix in an area defined by an intersection of data lines and gate lines; A backlight unit including light sources emitting light to the display panel; A data driver supplying data voltages to the data lines; And a gate driver configured to supply a gate pulse to the gate lines in synchronization with the data voltage, the liquid crystal display comprising: two of red, green, and blue for one frame period to a first sub pixel of each of the pixels; Sequentially displaying branch colors; And displaying a color that is not displayed in the first sub pixel during the one frame period, in the second sub pixel of each of the pixels.

The present invention divides a pixel into a first subpixel and a second subpixel, causes the first subpixel to sequentially display two colors of red, green, and blue, and the second subpixel is a first subpixel. Allows to display colors that are not displayed in. As a result, since the present invention only needs to display two colors in the first sub-pixel during one frame period, since the liquid crystal response time is sufficient, gray levels of red light, green light, and blue light can be properly displayed. In addition, the present invention can reduce the aperture ratio since the black matrix and the color filter are reduced. In addition, the present invention can reduce the brightness of the light sources of the backlight unit due to the increase in the luminance due to the aperture ratio, it is possible to reduce the power consumption.

Furthermore, while the conventional field sequential driving method sequentially displays three colors in one pixel during one frame period, the present invention sequentially displays two colors in one subpixel during one frame period, and another subpixel. Display one color in. As a result, the present invention can improve the color breakup phenomenon than the conventional field sequential driving method.

1 is a cross-sectional view schematically illustrating a portion of a conventional liquid crystal display.
2 is a cross-sectional view schematically illustrating a portion of a liquid crystal display device having a field sequential driving method.
3 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
4 is a cross-sectional view schematically illustrating a portion of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 5 shows the colors produced due to their mixing with red, green and blue.
6 is a plan view illustrating pixels formed in a pixel array of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 7 is a diagram illustrating gate pulses supplied to the first and second pixel circuits of FIG. 6, liquid crystal response characteristics of the first and second subpixels, and timings of on / off timings of light sources of the backlight unit.
FIG. 8 is a diagram illustrating data addressing of the display panel of FIG. 3 and scanning lighting of the backlight unit.
9 is a diagram illustrating a block of a display panel and a backlight unit of FIG. 3.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. Component names used in the following description may be selected in consideration of ease of specification, and may be different from actual product part names.

3 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention. 4 is a cross-sectional view schematically illustrating a portion of a liquid crystal display according to an exemplary embodiment of the present invention. 3 and 4, the liquid crystal display of the present invention includes a display panel 10, a backlight unit 30, a gate driver 110, a data driver 120, a backlight driver 130, and a timing controller 140. ), The backlight controller 150, the host system 160, and the like.

The display panel 10 displays an image under the control of the timing controller 140. In the display panel 10, a liquid crystal layer is formed between two substrates S1 and S2. Data lines and gate lines (or scan lines) intersect each other on the lower substrate S1 of the display panel 10, and pixels are matrixed in cell regions defined by the data lines and the gate lines. TFT arrays arranged in the form are formed. Each pixel of the display panel 10 is connected to a thin film transistor and is driven by an electric field between the pixel electrode and the common electrode.

A color filter array including a black matrix, a color filter, a common electrode, and the like is formed on the upper substrate S2 of the display panel 10. An upper polarizing plate P2 is attached to the upper substrate S2 of the display panel 10, and a lower polarizing plate P1 is attached to the lower substrate S1. The light transmission axis of the upper polarizer P2 and the light transmission axis of the lower polarizer P1 may be formed to be orthogonal to each other. In addition, an alignment layer for setting a pre-tilt angle of the liquid crystal is formed on the upper substrate S2 and the lower substrate S1. A spacer for maintaining a cell gap of the liquid crystal cell LC is formed between the upper substrate S2 and the lower substrate S1 of the display panel 10. The common electrode is formed on the upper substrate S2 in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is similar to the in plane switching (IPS) mode and the fringe field switching (FFS) mode. In the horizontal electric field driving method, the pixel electrode is formed on the lower substrate S1 together with the pixel electrode. The liquid crystal mode of the display panel 10 may be implemented in any of the liquid crystal modes as well as the above-described TN mode, VA mode, IPS mode, and FFS mode.

Pixels P of the display panel 10 include a first sub-pixel SUB1 and a second sub-pixel SUB2. The first subpixel SUB1 may be implemented as a subpixel that sequentially displays two colors of red, green, and blue. The second subpixel SUB2 may be implemented as a subpixel displaying a color not displayed on the first subpixel SUB1. The color expressed by the first and second sub-pixels SUB1 and SUB2 is determined by the color filter. The first color filter CF1 of the first sub-pixel SUB1 is implemented as a color filter that passes two wavelengths of red, green, and blue, and the second color filter CF2 is a first sub-pixel ( It may be implemented as a color filter for passing a wavelength of a color not indicated in SUB1).

5 shows the colors created due to their mixing with red, green, and blue. As illustrated in FIG. 5, the first subpixel SUB1 is implemented as a subpixel that sequentially displays red and green, and the second subpixel SUB2 is a subpixel that displays blue. It can be implemented as. In this case, the first color filter CF1 may be implemented as a yellow color filter capable of passing light of a red wavelength and light of a green wavelength, and the second color filter CF2 may be blue ( Blue) Implemented as a blue color filter that can pass light of the wavelength. The yellow color filter passes the light of red wavelength and the light of the green wavelength, does not pass the light of the remaining wavelengths, and the blue color filter passes the light of blue wavelength. And do not pass light of the remaining wavelengths.

As another example, the first sub-pixel SUB1 is implemented as a sub-pixel displaying green and blue sequentially, and the second sub-pixel SUB2 is a sub displaying red. It can be implemented in pixels. In this case, the first color filter CF1 is implemented as a cyan color filter that can pass light having a green wavelength and light having a blue wavelength, and the second color filter CF2 has a red color ( Red) Implemented as a red color filter that can pass light of the wavelength. Cyan color filter passes the light of green wavelength and blue wavelength light, does not pass the light of the remaining wavelength, red color filter passes the light of red wavelength And do not pass light of the remaining wavelengths.

As another example, the first sub-pixel SUB1 is implemented as a sub-pixel displaying red and blue sequentially, and the second sub-pixel SUB2 is a sub-displaying green. It can be implemented in pixels. In this case, the first color filter CF1 is implemented as a magenta color filter capable of passing light of red wavelength and light of blue wavelength, and the second color filter CF2 is green ( Green) Implemented as a green color filter that can pass light of wavelengths. The Magenta color filter passes through the red and blue wavelengths and does not pass through the remaining wavelengths. The green color filter passes through the green wavelengths. And do not pass light of the remaining wavelengths.

Hereinafter, for convenience of description, the first subpixel SUB1 is implemented as a subpixel sequentially displaying red and green, and the second subpixel SUB2 displays blue. The description has been made based on the implementation of subpixels.

The first and second color filters CF1 and CF2 are formed on the upper substrate S2. The lower substrate S1 of the first subpixel SUB1 may include a first pixel circuit including a first thin film transistor (T1), a first pixel electrode PE1, a first storage capacitor, and the like. PC1 is formed, and a second pixel circuit PC2 including a second TFT T2, a second pixel electrode PE2, a second storage capacitor, and the like is formed on the lower substrate S2 of the second subpixel SUB2. ) Is formed. Detailed description of the first and second pixel circuits PC1 and PC2 will be described later with reference to FIG. 5.

As the display panel 10, a transmissive liquid crystal display panel that modulates light from the backlight unit 30 may be selected. The backlight unit 30 includes a light source, a light guide plate (or a diffuser plate), a plurality of optical sheets, and the like, which light up according to a driving current supplied from the backlight unit driver 130. The backlight unit 30 may be implemented as a direct type backlight unit. The light sources of the backlight unit 30 may be any one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), and an organic light emitting diode (OLED). It may include a light source or two or more kinds of light sources. In addition, the light sources of the backlight unit 30 may be implemented with a cold cathode electron gun which is a light source of a field emission display (FED).

Each of the light sources of the backlight unit includes a red light source that emits light of red wavelength R, a green light source that emits light of green wavelength G, and a blue light source that emits light of blue wavelength B. Among the red, green, and blue light sources, a light source having the same color as the second color filter CF2 is disposed to irradiate light on the second sub-pixel SUB2, and the light sources of the remaining two colors are the first sub-pixel SUB1. Is arranged to irradiate light on.

The backlight unit driver 130 generates a driving current for turning on light sources of the backlight unit 30. The backlight unit driver 130 turns on / off a driving current supplied to the light sources under the control of the backlight controller 150. The backlight controller 150 adjusts the backlight brightness and the lighting timing according to the global / local dimming signal DIM input from the host system 160 and the backlight control signal C _BLU input from the timing controller 140. The data is output to the backlight unit driver 130 in the SPI (Serial Pheripheral Interface) data format. The backlight controller 150 may be included in the timing controller 140.

The data driver 120 includes a plurality of source drive ICs. The source drive ICs convert the image data RGB input from the timing controller 140 into positive / negative gamma compensation voltages to generate positive / negative analog data voltages. The positive / negative analog data voltages output from the source drive ICs are supplied to the data lines D of the display panel 10.

The gate driver 110 sequentially supplies gate pulses synchronized with the data voltage to the gate lines G of the display panel 10 under the control of the timing controller 140. The gate driver 110 may be composed of a plurality of gate drive integrated circuits each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, have. Alternatively, the gate driver 110 may be directly formed on the lower substrate of the display panel 10 by using a gate drive IC in panel (GIP) method. In the GIP method, the level shifter may be mounted on a printed circuit board (PCB), and the shift register may be formed on a lower substrate of the display panel 10.

The timing controller 140 may be configured to output image data RGB, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK, and the like output from the host system 160. The gate driver control signal is output to the gate driver 110 based on the signals, and the data driver control signal is output to the data driver 120. The gate driver control signal includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse (GSP) controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driver 110.

The data driver control signal includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like. . The source start pulse SSP controls the data sampling start time of the data driver 120. The source sampling clock is a clock signal that controls the sampling operation of the data driver 120 based on the rising or falling edge. If the digital video data to be input to the data driver 120 is transmitted using a mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted. The polarity control signal POL inverts the polarity of the data voltage output from the data driver 120 every L (L is a natural number) horizontal period period. The source output enable signal SOE controls the output timing of the data driver 120.

The timing controller 140 generates a gate driver control signal and a data driver control signal multiplied by P (P is a natural number of 2 or more) times, preferably 2 times, than the input frame frequency. The input frame frequency is 50 Hz in PAL (Phase Alternate Line) scheme and 60 Hz in NTSC (National Television Standards Committee) scheme. Therefore, the timing controller 140 generates a gate driver control signal and a data driver control signal at a frame frequency of 120 Hz when the input frame frequency is doubled. Therefore, the gate driver 110 and the data driver 120 are driven at a frame frequency of 120 Hz. A detailed description of the gate pulse output of the gate driver 110 and the data voltage supply of the data driver 120 will be described later with reference to FIGS. 7 and 8.

The host system 160 includes a system on chip (hereinafter referred to as "SoC") with a built-in scaler to display image data input from an external video source device on the display panel 10. Convert to a data format of the appropriate resolution. The host system 160 supplies the image data RGB to the timing controller 140 through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface.

6 is a plan view illustrating a pixel circuit formed in a pixel array of a liquid crystal display according to an exemplary embodiment of the present invention. 6 illustrates a first pixel circuit PC1 of a first subpixel SUB1 of a pixel P and a second pixel circuit PC2 of a second subpixel SUB2 according to an exemplary embodiment of the present invention. Referring to FIG. 6, the first subpixel SUB1 is formed larger than the second subpixel SUB2. The first subpixel SUB1 is preferably formed to be twice as large as the second subpixel SUB1, but is not limited thereto. That is, the sizes of the first sub-pixel SUB1 and the second sub-pixel SUB2 may be determined through a preliminary experiment in consideration of color reproducibility.

The first pixel circuit PC1 of the first subpixel SUB1 includes a first TFT T1, a first pixel electrode PE1, a first storage capacitor (not shown), and the like. The first TFT T1 is turned on in response to the gate pulse GPn of the gate line Gn, where n is a natural number, so that the data voltage of the odd data line (D _{2m -1} m is a natural number) of the first pixel electrode ( To PE1). The gate electrode of the first TFT T1 is connected to the gate line Gn, the source electrode is connected to the odd data line D _{2m −1} , and the drain electrode is connected to the first pixel electrode PE1. The data voltage supplied through the first TFT T1 is charged in the first pixel electrode PE1, and the first storage capacitor (not shown) receives the data voltage charged in the first pixel electrode PE1 for a predetermined period of time. Serves to maintain. The first subpixel SUB1 is driven by an electric field between the first pixel electrode PE1 and the common electrode.

The second pixel circuit PC2 of the second subpixel SUB2 includes a second TFT T2, a second pixel electrode PE2, a second storage capacitor (not shown), and the like. The second TFT T2 is turned on in response to the gate pulse GPn of the gate line Gn to supply the data voltage of the even data line D _2m to the second pixel electrode PE2. The gate electrode of the second TFT T2 is connected to the gate line Gn, the source electrode is connected to the even data line D _2m , and the drain electrode is connected to the second pixel electrode PE2. The data voltage supplied through the second TFT T2 is charged in the second pixel electrode PE2, and the second storage capacitor (not shown) receives the data voltage charged in the second pixel electrode PE2 for a predetermined period of time. Serves to maintain. The second subpixel SUB2 is driven by an electric field between the second pixel electrode PE2 and the common electrode.

FIG. 7 is a diagram illustrating gate pulses supplied to the first and second pixel circuits of FIG. 6, liquid crystal response characteristics of the first and second subpixels, and timings of on / off timings of light sources of the backlight unit. Referring to FIG. 7, one frame period is divided into first and second sub frame periods (1st sub frame and 2nd sub frame). One frame period (1 frame) is one frame period according to the input frame frequency, and the first and second sub frame periods (1st sub frame, 2nd sub frame) are doubled the input frame frequency by the timing controller 140. One frame period in one case.

First, the gate pulse GPn will be described. The gate pulse GPn is sequentially generated and is generated once in each of the first and second sub frame periods (1st sub frame and 2nd sub frame). The gate pulse GPn shown in FIG. 7 shows that a pulse occurs at the beginning of the first and second sub frame periods (1st sub frame, 2nd sub frame).

Second, the response characteristics LC (SUB1) and LC (SUB2) of the liquid crystals of the first and second subpixels SUB1 and SUB2 will be described. The timing controller 140 supplies R and B digital data RB to each of the source drive ICs of the data driver 120 during the first sub frame period. Accordingly, each of the source drive ICs of the data driver 120 supplies analog R data (Data (R)) converted from R digital data to odd data lines for a first sub frame period. The analog B data Data (B) converted from the B digital data is supplied to the data lines.

The timing controller 140 supplies G and B digital data GB to each of the source drive ICs of the data driver 120 during the second sub frame period. Each of the source drive ICs of the data driver 120 supplies analog G data Data (G) converted from G digital data to odd data lines for a second sub frame period, and the even data line To the analog B data (Data (B)) converted from the B digital data. Meanwhile, the B data Data (B) supplied during each of the first and second sub frame periods (1st sub frame and 2nd sub frame) by each of the source drive ICs of the data driver 120 is substantially the same data.

If the first TFT T1 of the first pixel circuit PC1 is turned on in response to the gate pulse GPn during the first sub frame period 1st sub frame, R data is stored in the first pixel electrode PE1. (Data (R)) is charged. When the second TFT T2 of the second pixel circuit PC2 is turned on in response to the gate pulse GPn, the B data Data (B) is charged in the second pixel electrode PE2.

If the first TFT T1 of the first pixel circuit PC1 is turned on in response to the gate pulse GPn during the second sub frame period (2nd sub frame), G data is stored in the first pixel electrode PE1. (Data (G)) is charged. When the second TFT T2 of the second pixel circuit PC2 is turned on in response to the gate pulse GPn, the B data Data (B) is charged in the second pixel electrode PE2.

In the liquid crystal response characteristic LC (SUB1) of the first sub-pixel SUB1, the liquid crystal transitions according to the R data Data (R) during the first sub frame period, and the second sub-frame period ( The liquid crystal transitions according to G data (Data (G)) during the 2nd sub frame. In the liquid crystal response characteristic LC (SUB2) of the second sub-pixel SUB2, the liquid crystal transitions according to the B data Data (B) during the first sub frame period, and the second sub-frame period ( The liquid crystal transitions according to the B data (Data (B)) during the 2nd sub frame. Meanwhile, since the second pixel electrode PE2 is filled with substantially the same B data Data (B) during the first and second sub frame periods (1st sub frame, 2nd sub frame), the second sub frame period (2nd) During the sub frame, the liquid crystal does not occur in the second sub pixel SUB2 as shown in FIG. 7. This is because the transition of the liquid crystal of the second sub-pixel SUB2 is completed during the first sub frame period (1st sub frame).

Third, look at the on / off timing of the light sources of the backlight unit. The light sources of the backlight unit include a red light source BL (R), a green light source BL (G), and a blue light source BL (B). The red light source BL (R) and the green light source BL (G) emit light to the first subpixel SUB1, and the blue light source BL (B) emits light to the second subpixel SUB2. Investigate. The red light source BL (R) is turned on only during the first sub frame period in which the R data Data (R) is supplied. The green light source BL (G) is turned on only during the second sub frame period to which the G data Data (G) is supplied. The blue light source BL (B) is turned on during the first and second sub frame periods 1st sub frame and 2nd sub frame to which the B data B is supplied.

The red light source BL (R) is turned on in accordance with the liquid crystal transition completion period (liquid crystal saturation period) of the liquid crystal response characteristic LC (SUB1) of the first sub-pixel SUB1 during the first sub frame period 1st sub frame. do. For example, the red light source BL (R) may be turned on at a pulse width modulation duty ratio of about 60% during the first sub frame period as shown in FIG. 7. The green light source BL (G) is turned on in accordance with the liquid crystal saturation period of the liquid crystal response characteristic LC (SUB2) of the second sub pixel SUB2 during the second sub frame period 2nd sub frame. For example, the green light source BL (G) may be turned on at a pulse width modulation duty ratio of about 60% during the second sub frame period as shown in FIG. 7. The blue light source BL (B) may be turned on at a predetermined duty ratio during the first and second sub frame periods (1st sub frame and 2nd sub frame). For example, the blue light source BL (B) is turned on in synchronization with the period in which the red light source BL (R) is turned on during the first sub frame period as shown in FIG. 7, and the second subframe is turned on. The light source BL (G) may be turned on in synchronization with the period in which the green light source BL (G) is turned on during the 2nd sub frame. In this case, the blue light source BL (B) may be turned on with a PWM width ratio of approximately 60%.

Meanwhile, since the backlight lighting period illustrated in FIG. 7 is only one embodiment, it should be noted that the present invention is not limited thereto. The backlight lighting period may vary depending on the brightness of the liquid crystal display, power consumption, and the like, and may be determined by a preliminary experiment. For example, the present invention has a higher luminance compared to the prior art due to the improvement of the aperture ratio, thereby reducing the backlight lighting period.

In sum, the first sub-pixel SUB1 displays red during the period in which the red light source BL (R) is turned on in the first sub-frame period 1st sub frame, and the second sub-frame period 2nd is displayed. Green is displayed during the period in which the green light source BL (G) is turned on in the sub frame. In addition, the second sub-pixel SUB2 displays blue during a period in which the blue light source BL (G) is turned on in the first and second sub frame periods (1st sub frame and 2nd sub frame).

FIG. 8 is a diagram illustrating data addressing of the display panel of FIG. 3 and scanning lighting of the backlight unit in detail. Referring to FIG. 8, R data (Data (R), G data (Data), and B data) of the display panel 10 during the first and second sub frame periods (1st sub frame, 2nd sub frame). The addressing of (Data (B)) is shown, and the lighting period for each block of the light sources of the backlight unit is shown.

First, addressing of R data Data (R), G data Data (G), and B data Data (B) of the display panel 10 will be described. The R data Data (R) and the B data Data (B) are addressed to the display panel 10 for a predetermined period of the first sub frame period (1st sub frame). In FIG. 7, the predetermined period is described as being about half of the first sub frame period, but it should be noted that the present invention is not limited thereto. The predetermined period may be appropriately determined within a first sub frame period through a preliminary experiment. Since the gate pulse GPn is sequentially supplied to the gate lines of the display panel 10, the R data Data (R) and the B data Data (B) are connected to the first gate line G1. From (P) to k (k is a natural number satisfying 1 ≦ n ≦ k, the number of gate lines of the display panel) is sequentially supplied to the pixels P connected to the gate line Gk. In this case, R data Data (R) is supplied to the first subpixels SUB1, and B data Data (B) is supplied to the second subpixels SUB2.

The G data Data (G) and the B data Data (B) are addressed by the display panel 10 for a predetermined period of the second sub frame period (2nd sub frame period). In FIG. 7, the predetermined period is described as being about half of the second sub frame period, but it should be noted that the present invention is not limited thereto. The predetermined period may be appropriately determined within a second sub frame period through a preliminary experiment. Since the gate pulse GPn is sequentially supplied to the gate lines of the display panel 10, the G data Data (G) and the B data Data (B) are connected to the first gate line G1. The pixels P are sequentially supplied to the pixels P connected to the k-th gate line Gk. In this case, the G data Data (G) is supplied to the first sub pixels SUB1, and the B data Data (B) is supplied to the second sub pixels SUB2.

Second, the lighting period of each block of the light sources of the backlight unit will be described. The backlight unit may be divided into first through qth blocks (q is a natural number of two or more). Since data addressing of the display panel 10 occurs sequentially from top to bottom, each of the first to q-th blocks is divided along the column direction of the display panel 10 as shown in FIG. 9. In FIG. 9, although the first to qth blocks are equally divided, it should be noted that the present invention is not limited thereto. 8 and 9, the backlight unit is divided into the first to fourth blocks BL1 to BL4, but the present disclosure is not limited thereto.

The first to fourth blocks BL1 to BL4 of the backlight unit are sequentially generated from the first block BL1 to the fourth block BL4 corresponding to the upper portion of the display panel 10. This is because the data addressing of the display panel 10 sequentially occurs from top to bottom, and thus the liquid crystal transition of pixels of the display panel 10 corresponding to the first block BL1 is completed first. In FIG. 8, the red and blue light sources BL (R) and BL (B) of the first to fourth blocks BL1 to BL4 are turned on at a PWM duty ratio of approximately 60% during the first sub frame period. The green and blue light sources BL (G) and BL (B) of the first to fourth blocks BL1 to BL4 are turned on at a PWM duty ratio of approximately 60% during the second sub frame period. It is illustrated, but not limited to this already described above.

As described above, the present invention divides a pixel into a first subpixel and a second subpixel, and sequentially displays two colors of red, green, and blue, and the second subpixel. Causes the pixel to display a color that is not displayed in the first sub pixel. As a result, since the present invention only needs to display two colors in the first sub-pixel during one frame period, since the liquid crystal response time is sufficient, gray levels of red light, green light, and blue light can be properly displayed. In addition, the present invention can reduce the aperture ratio since the black matrix and the color filter are reduced. In addition, the present invention can reduce the brightness of the light sources of the backlight unit due to the increase in the luminance due to the aperture ratio, it is possible to reduce the power consumption.

Furthermore, while the conventional field sequential driving method sequentially displays three colors in one pixel during one frame period, the present invention sequentially displays two colors in one subpixel during one frame period, and another subpixel. Display one color in. As a result, the present invention can improve the color breakup phenomenon than the conventional field sequential driving method.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display panel 30: backlight unit
110: gate driver 120: data driver
130: backlight driver 140: timing controller
150: backlight control unit 160: host system

Claims (12)

A display panel including pixels arranged in a matrix in a cell region defined by an intersection of data lines and gate lines;
A backlight unit including light sources emitting light to the display panel;
A data driver supplying data voltages to the data lines; And
A gate driver configured to supply a gate pulse to the gate lines in synchronization with the data voltage;
Each of the pixels,
A first sub pixel sequentially displaying two colors of red, green, and blue during one frame period; And
And a second sub pixel which displays a color not displayed on the first sub pixel during the one frame period. The method of claim 1,
The first sub pixel is,
Display one of the two colors during the first sub frame period of the one frame period, and display the other one of the two colors during the second sub frame period occurring after the first sub frame period. Characterized in that the liquid crystal display device. The method of claim 2,
The data driver may include:
Converts digital data of one of the two colors into an analog data voltage during the first sub frame period, and supplies the converted digital data to odd data lines connected to the first sub-pixel;
And converting digital data of one of the two colors into the analog data voltage and supplying the digital data to the odd data lines during the second sub frame period. The method of claim 3, wherein
The data driver may include:
And converting digital data of a color not displayed in the first sub-pixel during the first and second sub-frame periods into the analog data voltage and supplying the even data lines connected to the second sub-pixel. LCD display device. The method of claim 4, wherein
Supplying digital data of one of the two colors and digital data of a color not displayed on the first sub-pixel to the data driver during the first sub frame period,
And a timing controller configured to supply digital data of one of the two colors and digital data of a color not displayed on the first sub-pixel to the data driver during the second sub frame period. The method of claim 2,
Wherein the gate driver comprises:
Sequentially supplying the gate pulses to the gate lines during a predetermined period of the first sub frame period,
And sequentially supplying the gate pulses to the gate lines during a predetermined period of the second sub frame period. The method of claim 1,
The first color filter of the first sub-pixel is implemented as a color filter that passes both wavelengths of the two colors,
And the second color filter of the second subpixel is implemented as a color filter for passing a wavelength of a color not displayed on the first subpixel. The method of claim 2,
Light sources of the backlight unit,
A first light source that irradiates the first sub-pixel with light of any one of the two colors;
A second light source radiating light of one of the two colors to the first sub-pixel; And
And a third light source that irradiates the second sub-pixel with light of a color not displayed on the first sub-pixel. The method of claim 8,
The first light source is turned on only in the first sub frame period, the second light source is turned on only in the second sub frame period, and the third light source is turned on in the first and second sub frame periods. Liquid crystal display device. The method of claim 8,
And each of the first to third light sources is turned on at a predetermined PWM duty ratio. The method of claim 8,
The backlight unit is divided into first to qth blocks (q is a natural number of two or more) in a column direction of the display panel, and the first to third light sources of the first to third light sources from the first to third light sources of the first block. Liquid crystal display device characterized in that up to three light sources sequentially lit. A display panel including pixels arranged in a matrix in an area defined by an intersection of data lines and gate lines; A backlight unit including light sources emitting light to the display panel; A data driver supplying data voltages to the data lines; And a gate driver configured to supply a gate pulse to the gate lines in synchronization with the data voltage.
Sequentially displaying two colors of red, green, and blue on the first sub-pixel of each of the pixels for one frame period; And
And displaying a color not displayed on the first sub pixel during the one frame period on the second sub pixel of each of the pixels.

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