KR20130020120A - Planar type of sic mosfet - Google Patents

Planar type of sic mosfet Download PDF

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Publication number
KR20130020120A
KR20130020120A KR1020110082534A KR20110082534A KR20130020120A KR 20130020120 A KR20130020120 A KR 20130020120A KR 1020110082534 A KR1020110082534 A KR 1020110082534A KR 20110082534 A KR20110082534 A KR 20110082534A KR 20130020120 A KR20130020120 A KR 20130020120A
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KR
South Korea
Prior art keywords
channel
base layer
planar
gate
source
Prior art date
Application number
KR1020110082534A
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Korean (ko)
Inventor
홍경국
이종석
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현대자동차주식회사
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Priority to KR1020110082534A priority Critical patent/KR20130020120A/en
Publication of KR20130020120A publication Critical patent/KR20130020120A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/435—Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

PURPOSE: A planar silicon carbide MOSFET is provided to reduce manufacturing costs by improving current density. CONSTITUTION: A planar silicon carbide MOSFET includes a planar gate. An n+ source(11) and a p-base layer(12) form a pn junction under source metal. A trough type receiving groove(13) is concavely formed on the surface of the p-base layer and increases the width of a channel(14). A channel, a gate oxide layer, and a gate electrode(16) are successively laminated on the receiving groove and the surface of the p-base layer. The trough type receiving groove is formed with a dry etching process. [Reference numerals] (10,CC) Source metal; (11,BB) N+ source; (12) P-base layer; (14,AA) Channel; (16) Gate; (3) N-epi layer

Description

Planar Silicon Carbide MOSFET {Planar type of SiC MOSFET}

The present invention relates to a planar silicon carbide MOSFET, and more particularly to a planar silicon carbide MOSFET which can reduce the cost by improving the current density.

Recently, the demand for power semiconductor devices having high breakdown voltage, high current density, and high speed switching characteristics is increasing according to the trend of larger and larger applications.

In addition, a characteristic that can withstand the reverse high voltage of the pn junction applied to both ends of the power semiconductor element at the time of the off state or the switch off, that is, a high breakdown voltage characteristic is basically required.

Since silicon carbide (SiC) power devices have better characteristics than conventional silicon devices, they are currently being actively researched as the only devices capable of satisfying characteristics such as high breakdown voltage and high current density. It is in the early stages of entry.

However, due to the problem of expensive silicon carbide wafer costs and wafer defects, the market for silicon carbide power devices is not activated.

In order to overcome this problem, a trench gate structure MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that can reduce the device cost by maximizing the current density has been actively studied.

1 is a cross-sectional view showing a conventional trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

As shown, a conventional trench MOSFET includes a drain electrode 1, an n + substrate 2 positioned on the drain electrode 1, an n− epilayer 3 formed on the n + substrate 2, and And penetrate the p base layer 4 formed on the n− epi layer 3, the n + source region 5 formed on the p base layer 4, the source region 5 and the base layer 4. To fill a portion of the epitaxial layer 3 to a predetermined depth, the gate oxide film 7 formed on the inner side of the trench 6, and the gate oxide film 7 of the trench 6. A polysilicon gate 8, an oxide film 9 formed on the source region 5 and the polysilicon gate 8, and a source electrode connecting the plurality of source regions 5 and the p base layer 4. 10) including.

As described above, the MOSFET having the trench gate structure has an advantage in that a large current can be energized per unit area by increasing the current density.

However, a breakdown phenomenon occurs in which the oxide film 7 is destroyed due to an electric field crowding effect in which the breakdown voltage is concentrated in the oxide film 7 at the lower end of the trench gate. Because of the very low breakdown voltage, the breakdown voltage is lower than that of a planar gate MOSFET.

As a result, when mass-producing SiC power devices, a planar gate structure having a higher breakdown voltage than a trench gate structure having a low breakdown voltage is progressing.

2 is a cross-sectional view schematically showing a MOSFET (MOSFET) of a conventional planar gate structure.

As shown in FIG. 2, a MOSFET having a planar gate structure includes a p base layer 20, a channel 1, a gate oxide film 22, and a gate electrode 23 formed in a plane stacked on the p base layer 20. It is composed.

At this time, the drain current flows along the channel, and the magnitude of the drain current I D (or channel current) is proportional to the channel width Zp (= 3z).

However, in the MOSFET device having the planar gate structure, since the channel is formed in the horizontal direction, the channel density per unit device area is lower than that of the trench gate structure, so that the amount of current that can flow through the channel 21 is relatively small.

Therefore, although the MOSFET device of the planar gate structure cannot minimize the device area due to the low current density and can not reduce the cost, and thus has excellent characteristics compared to silicon, it is actually a large current such as an eco-friendly vehicle when producing SiC power devices. There is a problem that is not applicable for the purpose.

The present invention has been invented to solve the above problems, the planar silicon carbide MOSFET can reduce the cost by improving the current density by increasing the width of the existing channel by applying the furrow channel structure in the conventional planar MOSFET The purpose is to provide.

In order to achieve the above object, the planar silicon carbide MOSFET according to the present invention has a planar gate and forms a pn junction through an n + source and a p base layer under the source metal,

Grooved accommodating grooves formed concave at intervals on the surface of the p base layer to increase the width of the channel; It characterized in that it comprises a channel, a gate oxide film and a gate electrode sequentially stacked in the receiving groove.

In particular, the furrow-shaped receiving groove is characterized in that formed by dry etching.

The depth of the channel is characterized in that it is formed smaller than the n + source junction depth.

The advantages of the planar silicon carbide MOSFET according to the present invention are as follows.

1. The increase in channel width that can be formed varies depending on the depth, width, and number of grooves of the channel, but when the depth and width are the same, the channel width is increased by about 2/3 times that of the conventional planar gate structure. 2/3 times the current increase effect.

This improves the current density of 2/3 times when the same area of SiC power device is applied, so that the area of the device can be reduced to 2/3 to obtain the same current, thereby greatly reducing the cost.

1 is a cross-sectional view showing a MOSFET of a trench gate structure according to the prior art
2 is a schematic diagram showing a MOSFET of a planar gate structure according to the prior art
3 is a plan view showing a MOSFET of a planar gate structure according to an embodiment of the present invention;
4 is a cross-sectional view AA in FIG.
5 is a cross-sectional view taken along line BB of FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

3 is a plan view illustrating a MOSFET having a planar gate structure according to an exemplary embodiment of the present invention, FIG. 4 is a cross-sectional view taken along line A-A of FIG. 3, and FIG. 5 is a cross-sectional view taken along line B-B of FIG. 3.

The present invention is a semiconductor device that can improve the current density by applying a furrow gate structure in the MOSFET having a conventional planar gate structure longer than the width of the channel 14 of the conventional planar gate structure It is about.

According to the present invention, the current density can be improved by increasing the width Zp of the channel 14 without increasing the area of the unit device.

In the trench gate structure according to the present invention, the n + source 11 and the p base layer 12 form a pn junction under the source metal 10, and the p base layer 12 is dried on the surface of the p base layer 12. A silicon carbide MOSFET power device in which a gate channel 14, a gate oxide layer 15, and a gate electrode 16 are sequentially stacked on an etched groove receiving groove 13.

In other words, the MOSFET having the trench structure includes a p base layer 12, a channel 14 stacked on the p base layer 12, a gate oxide film 15, and a gate electrode 16.

The MOSFET of the furrow-type gate structure has a furrow type receiving groove 13 formed concave in the p base layer 12, and the receiving groove 13 is spaced along the width direction of the channel 14. It is formed.

And, the receiving groove 13 according to the embodiment has a rectangular cross-sectional shape, the length is long and the width is made of a furrow narrower than the length.

At this time, the surface of the p base layer 12 except for the receiving groove 13 is formed in a plane.

The receiving groove 13 is formed in a rectangular cross-sectional shape by a bottom portion formed horizontally at a position lower than the remaining plane of the p base layer 12 to a predetermined depth and side portions formed at both ends of the bottom portion, and formed directly upward, and a p base layer. It is formed by dry etching on the surface of (12).

The channel 14, the gate oxide film 15, and the gate electrode 16 are formed to have a predetermined thickness over the surface of the remaining p base layer 12 including the receiving groove 13.

According to the present invention, the grooved channel 14 may be applied to an existing planar gate structure due to the grooved groove 13 formed on the surface of the p base layer 12.

The operation and effects of the present invention by such a configuration will be described.

The present invention forms a groove-type accommodating groove 13 in a planar p base layer 12 by dry etching, and the channel 14 and the gate oxide film are formed along the surface of the p base layer 12 having the accommodating groove 13. By stacking the 15 and the gate electrode 16, the furrow-shaped channel 14 may be applied to increase the width of the channel 14 without increasing the area of the unit element.

The width of the channel 14 is the length of both the top plane (Z1 + Z2) of the receiving groove 13 of the horizontal plane and the bottom plane (Z3) of the receiving groove 13, and the side portion of the receiving groove 13 of the vertical plane ( 2t).

The furrow channel 14 according to the present invention has a width 2t of the depth of the receiving groove 13 (furrow) in addition to the width Z1 + Z2 + Z3 of the existing planar channel 14. Further, the channel current (drain current) can be increased by increasing the contact area between the channel 14 and the gate and the width of the channel 14 through the oxide film 15.

The number of formations of the furrows n depends on the process design rules.

The depth t of the furrow is preferably smaller than the n + source 11 junction depth d j . This is because when the depth of the furrow becomes deeper than the junction depth of the n + source 11, the electrons of the n + source 11 do not pass through the channel 14 at the bottom of the furrow.

In other words, the trench depth t of the p base layer 12 must be smaller than the n + junction depth d j so that electrons in the n + source 11 region can flow through the channel 14 of the trench structure.

If one furrow is present, the channel width becomes larger by 2 × t.

In addition, when there are n furrows in the furrow channel 14, channel widths of (2 x t) x n are additionally generated to increase the channel current by increasing the channel width.

Therefore, according to the present invention, although the degree of increase in the width of the channel that can be formed varies depending on the depth, width, and number of grooves of the channel 14, when the depth and width are the same, about 2/3 times that of the conventional planar gate structure. The channel width is increased, resulting in a 2/3 times increase in current.

This improves the current density of 2/3 times when the same area of SiC power device is applied, so that the area of the device can be reduced to 2/3 to obtain the same current, thereby greatly reducing the cost.

10: source metal 11: n + source
12: p base layer 13: receiving groove
14 channel 15 gate oxide film
16: gate electrode

Claims (3)

In a planar silicon carbide MOSFET having a planar gate and an n + source 11 and a p base layer 12 under the source metal 10 making a pn junction,
Grooved accommodating grooves 13 are formed concave at intervals on the surface of the p base layer 12 to increase the width of the channel 14;
A channel 14, a gate oxide film 15, and a gate electrode 16 sequentially stacked on surfaces of the receiving groove 13 and the p base layer 12;
Planar silicon carbide MOSFET characterized in that comprises a.
The method according to claim 1,
The furrow-shaped receiving groove 13 is a flat silicon carbide MOSFET, characterized in that formed by dry etching.
The method according to claim 1,
Planar silicon carbide MOSFET, characterized in that the depth of the channel (14) is formed smaller than the n + source (11) junction depth.
KR1020110082534A 2011-08-19 2011-08-19 Planar type of sic mosfet KR20130020120A (en)

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KR1020110082534A KR20130020120A (en) 2011-08-19 2011-08-19 Planar type of sic mosfet

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KR1020110082534A KR20130020120A (en) 2011-08-19 2011-08-19 Planar type of sic mosfet

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997624B2 (en) 2016-07-05 2018-06-12 Hyundai Motor Company Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997624B2 (en) 2016-07-05 2018-06-12 Hyundai Motor Company Semiconductor device and method of manufacturing the same

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