KR20130018487A - Memory device for implementing hidden timing parameters management - Google Patents

Abstract

PURPOSE: A memory device for managing hidden timing parameters is provided to secure timing parameter margin by hiding the timing parameters from a memory controller. CONSTITUTION: A memory device includes a plurality of banks in which a plurality of memory cells are arranged. Each bank includes two or more sub banks. In a sub bank interleave method to continuously operate the sub banks in one bank one by one, a continuous operation between sub banks is set at low active-to-low active time interval between different banks.

Description

Memory device for implementing hidden timing parameters management

The present invention relates to a memory device, and more particularly, to a memory device for managing hidden timing parameters that can hide timing parameters from a memory controller.

The memory device is operated in accordance with the provision of timing parameters such as a time of writing data into a memory cell, a wordline activation time, a precharge time, and the like. Due to the limitation of process shrink in semiconductor manufacturing, timing parameters are getting longer. This causes a decrease in semiconductor yield. As semiconductor processes become more sophisticated, semiconductor yield declines are expected to become more severe. Accordingly, there is a need for a method capable of managing timing parameters systemically.

An object of the present invention is to provide a memory device that secures timing parameter margin by hiding timing parameters to a memory controller.

According to an aspect of an exemplary embodiment, a memory device includes a plurality of banks in which a plurality of memory cells are arranged, each bank including at least two or more subbanks, and the sub banks sequentially operating one subbank in one bank. In the bank interleave scheme, the continuous operation between subbanks is set to be at low active-to-low active time (tRRD) intervals between the different banks.

According to embodiments of the present invention, the subbanks may be selectively accessed using one or more bits of the row address signals addressing the memory cells.

According to embodiments of the present invention, the data write time tWR to the memory cell in the continuous data write operation between the sub banks may be set longer than the data write time to the memory cell in the continuous data write operation between the banks. Can be. The data write time tWR into the memory cells may not be included in an interval time interval of successive data write operations between subbanks.

According to embodiments of the present invention, the bit line precharge time tRP of a memory cell in successive data write operations between subbanks is equal to the bitline precharge of a memory cell in successive data write operations between banks. It can be set longer than the idle time. The bit line precharge time tRP of the memory cell may not be included in an interval time interval of successive data write operations between subbanks.

According to embodiments of the present invention, the time tRCD between the row active command and the column active command in the continuous data write operation between the sub banks is equal to the row active command and the column active in the continuous data write operation between the banks. It can be set longer than the time between commands. The bit line precharge time tRP of the memory cell may not be included in an interval time interval of successive data write operations between subbanks.

According to embodiments of the present invention, the sub banks may be arranged in a direction in which word lines of memory cells are arranged. The sub banks may be arranged in a direction in which bit lines of the memory cells are arranged. The sub banks may be connected to independent data line sense blocks and data input / output lines.

A memory device according to another aspect of the present invention includes a plurality of banks in which a plurality of memory cells are arranged, each bank including a plurality of sub arrays, dividing the sub arrays into at least two sub array groups, Observe timing restrictions between successive instruction combinations applied to the sub arrays included in each sub array group.

According to embodiments of the present invention, sub-array groups may be selectively accessed using one or more bits of row address signals addressing memory cells.

According to embodiments of the present invention, when one sub array in a sub array group is activated, sub arrays adjacent to the activated sub array may be deactivated due to a keep away zone.

According to embodiments of the present invention, when a sub array belonging to a keep away zone belongs to another sub array group, the sub array belonging to another sub array group may be deactivated.

According to embodiments of the present disclosure, when a defective cell is generated in a sub array in a sub array group, the memory device may replace the defective cell with redundancy cells of the corresponding sub array or another sub array in the corresponding sub array group. .

According to embodiments of the present disclosure, the memory device may further include a storage configured to store the size of the sub array group representing the number of sub arrays included in each sub array group. The storage unit may be a nonvolatile device composed of a fuse or an antifuse.

According to embodiments of the present invention, each of the sub array groups may be connected to data line sense blocks and data input / output lines that are independent of each other.

According to embodiments of the present invention, the timing constraints may be set to the time when the column select line of the sub array operating on the previous command is turned off in the sub arrays to which successive commands are applied.

According to another aspect of the present invention, a memory system includes a plurality of banks in which a plurality of memory cells are arranged, and each of the banks includes a memory device including at least two subbanks, and a control unit for controlling the memory device. do. In the subbank interleaving method of continuously operating subbanks in one bank one by one, the controller performs a continuous operation between the subbanks at low active-to-low active time (tRRD) intervals between the different banks. To control.

According to embodiments of the present invention, the controller is disposed in a memory module in which the memory device is mounted, and transmits a command signal and an address signal received from the memory controller to the memory device, wherein the command signal and the address signal are one of the memory device. It may be a buffer chip that monitors whether subbanks in the bank are accessed.

According to embodiments of the present invention, the controller converts the command signal and the address signal of the memory device according to a read or write command requested from the host, and the command signal and the address signal access subbanks in one bank of the memory device. May be a memory controller that monitors whether

According to embodiments of the present invention, the controller may not observe the data write time (tWR) parameter definition to the memory cell in the continuous data write operation between the subbanks.

According to embodiments of the present invention, the control unit may not comply with the bit line precharge time (tRP) parameter definition of the memory cell in successive data write operations between subbanks.

According to another aspect of the present invention, a memory system includes a plurality of banks in which a plurality of memory cells are arranged, each bank including a plurality of sub arrays, and the sub arrays are divided into at least two sub array groups. And a controller that controls the memory device and observes timing restrictions between successive instruction combinations applied to the sub arrays included in each sub array group of the memory device.

According to embodiments of the present disclosure, the memory device may further include a storage configured to store the size of the sub array group representing the number of sub arrays included in each sub array group.

According to embodiments of the present invention, the controller may further include a storage unit for storing the size of the sub array group indicating the number of sub arrays included in each sub array group.

According to embodiments of the present disclosure, the controller may calculate row address bits for distinguishing a row address that is a boundary between each server array and a server array group by using the size of the sub array group of the memory device.

According to embodiments of the present disclosure, when one sub array in the sub array group of the memory device is activated, the controller may deactivate adjacent sub arrays belonging to the keep away zone of the activated sub array.

According to embodiments of the present disclosure, if a sub array belonging to a keep away zone belongs to another sub array group, the controller may deactivate a sub array belonging to another sub array group.

According to embodiments of the present invention, when a defective cell is generated in a subarray in a subarray group of a memory device, the defective cell may be replaced with redundancy cells of the corresponding subarray or another subarray in the corresponding subarray group. .

In the memory device of the present invention described above, in the sub-bank interleaving method, as the continuous data write operation is shortened at the tRRD time interval, the memory cell data write time tWR can be long during each data write operation. Thereby, sufficient time for data writing can be secured. This can complement the tWR parameter, which is prolonged as the semiconductor process becomes smaller.

Also, the memory cell data write time tWR is not included in the interval time interval of successive data write operations of the sub banks. The tWR time does not require the memory controller to comply with the timing parameter specification in the timing of successive data write operations of the subbanks. In the sub-bank interleaving scheme, the memory cell data writing time tWR may be hidden without knowing the memory controller. The hidden memory cell data write time tWR does not affect data processing time and data throughput.

1 is a block diagram illustrating a first example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.
FIG. 2 is a circuit diagram of the bank shown in FIG. 1.
3A and 3D are diagrams illustrating operation timings of the memory device of FIG. 1.
4 is a block diagram illustrating a second example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.
FIG. 5 is a block diagram illustrating a third example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.
FIG. 6 is a diagram for specifically describing an architecture of the first bank of FIG. 5.
FIG. 7 is a diagram illustrating timing constraints for successive commands of different subarrays of FIG. 6.
FIG. 8 is a block diagram illustrating a first example of a memory system that may be used to implement one or more hidden timing parameter management method embodiments described herein.
FIG. 9 is a block diagram illustrating a second example of a memory system that may be used to implement one or more hidden timing parameter management method embodiments described herein.
FIG. 10 is a diagram illustrating timing parameter definitions between the memory controller and the memory device of FIG. 9.
FIG. 11 is a diagram illustrating a semiconductor memory device implementing one or more hidden timing parameter management method embodiments described herein.
FIG. 12 is a diagram illustrating an implementation example of a memory system to which the semiconductor memory device of FIG. 11 is applied.
FIG. 13 is a block diagram illustrating a computing system having a memory system according to an example embodiment. Referring to FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

In semiconductor memory devices, timing parameters include low cycle time (tRC), ras-to-cas delay (tRCD), write recovery time (tWR), and low-free. There are core-timing parameters such as charge time tRP, low active-to-low active delay (tRRD), and the like.

The tRC parameter represents the time between the active command and the next active command. The tRCD parameter represents the time between the application of the / RAS signal and the application of the / CAS signal, and the time between the low active command and the column active command. The tWR parameter indicates the time to write data to the memory cell after word line enable. The tRP parameter represents the time to precharge the bit line to prepare for the next active command after the tWR time. The tRRD parameter represents the time between the low active command and the low active command, and means the low active-to-low active time between different banks.

The longer the tWR time, the longer the data write time can be in the memory cell. Accordingly, the memory device can secure a sufficient time margin for writing data.

Meanwhile, with the miniaturization of semiconductor processes, semiconductor yields are decreasing due to the problem that timing parameters become longer. Of the longer timing parameters, tWR is a major factor in lowering semiconductor yield.

If the long tWR parameter can be hidden as the semiconductor process becomes smaller, the semiconductor process will be easier and yield can be increased. Accordingly, the semiconductor manufacturing cost of the memory device can be lowered. A memory system including such a memory device may be supplied with a low-cost memory device having a high degree of integration even when the process scaling limit is reached.

1 is a block diagram illustrating a first example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.

Referring to FIG. 1, the memory device 100 includes a plurality of banks A BANK-H BANK 110, 120, 130, 140, 150, 160, 170, and 180 in which a plurality of memory cells are arranged in rows and columns. It includes. Each of the plurality of banks 110 to 180 may have a plurality of word lines WLs, a plurality of bit lines BLs, and between the word lines WLs and bit lines BLs, as shown in FIG. 2. It includes a plurality of memory cells (MCs) disposed at the intersection of. Each memory cell MC has a DRAM cell structure. Word lines WLs to which memory cells MCs are connected are defined as rows of banks 110 to 180, and bit lines BLs to which memory cells MCs are connected are banks 110 to 180. Can be defined as columns.

In this embodiment, an example in which the memory device 100 is composed of eight banks A BANK to H BANK will be described. The memory device 100 may include various numbers of banks in addition to the eight banks A BANK to H BANK.

Each of the banks 110 to 180 may include a first sub bank 111, a second sub bank 112, a first row decoder 113, a second row decoder 114, and a first column decoder 115. And a second column decoder 116. The first row decoder 113 and the second row decoder 114 may receive bank addresses BAs and row addresses RAs. The first column decoder 115 and the second column decoder 116 may receive column addresses (not shown). One bank of the plurality of banks 110 to 180 may be selected according to the bank addresses BAs, and memory cells in the selected bank may be addressed according to the row addresses RAs and column addresses (not shown). have.

The A bank 110 may be divided into a first sub bank 111 and a second sub bank 112. It can be seen that the first sub bank 111 and the second sub bank 112 are arranged in the direction in which the word lines WLs of the memory cells MCs are arranged, that is, in the row direction. The first sub bank 111 may be connected to the first row decoder 113 and the first column decoder 115. Memory cells of the first sub bank 111 may be addressed by the first row decoder 113 and the first column decoder 115. The second sub bank 112 may be connected to the second row decoder 114 and the second column decoder 116. Memory cells of the second sub bank 112 may be addressed by the second row decoder 114 and the second column decoder 116.

The first sub bank 111 and the second sub bank 112 are selected by a bit of any one of the row address signals RAs provided to the first row decoder 113 and the second row decoder 114. Can be. For example, the first sub bank 111 or the second sub bank 112 may be selected by the MSB signal RA _MSB of the row address signal. The first sub bank 111 may be selected by the / RA _MSB signal, and the second sub bank 112 may be selected by the RA _MSB .

The first sub bank 111 and the second sub bank 112 are connected to the respective data line sense amplifier blocks 117 and 118, and are independent of the data input / output lines I / O _AS1 and I / O _AS2 . Can be connected. The data read from the first sub bank 111 may be output through the first data line sense amplifier block 117 and the first data input / output lines I / O _AS1 . The data read from the second sub bank 112 may be output through the second data line sense amplifier 118 and the second data input / output lines I / O _AS2 .

Each of the B banks to the H banks 120 to 180 may be divided into a first sub bank and a second sub bank, similarly to the A bank 110. The first sub bank of each bank may be connected to a first row decoder, a first column decoder, a first data line sense amplifier block, and first data input / output lines. The second sub bank and each of the second sub banks may be connected to a second row decoder, a second column decoder, a second data line sense amplifier block, and second data input / output lines. In the present exemplary embodiment, an example in which the A banks to the H banks 110 to 180 are formed of two sub banks is described. However, the sub banks 110 to 180 may be configured to have various numbers of sub banks. Various numbers of subbanks may be connected to independent data line sense amplifier blocks and data input / output lines.

3A and 3D are diagrams illustrating operation timings of the memory device 100 of FIG. 1. 3A is a diagram illustrating a bank interleaving scheme, and FIGS. 3B to 3D are diagrams illustrating a subbank interleaving scheme.

Referring to FIG. 3A, the bank interleaving scheme shows timings for interleaving A banks to H banks 110-180, that is, one by one in succession. For example, the bank interleaving method may be performed by any one bank operation among the remaining banks 120-180 other than the A bank 110 after the operation of the A bank 110. Alternatively, the bank interleaving method may be performed by the operation of the A bank 110 after the operation of the A bank 110. The bank interleaving scheme of FIG. 3A is described with continuous A bank 110 operation.

The first active command ACT0 for the A bank 110 is applied, and the first word line WL0 is enabled after the tRCD time. The first word line WL0 is connected to selected memory cells in the A bank 110. A data write operation is performed to selected memory cells connected to the first word line WL0. The memory cell data write operation of the A bank 110 is performed for tWR time. After the tWR time, the bit lines of the memory cells in the A bank are precharged by the first precharge command PRE0. Bit line precharge operation of the A bank 110 is performed during the tRP time. It can be seen that the first write operation for the A bank 110 is performed for tRCD + tWR + tRP time.

Thereafter, the second active command ACT1 for the A bank 110 is applied, and the second word line WL1 is enabled after the tRCD time. The second word line WL1 is connected to selected memory cells in the A bank 110. A data write operation is performed to selected memory cells connected to the second word line WL1. The memory cell data write operation of the A bank 110 is performed for tWR time. After the tWR time, the bit lines of the memory cells in the A bank 110 are precharged by the second precharge command PRE1. Bit line precharge operation of the A bank 110 is performed during the tRP time. It can be seen that the second write operation for the A bank 110 is performed for tRCD + tWR + tRP time.

In the bank interleaving scheme, the first write operation and the second write operation for the A bank 110 are performed at tRC time intervals, which are tRCD + tWR + tRP time intervals. The tRC time is for example at least 50 ns.

Referring to FIG. 3B, the sub-bank interleaving scheme interleaves the sub-banks 111 and 112 in one of the A banks to the H banks 110 to 180 to interleave, that is, timing one by one in succession. Shows. The subbank interleaving scheme is described, for example, as an operation for the subbanks 111 and 112 of the A bank 110. Assume that the first active command ACT0 is an active command for the first sub bank 111 and the second active command ACT1 is an active command for the second sub bank 112.

The first active command ACT0 is applied to the first sub bank 111 and the first word line WL0 is enabled after the tRCD time. The first word line WL0 is connected to selected memory cells in the first sub bank 111. A data write operation is performed to selected memory cells connected to the first word line WL0. The memory cell data write operation of the first sub bank 111 is performed for tWR 'time. After the tWR 'time, the bit lines of the memory cells in the first sub bank 111 are precharged by the first precharge command PRE0. The bit line free-charge operation of the first sub-bank 111 occurs during the tRP time. After that, the first active command ACT0 for the first sub bank 111 is applied again, the first word line WL0 is enabled, a memory cell data write operation is performed, and a bit line precharge is performed. Operation can be made.

The second active command ACT1 for the second sub bank 112 is applied, and the second word line WL1 is enabled after the tRCD time. The second word line WL1 is connected to selected memory cells in the second sub bank 112. A data write operation is performed to selected memory cells connected to the second word line WL1. The memory cell data write operation of the second sub bank 112 is performed for tWR 'time. After the tWR 'time, the bit lines of the memory cells in the second sub bank 112 are precharged by the second precharge command PRE1. The bit line precharge operation of the second sub bank 112 is performed during the tRP time. Thereafter, the second active command ACT1 for the second sub bank 112 is applied again, the second word line WL1 is enabled, a memory cell data write operation is performed, and a bit line precharge is performed. Operation can be made.

In the sub-bank interleaving scheme, the first active command ACT0 for the first sub bank 111 and the second active command ACT1 for the second sub bank 112 are row active-to-between different banks. It may be applied at a tRRD time interval, which is a low active time. The tRRD time is, for example, at least about 6 ns.

In the bank interleaving method, since two word lines cannot be enabled in one A bank 110, the continuous data write operation for the A bank 110 can only write data at a tRC time interval. In contrast, in the sub-bank interleaving method, the data write operation for the sub-banks 111 and 112 in the A bank 110 can write data at tRRD time intervals. The tRRD time is considerably shorter than the tRC time. Accordingly, in the sub-bank interleaving scheme, as the continuous data write operation is shortened at the tRRD time interval, the memory cell data write time tWR 'can be long during each data write operation.

In the sub-bank interleaving method, the memory cell data writing time tWR 'is long, and thus the time required for data writing can be sufficiently secured. This can complement the tWR parameter, which is prolonged as the semiconductor process becomes smaller.

Also, the memory cell data write time tWR 'is not included in the interval time interval of successive data write operations of the subbanks. The tWR 'time is not required for the host, e. That is, in the sub-bank interleaving scheme, the memory cell data writing time tWR 'may be hidden without knowing the memory controller. The hidden memory cell data write time tWR 'does not affect the data processing time and the data throughput.

In this embodiment, an example of sufficiently securing the tWR 'time in the sub-bank interleaving method has been described. The sub-bank interleaving scheme can secure the tRCD or tRP time sufficiently long instead of the tWR 'time.

FIG. 3C illustrates a case in which the tRCD 'time is secured during a continuous data write operation of sub banks, and FIG. 3D illustrates a case in which the tRP' time is secured. The tRCD 'time and the tRP' time are not included in the interval time interval of successive data write operations of the subbanks. The tRCD 'time and the tRP' time can be hidden without knowing the memory controller in the timing of successive data write operations of the subbanks. Hidden tRCD 'or tRP' time does not affect data processing time and data throughput.

4 is a block diagram illustrating a second example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.

Referring to FIG. 4, the memory device 400 is different from the memory device 100 of FIG. 1 in that the A bank 110 ^I is composed of four subbanks. The A bank 110 ^I may be divided into first to fourth sub banks 411, 412, 413, and 414.

The first sub bank 411 may be connected to the first row decoder 421, the first column decoder 431, the first data line sense amplifier block 441, and the first data input / output lines I / O _AS1 . have. Memory cells of the first sub bank 411 may be addressed by the first row decoder 421 and the first column decoder 431. Data read from the first sub bank 411 may be output through the first data line sense amplifier block 441 and the first data input / output lines I / O _AS1 .

The second sub bank 412 may be connected to the second row decoder 422, the second column decoder 432, the second data line sense amplifier block 442, and the second data input / output lines I / O _AS2 . have. Memory cells of the second sub bank 412 may be addressed by the second row decoder 422 and the second column decoder 432. Data read from the second sub bank 412 may be output through the second data line sense amplifier block 442 and the second data input / output lines I / O _AS2 .

The third sub bank 413 may be connected to the third row decoder 423, the third column decoder 433, the third data line sense amplifier block 443, and the third data input / output lines I / O _AS3 . have. The memory cells of the third sub-bank 413 may be addressed by the third row decoder 423 and the third column decoder 433. [ The data read from the third sub bank 413 may be output through the third data line sense amplifier block 443 and the third data input / output lines I / O _AS3 .

The fourth sub bank 414 may be connected to the fourth row decoder 424, the fourth column decoder 434, the fourth data line sense amplifier block 444, and the fourth data input / output lines I / O _AS4 . have. Memory cells of the fourth sub bank 414 may be addressed by the fourth row decoder 424 and the fourth column decoder 434. Data read from the fourth sub bank 414 may be output through the fourth data line sense amplifier block 444 and the fourth data input / output lines I / O _AS4 .

The first to fourth subbanks 411, 412, 413, and 114 may be selected by two bits of the row address signals RAs provided to the first to fourth row decoders 421 to 424. have. For example, any one of the first to fourth subbanks 411, 412, 413, 114 is selected by the MSB signal RA _MSB and the MSB-1 signal RA _{MSB -1} of the row address signal. Can be.

Each of the B banks to the H banks 120 to 180 of FIG. 1 is also divided into four subbanks, similarly to the A bank 110 ^I of FIG. 4, and the first to fourth subbanks are the first to the fourth banks. 4 can be selected by the row address signal provided to the row decoder MSB signal (RA _MSB) and the MSB-1 signal (RA _{MSB -1).} The first sub bank of each bank may be connected to a first row decoder, a first column decoder, a first data line sense amplifier block, and first data input / output lines. The second sub bank of each bank may be connected to a second row decoder, a second column decoder, a second data line sense amplifier block, and second data input / output lines. The third subbank of each bank may be connected to a third row decoder, a third column decoder, a third data line sense amplifier block, and third data input / output lines. The fourth sub bank of each bank may be connected to a fourth row decoder, a fourth column decoder, a fourth data line sense amplifier block, and fourth data input / output lines.

In the present exemplary embodiment, an example in which the memory device 400 includes eight banks A BANK to H BANK and the A banks to H banks are composed of four subbanks is described. It may consist of various numbers of subbanks. Various numbers of subbanks may be connected to independent data line sense amplifier blocks and data input / output lines.

FIG. 5 is a block diagram illustrating a third example of a memory device that may be used to implement one or more hidden timing parameter management method embodiments described herein.

Referring to FIG. 5, the memory device 500 includes a plurality of memory banks BANK0 to BANK7 having a stack bank architecture. The memory banks BANK0-BANK7 may be separately arranged for noise dispersion. The memory banks BANK0 to BANK7 may be divided into quadrants 50A, 50B, 50C, and 50D based on pads arranged in the center of the memory device 500.

The first bank BANK0 may be divided into the first quadrant 50A and the fourth quadrant 50D, and the second bank BANK1 may be divided into the second quadrant 50B and the third quadrant 50C. have. The remaining even number banks BANK2, BANK4, and BANK6 may be divided into the first quadrant 50A and the fourth quadrant 50D. The remaining odd number banks BANK3, BANK5, and BANK7 may be divided into the second quadrant 50B and the third quadrant 50C.

The first bank BANK0 may include a first memory cell array block 510a disposed in the first quadrant 50A and a second memory cell array block 510b disposed in the fourth quadrant 50D. The second bank BANK1 may include a first memory cell array block 520a disposed in the second quadrant 50B and a second memory cell array block 520b disposed in the third quadrant 50C. The third bank BANK2 may include a first memory cell array block 530a disposed in the first quadrant 50A and a second memory cell array block 530b disposed in the fourth quadrant 50D.

Each of the remaining even banks BANK4 and BANK6 may also include a first memory cell array block disposed in the first quadrant 50A and a second memory cell array block disposed in the fourth quadrant 50D. Each of the remaining odd number banks BANK3, BANK5, and BANK7 may also include a first memory cell array block disposed in the second quadrant 50B and a second memory cell array block disposed in the third quadrant 50C. .

Referring to the first quadrant 50A of the memory device 500, the first memory cell array block 510a of the first bank BANK0 and the first memory cell array block 530a of the third bank BANK2 are stacked. Stack bank structure. The first memory cell array block 510a of the first bank BANK0 may be divided into two array groups 511 and 512. The first memory cell array block 530a of the third bank BANK2 may also be divided into two sub array groups 531 and 532. The sub array groups 511 and 512 of the first bank BANK0 and the sub array groups 531 and 532 of the third bank BANK2 are arranged in a direction in which bit lines of memory cells are arranged, that is, in a column direction. You can see that.

The first memory cell array blocks 510a and 530a of the first bank BANK0 and the third bank BANK3 are divided by a row decoder 513 in between. The divided first memory cell array blocks 510a and 530a may be connected to the row decoder 513 and the first and second column decoders 515 and 516. The memory cells of the divided first memory cell array blocks 510a and 530a may be addressed by the row decoder 513 and the first and second column decoders 515 and 516.

The row decoder 513 may receive the bank addresses BAs and the row addresses RAs. The first and second column decoders 515 and 516 may receive column addresses (not shown). One bank of the first and third banks BANK0 and BANK3 is selected according to the bank addresses BAs, and a sub memory cell in the bank selected according to the row addresses RAs and column addresses (not shown). Memory cells of the array blocks 511, 512, 531, and 532 may be addressed.

The first sub array group 511 and the second sub array group 512 of the first bank BANK0 may be selected by a bit of any one of the row address signals RAs provided to the row decoder 513. have. For example, the first sub array group 511 or the second sub array group 512 may be selected by the MSB signal RA _MSB of the row address signal. The first sub array group 511 may be selected by the / RA _MSB signal, and the second sub array group 512 may be selected by the RA _MSB .

Similar to the first and third banks BANK0 and BANK2, the fifth and seventh banks BANK4 and BANK6 are also stacked with memory cell array blocks divided into two sub-array groups. Sub-array groups of the fifth and seventh banks BANK4 and BANK6 may be selected by the MSB signal RA _MSB of the row address signal provided to the row decoder 513.

Memory cell array blocks in which the memory banks BANK0 to BANK7 of the other quadrants 50B, 50C and 50D are divided into two subarray groups are stacked. Sub-array groups in the memory banks BANK0-BANK7 may be selected by the MSB signal RA _MSB of the row address signal provided to the row decoder disposed in the corresponding quadrants 50B, 50C, and 50D.

In the present exemplary embodiment, an example in which the memory banks BANK0 to BANK7 are configured as two sub array groups is described. However, the memory banks BANK0 to BANK7 may be configured as various sub array groups other than two.

FIG. 6 is a diagram for specifically describing an architecture of the first bank of FIG. 5.

Referring to FIG. 6, the first sub array group 511 and the second sub array group 512 may include a plurality of sub arrays 611-618. The sub arrays 611-618 in the first sub array group 511 may be designed to share data input / output lines (not shown) and a data line sense amplifier block (not shown). Similarly, the sub arrays in the second sub array group 512 may be designed to share the data input / output lines (not shown) and the data line sense amplifier block (not shown).

The sub array 614 in the first sub array group 511 may be connected to bit line sense amplifier blocks 621 and 622 disposed above and below the sub array 614. The bit line sense amplifier block 621 may be connected to the sub array 613. The bit line sense amplifier block 621 may be shared by the sub arrays 613 and 614. The bit line sense amplifier block 622 may be connected to the sub array 615. The bit line sense amplifier block 622 may be shared by the sub arrays 614 and 615.

In the sub array 614 in the first sub array group 511, when one word line WL1 is enabled, data of the memory cells connected to the word line WL1 may be bit line sense amplifier blocks 621 and 622. Can be sensed and amplified. In this case, the sub array 613 connected to the bit line sense amplifier block 621 and the sub array 615 connected to the bit line sense amplifier block 622 should be deactivated. That is, subarrays 613 and 615 adjacent to the subarray 614 to be activated should be deactivated. The subarrays 613 and 615 that are deactivated may be referred to as a keep away zone.

The first sub array group 511 may activate a sub array, eg, the sub array 612, in an area outside the keep away zone of the activated sub array 614. When the sub array 612 is activated, the sub arrays 611 and 613 adjacent to the sub array 612 belong to the keep away zone and must be deactivated.

Meanwhile, the sub array 618 in the first sub array group 511 may be activated. The sub array 618 of the first sub array group 511 is adjacent to the second sub array group 512. When the subarray 618 of the first subarray group 511 is activated, the subarray 617 of the first subarray group 511 and the subarray 631 of the second subarray group 512 are kept away. It belongs to the zone and must be deactivated.

Defective cells may occur in the subarrays 611 - 618 in the first subarray group 511. Each of the subarrays 611-618 may include redundancy cells for repairing defective cells. Each of the sub arrays 611-618 may replace a defective cell generated in the sub array with a redundancy cell of the sub array. In addition, the subarrays 611-618 may replace defective cells generated in the subarrays with redundancy cells of other subarrays. The other sub array to be replaced may be limited to belonging to the first sub array group 511. That is, the first sub array group 511 may be set to have repair flexibility within the first sub array group 511.

The second sub array group 512 may also be set to have relief flexibility within the second sub array group 512. Each of the sub arrays in the second sub array group 512 may include redundancy cells for repairing defective cells. The defective cell occurring in each sub array in the second sub array group 512 may be replaced with a redundancy cell of the corresponding sub array. The defective cells occurring in each sub array in the second sub array group 512 may be replaced with redundancy cells of another sub array.

The first and second subarray groups 511 and 512 may reduce the size of the subarray group by reducing the number of subarrays 611 to 618. Accordingly, the number of subarray groups may be increased to increase parallelism efficiency. On the other hand, the number of subarrays in the subarray group may reduce the relief flexibility. It can be seen that there is a trade-off between subarray size granularity and rescue flexibility.

The size of the sub array group may be stored in a storage unit (not shown) in the memory device 500. The storage unit may include a nonvolatile device configured as a fuse or an antifuse. The size of the subarray group can be set to a sufficiently large number that includes all the subarrays. In addition, the size of the sub array group may be specified according to the user purpose.

The first and second sub-array groups 511 and 512 may be connected to as many row decoders or latch type word line drivers as are simultaneously enabled in order to enable a plurality of word lines at the same time. Since having a plurality of row decoders can be a heavy burden in terms of chip area, a latch type wordline driver can be employed.

Each of the first and second sub array groups 511 and 512 includes a plurality of sub arrays, and the sub arrays are designed to share data input / output lines (not shown) and data line sense amplifier blocks (not shown). . Operation commands may be sequentially applied to different sub arrays. Since the sub arrays share data input / output lines, timing constraints may exist in instruction combinations applied to different sub arrays.

FIG. 7 is a diagram illustrating timing constraints for successive commands of different subarrays of FIG. 6.

Referring to FIG. 7, one of the plurality of sub arrays 611-618 in the first sub array group 511 of FIG. 6 is referred to as a sub array A, and the other sub array is referred to as a sub array B. . Looking at the timing between the current command of sub array A and the next command of sub array B, there is no timing restriction between the active command ACT of sub array A and the active command ACT of sub array B. This is because the active command ACT belongs to a row command, so that collisions with respect to the paths of the data input / output lines shared by the sub array A and the sub array B do not occur.

There is no timing restriction between the active command ACT of the sub array A and the precharge command PRE of the sub array B. There is no timing limitation between the active command ACT of the sub array A and the refresh command REF of the sub array B. This is because, like the active command ACT, the precharge command PRE and the refresh command REF belong to the low command, so that data input / output line collision does not occur.

The write / read command WR / RD of the sub array B is not valid after the active command ACT of the sub array A. Because the column select line is on during the write or read command, and the path to the data input / output line is formed by the column select line, two words in different sub arrays in the sub array group sharing the data input / output line. This is because the lines cannot be enabled at the same time. In other words, an active command may have been previously performed to perform the write / read command (WR / RD) in the sub array B, which is not valid because the word lines are written / read in two enabled states at the same time.

After the precharge command PRE of the sub array A, there is no timing restriction between the active command ACT, the precharge command PRE or the refresh command REF of the sub array B.

A precharge-to-write time interval tPRE2WR is required between the subarray B's write command WR after the subarray A's precharge command PRE. After the precharge command PRE of the sub array A, the precharge-to-read time period tPRE2RD is required between the read commands RD of the sub array B. When one word line is turned off by the precharge command PRE in the sub array A, one word line enable for the write or read operation in the sub array B becomes possible. The tPRE2WR time and tPRE2RD time can be viewed as the time taken for the word line of sub array A to turn off.

After the refresh command REF of the sub array A, there is no timing restriction between the active command ACT, the precharge command PRE or the refresh command REF of the sub array B.

After the refresh command REF of the sub array A, the refresh-to-write time tREF2WR interval is required between the write commands WR of the sub array B. After the refresh command REF of the sub array A, a refresh-to-read time period tREF2RD is required between the read commands RD of the sub array B. If one word line is active by the write / read command of sub array B while one word line is refreshed by the refresh command REF of sub array A, if one word line is off after refresh, the sub array One word line enable for write or read operation in B is enabled. The tREF2WR time and tREF2RD time can be viewed as the time taken for the word line of sub array A to turn off.

A write-to-active time tWR2ACT interval is required between the write command WR of the sub array A and the active command ACT of the sub array B. A read-to-active time tRD2ACT interval is required between the read command RD of the sub array A and the active command ACT of the sub array B. If the column select line is turned off when data is written to the memory cell by the write / read command (WR / RD) of the sub array A or the read data is latched to the data line sense amplifier, the active operation in the sub array B becomes possible. . The tWR2ACT time and tRD2ACT time can be viewed as the time taken for the column select line of sub array A to turn off.

The precharge command PRE or the write / read command WR / RD of the sub array B is not valid after the write / read command WR / RD of the sub array A. This is because two word lines may not be enabled at the same time in different sub arrays in a sub array group sharing data input / output lines.

After the write command WR of the sub array A, a write-to-refresh time period tWR2REF is required between the refresh commands REF of the sub array B. A read-to-refresh time interval tRD2REF is required between the read command RD of the sub array A and the refresh command REF of the sub array B. FIG. When the column select line is turned off by the write / read command WR / RD of the sub array A, the refresh operation in the sub array B becomes possible. The tWR2REF time and tRD2REF time can be seen as the time taken for the column select line of sub array A to turn off.

FIG. 8 is a block diagram illustrating a first example of a memory system that may be used to implement one or more hidden timing parameter management method embodiments described herein.

Referring to FIG. 8, the memory system 800 includes a memory controller 810 and a memory module 820. The memory controller 810 may provide the command signals CMD, the address signals ADDR, and the data DQ to the memory module 820. The memory module 820 may include a plurality of memory devices 100 and a buffer chip 822. The memory module 820 may further include a nonvolatile memory device 824.

For example, nine memory devices 100 may be mounted in the memory module 820. One of the nine memory devices 100 may be used to correct an error occurring in the remaining eight memory devices 100. That is, in order to correct a 1-bit error generated in each of the eight memory devices 100, an 8-bit parity bit is required. For this purpose, one memory device 100 may be used. Accordingly, X72 data DQ, which is the sum of X8 data DQ input and output to and from each memory device 100, may be transferred between the memory controller 810 and the memory module 820.

The memory devices 100 may be memory devices that operate in the sub-bank interleaving method described with reference to FIGS. 1 and 4. The memory device 100 may include a plurality of banks composed of at least two subbanks. The memory device 100 may operate to interleave subbanks in one bank of the plurality of banks one by one in succession.

The memory device 100 may shorten a continuous data write operation in one bank to a tRRD time interval that is a low active-to-low active time between different banks. Accordingly, the data write operation in one bank may be performed by changing the memory cell data write time tWR ', the time between application of the / RAS signal and the application of the / CAS signal tRCD' or the bit line precharge time tRP '. You can have long. The tRCD ', tWR', and tRP 'times are not included in the interval time interval of successive data write operations of the subbanks. In continuous data write operation timing, the host, e.g., the memory controller, does not need to comply with the tRCD ', tWR', tRP 'timing parameter specifications. The tRCD ', tWR', and tRP 'times can be hidden from the memory controller.

In addition, the memory device 100 may be a memory device 500 including a plurality of banks in which memory cell array blocks including at least two sub-array groups described in FIG. 5 are stacked. The memory device 100 may activate a subarray of an area outside the keep away zone of the activated subarray in the subarray group. In addition, when a sub array belonging to the keep away zone belongs to another sub array group, the sub array belonging to another sub array group may be deactivated. The memory device 100 may replace defective cells generated in sub arrays in a sub array group with redundancy cells of the sub array or another sub array in the sub array group. The memory device 100 may have timing limitations in command combinations that are successively applied to different sub arrays.

The buffer chip 822 may receive the command signals CMD and the address signal ADDR from the memory controller 810 and transmit them to the memory devices 100. When the interface speed with the memory controller 810 is extremely high, performance degradation caused by the speed difference may be minimized through the buffer chip 822.

In addition, the buffer chip 822 may control the operation of the memory device 100 to be selectively relaxed. The buffer chip 822 monitors whether the received command signal CMD and the address signal ADDR access subbanks in one bank of the memory device 100.

The buffer chip 822 may monitor the MSB signal RA _MSB of the row address signal that selects the subbanks of the memory device 100. When the subbanks are accessed, the buffer chip 822 may perform the memory cell data write time tWR 'during the data write operation in one bank, the time tRCD' or the bit between the / RAS signal application and the / CAS signal application. The memory device 100 may be reflexively operated to have a long line precharge time tRP ′.

The nonvolatile memory device 824 may store the size of the subarray group of the memory device 500 (that is, the number of subarrays included in the subarray group). The nonvolatile memory device 824 may be configured as a fuse, an antifuse, a PROM, a flash memory, or the like. The size of the subarray group stored in the nonvolatile memory device 824 may be provided to the memory controller 810 at power-up.

The memory controller 810 may calculate row address bits that divide each sub array group and a row address that is a boundary between each sub array using the sub array group information of the memory device 100. Accordingly, the memory controller 810 may activate a sub array in an area outside the keep away zone of the activated sub array in the sub array group of the memory device 100. In addition, when a sub array belonging to the keep away zone belongs to another sub array group, the sub array may be deactivated. The memory controller 810 may replace defective cells generated in the sub arrays in the sub array group of the memory device 100 with redundancy cells of the sub array or another sub array in the sub array group. The memory controller 810 may observe timing restrictions present in command combinations that are successively applied to different sub arrays of the memory device 100.

FIG. 9 is a block diagram illustrating a second example of a memory system that may be used to implement one or more hidden timing parameter management method embodiments described herein.

Referring to FIG. 9, the memory system 900 includes a plurality of hosts 901 and 902, a memory controller 910, and a memory device 100. The hosts 901 and 902 may be configured as microprocessors or the like. The memory controller 910 may control the memory device 100 according to a read or write command RD / WR requested from the hosts 901 and 902. The memory controller 910 may generate a command signal CMD and an address signal ADDR based on the read or write commands RD / WR of the hosts 901 and 902 and transmit them to the memory device 100. Also, the memory controller 910 may transmit / receive data DQ according to the read or write command RD / WR of the hosts 901 and 902 to / from the memory device 100.

The memory devices 100 may be memory devices that operate in the sub-bank interleaving method described with reference to FIGS. 1 and 4. The memory device 100 may include a plurality of banks composed of at least two subbanks. The memory device 100 may operate to interleave subbanks in one bank of the plurality of banks one by one in succession.

The memory device 100 may shorten a continuous data write operation in one bank to a tRRD time interval that is a low active-to-low active time between different banks. Accordingly, the data write operation in one bank may be performed by changing the memory cell data write time tWR ', the time between application of the / RAS signal and the application of the / CAS signal tRCD' or the bit line precharge time tRP '. You can have long. The tRCD ', tWR', and tRP 'times are not included in the interval time interval of successive data write operations of the subbanks. In the timing of successive data write operations of the sub banks, the memory controller 710 does not need to comply with the tRCD ', tWR', and tRP 'timing parameter specifications. The tRCD ', tWR', and tRP 'times may be hidden from the memory controller 910.

In addition, the memory device 100 may be a memory device 500 including a plurality of banks in which memory cell array blocks including at least two sub-array groups described in FIG. 5 are stacked. The memory device 100 may activate a subarray of an area outside the keep away zone of the activated subarray in the subarray group. In addition, when a sub array belonging to the keep away zone belongs to another sub array group, the sub array belonging to another sub array group may be deactivated. The memory device 100 may replace defective cells generated in sub arrays in a sub array group with redundancy cells of the sub array or another sub array in the sub array group. The memory device 100 may have timing limitations in command combinations that are successively applied to different sub arrays.

The memory controller 910 may convert the command signal CMD and the address signal ADDR of the memory device 100 according to a read or write command Rd / WR requested from the hosts 901 and 902. The memory controller 910 may include a transaction queue 911, a command queue 915, and a monitoring unit 916. The transaction queue 911 includes an ordering unit 912 for ordering a read or write command (RD / WR) requested from a plurality of hosts 901 and 902, and a read or write of the hosts 901 and 902. The logic unit 913 may generate the command RD / WR as a command signal CMD and an address signal ADDR of the memory device 100. The command queue 915 may sequentially store the command signal CMD and the address signal ADDR generated through the logic unit 913, and then transmit them to the memory device 100.

The monitoring unit 916 may determine whether to access subbanks in one bank of the memory device 100 by monitoring the command signal CMD and the address signal ADDR stored in the command queue 915. The monitoring unit 916 may monitor the MSB signal RA _MSB of the row address signal that selects the subbanks of the memory device 100. When the sub banks are accessed, the monitoring unit 916 performs the memory cell data write time tWR 'during the data write operation in one bank, the time tRCD' or the bit between the / RAS signal application and the / CAS signal application. The memory device 100 may be reflexively operated to have a long line precharge time tRP ′.

The memory controller 910 can calculate the row address to be a boundary between each subarray and the row address bits for distinguishing each subarray group using the subarray group information of the memory device 100. [ Accordingly, the memory controller 910 may activate a sub array in an area outside the keep away zone of the activated sub array in the sub array group of the memory device 100. In addition, when a sub array belonging to the keep away zone belongs to another sub array group, the sub array may be deactivated. The memory controller 910 may replace defective cells generated in the sub arrays in the sub array group of the memory device 100 with redundancy cells of the sub array or another sub array in the sub array group. The memory controller 910 may observe timing limitations present in command combinations that are sequentially applied to different sub arrays of the memory device 100.

As shown in FIG. 10, the memory controller 910 complies with whether the memory device 100 operates in accordance with the timing parameter definition in the data write operation. When the memory device 100 operates in the bank interleaving method of FIG. 3A, the memory controller 910 may, for example, tWR time and tRP among data write operation timings after inputting predetermined write data DIN and before the next active command. Observe the time regulations. The tWR time may be defined, for example, at least 15 ns, and the tRP time may be defined, for example, at least 15 ns.

When the memory device 100 operates in the sub-bank interleaving method of FIGS. 3B to 3D, for example, when different subbanks are selected by toggling the MSB signal RA _MSB of the row address signal, the memory controller 910. ) Does not have to comply with the tWR time regulation and the tRP time regulation among the data write operation timings. In this case, the tWR time of the memory device 100 that the memory controller 910 observes may be defined as 0 ns, and the tRP time may also be defined as 0 ns. As the tRP time is defined as 0 ns, the precharge operation actually operated in the memory device 100 becomes a hidden precharge operation.

Meanwhile, even when the memory device 100 operates in the sub bank interleaving method of FIGS. 3B to 3D, the same subbanks may be selected because the MSB signal RA _MSB of the row address signal is not toggled. In this case, the memory device 100 may be regarded to operate similarly to the continuous same bank access operation in the bank interleaving method. The memory controller 910 needs to comply with the tWR time rule and the tRP time rule among the data write operation timings. In this case, the tWR time of the memory device 100 that the memory controller 910 observes may be defined, for example, at least 25 ns, and the tRP time may be defined, for example, at least 15 ns.

The memory device implementing the at least one hidden timing parameter management method described herein may be included in a semiconductor memory device such as the DDR-SDRAM as shown in FIG.

Referring to FIG. 11, the DDR-SDRAM 1100 may include a memory cell array 1101 including DRAM cells and various circuit blocks for driving DRAM cells. For example, the timing register 1102 may be activated when the chip select signal CS is changed from an inactivation level (eg, logic high) to an activation level (eg, logic low). The timing register 1202 includes a clock signal CLK, a clock enable signal CKE, a chip select signal CSB, a row address strobe signal RABS, and a column address strobe signal CASB from an external source. And various internal command signals LRAS for receiving a command signal such as a write enable signal WEB and a data input / output mask signal DQM, and processing the received command signal to control circuit blocks. LCBR, LWE, LCAS, LWCBR, LDQM) can be generated.

Some internal command signals generated from timing register 1102 are stored in programming register 1204. For example, latency information, burst length information, and the like related to data output may be stored in the programming register 1104. The internal command signals stored in the programming register 1104 may be provided to the latency / burst length control unit 1106, and the latency / burst length control unit 1106 may control a control signal for controlling the latency or burst length of the data output in the column buffer. The column decoder 1110 or the output buffer 1112 may be provided through the 1108.

The address register 1120 may receive the address signal ADD from the outside. The row address signal may be provided to the row decoder 1124 through the row address buffer 1122. In addition, the column address signal may be provided to the column decoder 1110 through the column address buffer 1108. The row address buffer 1122 may further receive a refresh address signal generated by the refresh counter in response to the refresh commands LRAS and LCBR, and provide either the row address signal or the refresh address signal to the row decoder 1124. can do. In addition, the address register 1120 may provide a bank signal for selecting a bank to the bank selector 1126.

The row decoder 1124 may decode a row address signal or a refresh address signal input from the row address buffer 1122, and activate a word line of the memory cell array 1101. The column decoder 1110 may decode the column address signal and perform a selection operation on the bit line of the memory cell array 1101. For example, a column selection line may be applied to the semiconductor memory device 1100 to perform a selection operation through the column selection line.

The sense amplifier 1130 may amplify data of a memory cell selected by the row decoder 1124 and the column decoder 1110 and provide the amplified data to the output buffer 1112. Data for writing a data cell is provided to the memory cell array 1101 through the data input register 1132, and the input / output controller 1134 may control a data transfer operation through the data input register 1132.

The memory cell array 1101 may include a plurality of banks composed of at least two subbanks. In the memory cell array 1101, subbanks in any one of the plurality of banks can be successively interleaved one by one. Consecutive data write operations in one bank can be shortened to a tRRD time interval, which is a low active-to-low active time between different banks. Accordingly, the data write operation in one bank may be performed by changing the memory cell data write time tWR ', the time between application of the / RAS signal and the application of the / CAS signal tRCD' or the bit line precharge time tRP '. You can have long. The tRCD ', tWR', and tRP 'times are not included in the interval time interval of successive data write operations of the subbanks. In the timing of successive data write operations of the subbanks, the memory controller does not need to comply with the tRCD ', tWR', and tRP 'timing parameter specifications. The tRCD ', tWR', and tRP 'times can be hidden from the memory controller.

In addition, the memory cell array 1101 may include a plurality of banks in which memory cell array blocks composed of two or more sub-array groups are stacked. In the memory cell array 1101, a subarray of an area outside the keep away zone of an activated subarray in a subarray group may be activated. In addition, when a sub array belonging to the keep away zone belongs to another sub array group, the sub array belonging to another sub array group may be deactivated. In the memory cell array 1101, defective cells generated in the sub arrays in the sub array group may be replaced with redundancy cells of the sub array or another sub array in the sub array group. In the memory cell array 1101, timing restrictions may exist in instruction combinations that are sequentially applied to different sub arrays.

FIG. 12 is a diagram illustrating an implementation example of a memory system to which the semiconductor memory device of FIG. 11 is applied.

Referring to FIG. 12, the memory system 1200 may include a memory module 1210 and a memory controller 1220. The memory module 1210 may mount at least one semiconductor memory device 1230 on a module board. The semiconductor memory device 1230 may be implemented with a DRAM chip, and each semiconductor memory device 1230 may include a plurality of semiconductor layers. The semiconductor layers may include one or more master chips 1231 and one or more slave chips 1232. The signal transfer between the semiconductor layers may be performed through through silicon vias (TSVs).

The master chip 1231 and the slave chip 1232 may include the memory device 100 according to embodiments of the present invention. The memory devices 100 may be memory devices that operate in the sub-bank interleaving method described with reference to FIGS. 1 and 4. The memory device 100 may include a plurality of banks composed of at least two subbanks. The memory device 100 may operate to interleave subbanks in one bank of the plurality of banks one by one in succession.

The memory device 100 may shorten a continuous data write operation in one bank to a tRRD time interval that is a low active-to-low active time between different banks. Accordingly, the data write operation in one bank may be performed by changing the memory cell data write time tWR ', the time between application of the / RAS signal and the application of the / CAS signal tRCD' or the bit line precharge time tRP '. You can have long. The tRCD ', tWR', and tRP 'times are not included in the interval time interval of successive data write operations of the subbanks. In the timing of successive data write operations of the subbanks, the memory controller does not need to comply with the tRCD ', tWR', and tRP 'timing parameter specifications. The tRCD ', tWR', and tRP 'times can be hidden from the memory controller.

In addition, the memory device 100 may be a memory device 500 including a plurality of banks in which memory cell array blocks including at least two sub-array groups described in FIG. 5 are stacked. The memory device 100 may activate a subarray of an area outside the keep away zone of the activated subarray in the subarray group. In addition, when a sub array belonging to the keep away zone belongs to another sub array group, the sub array belonging to another sub array group may be deactivated. The memory device 100 may replace defective cells generated in sub arrays in a sub array group with redundancy cells of the sub array or another sub array in the sub array group. The memory device 100 may have timing limitations in command combinations that are successively applied to different sub arrays.

The memory module 1210 may communicate with the memory controller 1220 through a system bus. The data DQ, the command / address CMD / ADD, and the clock signal CLK may be transmitted and received between the memory module 1210 and the memory controller 1220 through the system bus.

FIG. 13 is a block diagram illustrating a computing system having a memory system according to an example embodiment. Referring to FIG.

Referring to FIG. 13, a semiconductor memory device of the present invention may be mounted as a RAM 1320 in a computing system 1300 such as a mobile device or a desktop computer. The semiconductor memory device mounted as the RAM 1320 may have any one of the above-described embodiments. For example, the RAM 1320 may be a semiconductor memory device, or may be applied in the form of a memory module. In addition, the RAM 1320 may be a concept including a semiconductor memory device and a memory controller.

The computing system 1300 according to an embodiment of the present invention includes a central processing unit 1310, a RAM 1320, a user interface 1330, and a nonvolatile memory 1340, each of which is a bus 1350. Is electrically connected). The nonvolatile memory 1340 may use a mass storage device such as an SSD or an HDD.

In the computing system 1300, the RAM 1320 may include a memory device 100 according to embodiments of the present invention. The memory devices 100 may be memory devices that operate in the sub-bank interleaving method described with reference to FIGS. 1 and 4. The memory device 100 may include a plurality of banks composed of at least two subbanks. The memory device 100 may operate to interleave subbanks in one bank of the plurality of banks one by one in succession.

The memory device 100 may shorten a continuous data write operation in one bank to a tRRD time interval that is a low active-to-low active time between different banks. Accordingly, the data write operation in one bank may be performed by changing the memory cell data write time tWR ', the time between application of the / RAS signal and the application of the / CAS signal tRCD' or the bit line precharge time tRP '. You can have long. The tRCD ', tWR', and tRP 'times are not included in the interval time interval of successive data write operations of the subbanks. In the timing of successive data write operations of the sub banks, the memory controller 710 does not need to comply with the tRCD ', tWR', and tRP 'timing parameter specifications. The tRCD ', tWR', and tRP 'times may be hidden from the memory controller 710.

In addition, the memory device 100 may be a memory device 500 including a plurality of banks in which memory cell array blocks including at least two sub-array groups described in FIG. 5 are stacked. The memory device 100 may activate a subarray of an area outside the keep away zone of the activated subarray in the subarray group. In addition, when a sub array belonging to the keep away zone belongs to another sub array group, the sub array belonging to another sub array group may be deactivated. The memory device 100 may replace defective cells generated in sub arrays in a sub array group with redundancy cells of the sub array or another sub array in the sub array group. The memory device 100 may have timing limitations in command combinations that are successively applied to different sub arrays.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (20)

A plurality of banks in which a plurality of memory cells are arranged;
Each of the banks includes at least two subbanks,
In a subbank interleaving scheme in which the subbanks in the one bank are sequentially operated one by one, continuous operation between the subbanks conforms to a low active-to-low active time (tRRD) interval between the different banks. And a memory device. The method of claim 1,
And the subbanks are selectively accessed using one or more bits of row address signals addressing the memory cells. The method of claim 1,
The data write time tWR to the memory cell in the continuous data write operation between the sub banks is set to be longer than the data write time to the memory cell in the continuous data write operation between the banks. Device. The method of claim 3,
And a data write time (tWR) to the memory cells is not included in an interval time interval of successive data write operations between the subbanks. The method of claim 1,
The bit line precharge time tRP of the memory cell is set longer than the bit line precharge time of the memory cell in successive data write operations between the subbanks. Memory device, characterized in that. The method of claim 5,
And the bit line precharge time (tRP) of the memory cells is not included in an interval time interval of successive data write operations between the subbanks. The method of claim 1,
The time tRCD between the row active command and the column active command in the continuous data write operation between the sub banks is set longer than the time between the row active command and the column active command in the continuous data write operation between the banks. Memory device, characterized in that. The method of claim 7, wherein
And a time tRCD between the row active command and the column active command is not included in an interval time interval of successive data write operations between the subbanks. The method of claim 1,
And the sub banks are arranged in a direction in which word lines of the memory cells are arranged. The method of claim 1,
And the sub banks are arranged in a direction in which bit lines of the memory cells are arranged. The method of claim 1,
And the sub banks are connected to independent data line sense blocks and data input / output lines. A plurality of banks in which a plurality of memory cells are arranged;
Each of the banks comprises a plurality of sub-arrays,
Dividing the sub arrays into at least two sub array groups, and complying with timing restrictions between successive instruction combinations applied to the sub arrays included in each of the sub array groups. The method of claim 12, wherein the sub-array groups
And is selectively accessed using one or more bits of the row address signals addressing the memory cells. The memory device of claim 12, wherein the memory device
And when one of the subarrays in the subarray group is activated, the subarrays adjacent to the activated subarray are deactivated belonging to a keep away zone. 15. The method of claim 14, wherein the memory device
And when the sub array belonging to the keep away zone belongs to another sub array group, the sub array belonging to the other sub array group is deactivated. The memory device of claim 12, wherein the memory device
And when a defective cell is generated in the subarray in the subarray group, replacing the defective cell with redundancy cells of the subarray or another subarray in the corresponding subarray group. The memory device of claim 12, wherein the memory device
And a storage unit which stores the size of the sub array group indicating the number of the sub arrays included in each of the sub array groups. The method of claim 17, wherein the storage unit
A nonvolatile device comprising a fuse or an anti-fuse. The method of claim 12, wherein each of the sub array groups
And a data line sense block and data input / output lines that are independent from each other. 13. The method of claim 12, wherein the timing constraints are
And in the sub arrays to which the consecutive commands are applied, a time at which the column select line of the sub array operating on the previous command is turned off.

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